lxdream 0.9.1| filename | src/pvr2/pvr2.c |
| changeset | 1157:20053990db61 |
| prev | 1080:5b17c9900d9e |
| next | 1280:38f2b0e60261 |
| author | nkeynes |
| date | Tue Feb 28 18:22:52 2012 +1000 (12 years ago) |
| permissions | -rw-r--r-- |
| last change | Add a GL-only video driver for android usage (since the Java code is responsible for creating the context) |
| view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include <assert.h>
21 #include "dream.h"
22 #include "eventq.h"
23 #include "display.h"
24 #include "mem.h"
25 #include "asic.h"
26 #include "clock.h"
27 #include "pvr2/pvr2.h"
28 #include "pvr2/pvr2mmio.h"
29 #include "pvr2/scene.h"
30 #include "sh4/sh4.h"
31 #define MMIO_IMPL
32 #include "pvr2/pvr2mmio.h"
34 #define MAX_RENDER_BUFFERS 4
36 #define HPOS_PER_FRAME 0
37 #define HPOS_PER_LINECOUNT 1
39 static void pvr2_init( void );
40 static void pvr2_reset( void );
41 static uint32_t pvr2_run_slice( uint32_t );
42 static void pvr2_save_state( FILE *f );
43 static int pvr2_load_state( FILE *f );
44 static void pvr2_update_raster_posn( uint32_t nanosecs );
45 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
46 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
47 static render_buffer_t pvr2_next_render_buffer( );
48 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
49 uint32_t pvr2_get_sync_status();
50 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
51 static int render_colour_formats[8] = {
52 COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
53 COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
56 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
57 pvr2_run_slice, NULL,
58 pvr2_save_state, pvr2_load_state };
61 display_driver_t display_driver = NULL;
63 struct pvr2_state {
64 uint32_t frame_count;
65 uint32_t line_count;
66 uint32_t line_remainder;
67 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
68 uint32_t irq_hpos_line;
69 uint32_t irq_hpos_line_count;
70 uint32_t irq_hpos_mode;
71 uint32_t irq_hpos_time_ns; /* Time within the line */
72 uint32_t irq_vpos1;
73 uint32_t irq_vpos2;
74 uint32_t odd_even_field; /* 1 = odd, 0 = even */
75 int32_t palette_changed; /* TRUE if palette has changed since last render */
76 /* timing */
77 uint32_t dot_clock;
78 uint32_t total_lines;
79 uint32_t line_size;
80 uint32_t line_time_ns;
81 uint32_t vsync_lines;
82 uint32_t hsync_width_ns;
83 uint32_t front_porch_ns;
84 uint32_t back_porch_ns;
85 uint32_t retrace_start_line;
86 uint32_t retrace_end_line;
87 int32_t interlaced;
88 } pvr2_state;
90 static gchar *save_next_render_filename;
91 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
92 static uint32_t render_buffer_count = 0;
93 static render_buffer_t displayed_render_buffer = NULL;
94 static uint32_t displayed_border_colour = 0;
96 /**
97 * Event handler for the hpos callback
98 */
99 static void pvr2_hpos_callback( int eventid ) {
100 asic_event( eventid );
101 pvr2_update_raster_posn(sh4r.slice_cycle);
102 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
103 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
104 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
105 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
106 }
107 }
108 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
109 pvr2_state.irq_hpos_time_ns );
110 }
112 /**
113 * Event handler for the scanline callbacks. Fires the corresponding
114 * ASIC event, and resets the timer for the next field.
115 */
116 static void pvr2_scanline_callback( int eventid )
117 {
118 asic_event( eventid );
119 pvr2_update_raster_posn(sh4r.slice_cycle);
120 if( eventid == EVENT_SCANLINE1 ) {
121 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
122 } else {
123 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
124 }
125 }
127 static void pvr2_gunpos_callback( int eventid )
128 {
129 pvr2_update_raster_posn(sh4r.slice_cycle);
130 int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
131 MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
132 asic_event( EVENT_MAPLE_DMA );
133 }
135 static void pvr2_init( void )
136 {
137 int i;
138 register_io_region( &mmio_region_PVR2 );
139 register_io_region( &mmio_region_PVR2PAL );
140 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
141 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
142 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
143 register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
144 texcache_init();
145 pvr2_reset();
146 pvr2_ta_reset();
147 save_next_render_filename = NULL;
148 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
149 render_buffers[i] = NULL;
150 }
151 render_buffer_count = 0;
152 displayed_render_buffer = NULL;
153 displayed_border_colour = 0;
154 }
156 static void pvr2_reset( void )
157 {
158 int i;
159 pvr2_state.line_count = 0;
160 pvr2_state.line_remainder = 0;
161 pvr2_state.cycles_run = 0;
162 pvr2_state.irq_vpos1 = 0;
163 pvr2_state.irq_vpos2 = 0;
164 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
165 pvr2_state.back_porch_ns = 4000;
166 pvr2_state.palette_changed = FALSE;
167 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
168 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
169 mmio_region_PVR2_write( YUV_ADDR, 0 );
170 mmio_region_PVR2_write( YUV_CFG, 0 );
172 pvr2_ta_init();
173 texcache_flush();
174 if( display_driver ) {
175 display_driver->display_blank(0);
176 for( i=0; i<render_buffer_count; i++ ) {
177 display_driver->destroy_render_buffer(render_buffers[i]);
178 render_buffers[i] = NULL;
179 }
180 render_buffer_count = 0;
181 }
182 }
184 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
185 {
186 struct frame_buffer fbuf;
188 fbuf.width = buffer->width;
189 fbuf.height = buffer->height;
190 fbuf.rowstride = fbuf.width*3;
191 fbuf.colour_format = COLFMT_BGR888;
192 fbuf.inverted = buffer->inverted;
193 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
195 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
196 write_png_to_stream( f, &fbuf );
197 g_free( fbuf.data );
199 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
200 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
201 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
202 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
203 int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
204 fwrite( &flushed, sizeof(flushed), 1, f );
206 }
208 render_buffer_t pvr2_load_render_buffer( FILE *f, gboolean *status )
209 {
210 frame_buffer_t frame = read_png_from_stream( f );
211 if( frame == NULL ) {
212 *status = FALSE;
213 return NULL;
214 }
215 *status = TRUE;
217 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
218 if( buffer != NULL ) {
219 int32_t flushed;
220 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
221 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
222 fread( &buffer->address, sizeof(buffer->address), 1, f );
223 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
224 fread( &flushed, sizeof(flushed), 1, f );
225 buffer->flushed = (gboolean)flushed;
226 } else {
227 fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
228 sizeof(buffer->address)+sizeof(buffer->scale)+
229 sizeof(int32_t), SEEK_CUR );
230 }
231 return buffer;
232 }
237 void pvr2_save_render_buffers( FILE *f )
238 {
239 int i;
240 uint32_t has_frontbuffer;
241 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
242 if( displayed_render_buffer != NULL ) {
243 has_frontbuffer = 1;
244 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
245 pvr2_save_render_buffer( f, displayed_render_buffer );
246 } else {
247 has_frontbuffer = 0;
248 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
249 }
251 for( i=0; i<render_buffer_count; i++ ) {
252 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
253 pvr2_save_render_buffer( f, render_buffers[i] );
254 }
255 }
256 }
258 gboolean pvr2_load_render_buffers( FILE *f )
259 {
260 uint32_t count, has_frontbuffer;
261 gboolean loadok;
262 int i;
264 fread( &count, sizeof(count), 1, f );
265 if( count > MAX_RENDER_BUFFERS ) {
266 return FALSE;
267 }
268 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
269 for( i=0; i<render_buffer_count; i++ ) {
270 display_driver->destroy_render_buffer(render_buffers[i]);
271 render_buffers[i] = NULL;
272 }
273 render_buffer_count = 0;
275 if( has_frontbuffer ) {
276 displayed_render_buffer = pvr2_load_render_buffer(f, &loadok);
277 if( displayed_render_buffer != NULL )
278 display_driver->display_render_buffer( displayed_render_buffer );
279 else if( !loadok )
280 return FALSE;
281 count--;
282 }
284 for( i=0; i<count; i++ ) {
285 pvr2_load_render_buffer( f, &loadok );
286 if( !loadok )
287 return FALSE;
288 }
289 return TRUE;
290 }
293 static void pvr2_save_state( FILE *f )
294 {
295 pvr2_save_render_buffers( f );
296 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
297 pvr2_ta_save_state( f );
298 pvr2_yuv_save_state( f );
299 }
301 static int pvr2_load_state( FILE *f )
302 {
303 if( !pvr2_load_render_buffers(f) )
304 return 1;
305 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
306 return 1;
307 if( pvr2_ta_load_state(f) ) {
308 return 1;
309 }
310 return pvr2_yuv_load_state(f);
311 }
313 /**
314 * Update the current raster position to the given number of nanoseconds,
315 * relative to the last time slice. (ie the raster will be adjusted forward
316 * by nanosecs - nanosecs_already_run_this_timeslice)
317 */
318 static void pvr2_update_raster_posn( uint32_t nanosecs )
319 {
320 uint32_t old_line_count = pvr2_state.line_count;
321 if( pvr2_state.line_time_ns == 0 ) {
322 return; /* do nothing */
323 }
324 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
325 pvr2_state.cycles_run = nanosecs;
326 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
327 pvr2_state.line_count ++;
328 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
329 }
331 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
332 pvr2_state.line_count -= pvr2_state.total_lines;
333 if( pvr2_state.interlaced ) {
334 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
335 }
336 }
337 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
338 (old_line_count < pvr2_state.retrace_end_line ||
339 old_line_count > pvr2_state.line_count) ) {
340 pvr2_state.frame_count++;
341 pvr2_next_frame();
342 pvr2_draw_frame();
343 }
344 }
346 static uint32_t pvr2_run_slice( uint32_t nanosecs )
347 {
348 pvr2_update_raster_posn( nanosecs );
349 pvr2_state.cycles_run = 0;
350 return nanosecs;
351 }
353 int pvr2_get_frame_count()
354 {
355 return pvr2_state.frame_count;
356 }
358 void pvr2_draw_frame()
359 {
360 if( display_driver != NULL && display_driver != &display_null_driver ) {
361 if( displayed_render_buffer == NULL ) {
362 display_driver->display_blank(displayed_border_colour);
363 } else {
364 display_driver->display_render_buffer(displayed_render_buffer);
365 }
366 }
367 }
369 gboolean pvr2_save_next_scene( const gchar *filename )
370 {
371 if( save_next_render_filename != NULL ) {
372 g_free( save_next_render_filename );
373 }
374 save_next_render_filename = g_strdup(filename);
375 return TRUE;
376 }
380 /**
381 * Advance to the next frame, copying the current contents of video ram to
382 * the window. If the video configuration has changed, first recompute the
383 * new frame size/depth.
384 */
385 void pvr2_next_frame( void )
386 {
387 int dispmode = MMIO_READ( PVR2, DISP_MODE );
388 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
389 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
391 if( !bEnabled ) {
392 /* Output disabled == black */
393 displayed_render_buffer = NULL;
394 displayed_border_colour = 0;
395 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
396 /* Enabled but blanked - border colour */
397 displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
398 displayed_render_buffer = NULL;
399 } else {
400 /* Real output - determine dimensions etc */
401 struct frame_buffer fbuf;
402 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
403 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
404 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
406 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
407 fbuf.width = (vid_ppl << 2) / colour_formats[fbuf.colour_format].bpp;
408 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
409 fbuf.size = (vid_ppl << 2) * fbuf.height;
410 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
412 /* Determine the field to display, and deinterlace if possible */
413 if( pvr2_state.interlaced ) {
414 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
415 fbuf.height = fbuf.height << 1;
416 fbuf.rowstride = vid_ppl << 2;
417 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
418 } else {
419 /* Just display the field as is, folks. This is slightly tricky -
420 * we pick the field based on which frame is about to come through,
421 * which may not be the same as the odd_even_field.
422 */
423 gboolean oddfield = pvr2_state.odd_even_field;
424 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
425 oddfield = !oddfield;
426 }
427 if( oddfield ) {
428 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
429 } else {
430 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
431 }
432 }
433 } else {
434 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
435 }
436 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
437 fbuf.inverted = FALSE;
438 fbuf.data = pvr2_main_ram + (fbuf.address&0x00FFFFFF);
440 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
441 if( rbuf == NULL ) {
442 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
443 }
444 displayed_render_buffer = rbuf;
445 }
446 }
448 /**
449 * This has to handle every single register individually as they all get masked
450 * off differently (and its easier to do it at write time)
451 */
452 MMIO_REGION_WRITE_FN( PVR2, reg, val )
453 {
454 reg &= 0xFFF;
455 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
456 MMIO_WRITE( PVR2, reg, val );
457 return;
458 }
460 switch(reg) {
461 case PVRID:
462 case PVRVER:
463 case GUNPOS: /* Read only registers */
464 break;
465 case PVRRESET:
466 val &= 0x00000007; /* Do stuff? */
467 MMIO_WRITE( PVR2, reg, val );
468 break;
469 case RENDER_START: /* Don't really care what value */
470 if( save_next_render_filename != NULL ) {
471 if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
472 INFO( "Saved scene to %s", save_next_render_filename);
473 }
474 g_free( save_next_render_filename );
475 save_next_render_filename = NULL;
476 }
477 pvr2_scene_read();
478 render_buffer_t buffer = pvr2_next_render_buffer();
479 if( buffer != NULL ) {
480 pvr2_scene_render( buffer );
481 if( buffer->address < PVR2_RAM_BASE ) {
482 // Flush immediately - optimize this later. Otherwise this gets
483 // complicated very quickly trying to second-guess how it's
484 // going to be used as a texture.
485 pvr2_finish_render_buffer( buffer );
486 pvr2_render_buffer_copy_to_sh4( buffer );
487 }
488 }
489 asic_event( EVENT_PVR_RENDER_DONE );
490 break;
491 case RENDER_POLYBASE:
492 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
493 break;
494 case RENDER_TSPCFG:
495 MMIO_WRITE( PVR2, reg, val&0x00010101 );
496 break;
497 case DISP_BORDER:
498 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
499 break;
500 case DISP_MODE:
501 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
502 break;
503 case RENDER_MODE:
504 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
505 break;
506 case RENDER_SIZE:
507 MMIO_WRITE( PVR2, reg, val&0x000001FF );
508 break;
509 case DISP_ADDR1:
510 val &= 0x00FFFFFC;
511 MMIO_WRITE( PVR2, reg, val );
512 pvr2_update_raster_posn(sh4r.slice_cycle);
513 break;
514 case DISP_ADDR2:
515 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
516 pvr2_update_raster_posn(sh4r.slice_cycle);
517 break;
518 case DISP_SIZE:
519 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
520 break;
521 case RENDER_ADDR1:
522 case RENDER_ADDR2:
523 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
524 break;
525 case RENDER_HCLIP:
526 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
527 break;
528 case RENDER_VCLIP:
529 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
530 break;
531 case DISP_HPOSIRQ:
532 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
533 pvr2_state.irq_hpos_line = val & 0x03FF;
534 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
535 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
536 switch( pvr2_state.irq_hpos_mode ) {
537 case 3: /* Reserved - treat as 0 */
538 case 0: /* Once per frame at specified line */
539 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
540 break;
541 case 2: /* Once per line - as per-line-count */
542 pvr2_state.irq_hpos_line = 1;
543 pvr2_state.irq_hpos_mode = 1;
544 case 1: /* Once per N lines */
545 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
546 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
547 pvr2_state.irq_hpos_line_count;
548 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
549 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
550 }
551 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
552 }
553 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
554 pvr2_state.irq_hpos_time_ns );
555 break;
556 case DISP_VPOSIRQ:
557 val = val & 0x03FF03FF;
558 pvr2_state.irq_vpos1 = (val >> 16);
559 pvr2_state.irq_vpos2 = val & 0x03FF;
560 pvr2_update_raster_posn(sh4r.slice_cycle);
561 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
562 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
563 MMIO_WRITE( PVR2, reg, val );
564 break;
565 case RENDER_NEARCLIP:
566 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
567 break;
568 case RENDER_SHADOW:
569 MMIO_WRITE( PVR2, reg, val&0x000001FF );
570 break;
571 case RENDER_OBJCFG:
572 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
573 break;
574 case RENDER_TSPCLIP:
575 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
576 break;
577 case RENDER_FARCLIP:
578 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
579 break;
580 case RENDER_BGPLANE:
581 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
582 break;
583 case RENDER_ISPCFG:
584 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
585 break;
586 case VRAM_CFG1:
587 MMIO_WRITE( PVR2, reg, val&0x000000FF );
588 break;
589 case VRAM_CFG2:
590 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
591 break;
592 case VRAM_CFG3:
593 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
594 break;
595 case RENDER_FOGTBLCOL:
596 case RENDER_FOGVRTCOL:
597 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
598 break;
599 case RENDER_FOGCOEFF:
600 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
601 break;
602 case RENDER_CLAMPHI:
603 case RENDER_CLAMPLO:
604 MMIO_WRITE( PVR2, reg, val );
605 break;
606 case RENDER_TEXSIZE:
607 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
608 break;
609 case RENDER_PALETTE:
610 MMIO_WRITE( PVR2, reg, val&0x00000003 );
611 break;
612 case RENDER_ALPHA_REF:
613 MMIO_WRITE( PVR2, reg, val&0x000000FF );
614 break;
615 /********** CRTC registers *************/
616 case DISP_HBORDER:
617 case DISP_VBORDER:
618 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
619 break;
620 case DISP_TOTAL:
621 val = val & 0x03FF03FF;
622 MMIO_WRITE( PVR2, reg, val );
623 pvr2_update_raster_posn(sh4r.slice_cycle);
624 pvr2_state.total_lines = (val >> 16) + 1;
625 pvr2_state.line_size = (val & 0x03FF) + 1;
626 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
627 pvr2_state.retrace_end_line = 0x2A;
628 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
629 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
630 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
631 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
632 pvr2_state.irq_hpos_time_ns );
633 break;
634 case DISP_SYNCCFG:
635 MMIO_WRITE( PVR2, reg, val&0x000003FF );
636 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
637 break;
638 case DISP_SYNCTIME:
639 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
640 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
641 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
642 break;
643 case DISP_CFG2:
644 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
645 break;
646 case DISP_HPOS:
647 val = val & 0x03FF;
648 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
649 MMIO_WRITE( PVR2, reg, val );
650 break;
651 case DISP_VPOS:
652 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
653 break;
655 /*********** Tile accelerator registers ***********/
656 case TA_POLYPOS:
657 case TA_LISTPOS:
658 /* Readonly registers */
659 break;
660 case TA_TILEBASE:
661 case TA_LISTEND:
662 case TA_LISTBASE:
663 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
664 break;
665 case RENDER_TILEBASE:
666 case TA_POLYBASE:
667 case TA_POLYEND:
668 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
669 break;
670 case TA_TILESIZE:
671 MMIO_WRITE( PVR2, reg, val&0x000F003F );
672 break;
673 case TA_TILECFG:
674 MMIO_WRITE( PVR2, reg, val&0x00133333 );
675 break;
676 case TA_INIT:
677 if( val & 0x80000000 )
678 pvr2_ta_init();
679 break;
680 case TA_REINIT:
681 break;
682 /**************** Scaler registers? ****************/
683 case RENDER_SCALER:
684 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
685 break;
687 case YUV_ADDR:
688 val = val & 0x00FFFFF8;
689 MMIO_WRITE( PVR2, reg, val );
690 pvr2_yuv_init( val );
691 break;
692 case YUV_CFG:
693 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
694 pvr2_yuv_set_config(val);
695 break;
697 /**************** Unknowns ***************/
698 case PVRUNK1:
699 MMIO_WRITE( PVR2, reg, val&0x000007FF );
700 break;
701 case PVRUNK2:
702 MMIO_WRITE( PVR2, reg, val&0x00000007 );
703 break;
704 case PVRUNK3:
705 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
706 break;
707 case PVRUNK5:
708 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
709 break;
710 case PVRUNK7:
711 MMIO_WRITE( PVR2, reg, val&0x00000001 );
712 break;
713 case PVRUNK8:
714 MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
715 break;
716 }
717 }
719 /**
720 * Calculate the current read value of the syncstat register, using
721 * the current SH4 clock time as an offset from the last timeslice.
722 * The register reads (LSB to MSB) as:
723 * 0..9 Current scan line
724 * 10 Odd/even field (1 = odd, 0 = even)
725 * 11 Display active (including border and overscan)
726 * 12 Horizontal sync off
727 * 13 Vertical sync off
728 * Note this method is probably incorrect for anything other than straight
729 * interlaced PAL/NTSC, and needs further testing.
730 */
731 uint32_t pvr2_get_sync_status()
732 {
733 pvr2_update_raster_posn(sh4r.slice_cycle);
734 uint32_t result = pvr2_state.line_count;
736 if( pvr2_state.odd_even_field ) {
737 result |= 0x0400;
738 }
739 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
740 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
741 result |= 0x1000; /* !HSYNC */
742 }
743 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
744 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
745 result |= 0x2800; /* Display active */
746 } else {
747 result |= 0x2000; /* Front porch */
748 }
749 }
750 } else {
751 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
752 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
753 result |= 0x3800; /* Display active */
754 } else {
755 result |= 0x3000;
756 }
757 } else {
758 result |= 0x1000; /* Back porch */
759 }
760 }
761 return result;
762 }
764 /**
765 * Schedule a "scanline" event. This actually goes off at
766 * 2 * line in even fields and 2 * line + 1 in odd fields.
767 * Otherwise this behaves as per pvr2_schedule_line_event().
768 * The raster position should be updated before calling this
769 * method.
770 * @param eventid Event to fire at the specified time
771 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
772 * displays).
773 * @param hpos_ns Nanoseconds into the line at which to fire.
774 */
775 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
776 {
777 uint32_t field = pvr2_state.odd_even_field;
778 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
779 field = !field;
780 }
781 if( hpos_ns > pvr2_state.line_time_ns ) {
782 hpos_ns = pvr2_state.line_time_ns;
783 }
785 line <<= 1;
786 if( field ) {
787 line += 1;
788 }
790 if( line < pvr2_state.total_lines ) {
791 uint32_t lines;
792 uint32_t time;
793 if( line <= pvr2_state.line_count ) {
794 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
795 } else {
796 lines = (line - pvr2_state.line_count);
797 }
798 if( lines <= minimum_lines ) {
799 lines += pvr2_state.total_lines;
800 }
801 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
802 event_schedule( eventid, time );
803 } else {
804 event_cancel( eventid );
805 }
806 }
808 void pvr2_queue_gun_event( int xpos, int ypos )
809 {
810 pvr2_update_raster_posn(sh4r.slice_cycle);
811 pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,
812 (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns );
813 }
815 MMIO_REGION_READ_FN( PVR2, reg )
816 {
817 reg &= 0xFFF;
818 switch( reg ) {
819 case DISP_SYNCSTAT:
820 return pvr2_get_sync_status();
821 default:
822 return MMIO_READ( PVR2, reg );
823 }
824 }
825 MMIO_REGION_READ_DEFSUBFNS(PVR2)
826 MMIO_REGION_READ_DEFSUBFNS(PVR2PAL)
828 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
829 {
830 reg &= 0xFFF;
831 MMIO_WRITE( PVR2PAL, reg, val );
832 pvr2_state.palette_changed = TRUE;
833 }
835 void pvr2_check_palette_changed()
836 {
837 if( pvr2_state.palette_changed ) {
838 texcache_invalidate_palette();
839 pvr2_state.palette_changed = FALSE;
840 }
841 }
843 MMIO_REGION_READ_DEFFN( PVR2PAL );
845 void pvr2_set_base_address( uint32_t base )
846 {
847 mmio_region_PVR2_write( DISP_ADDR1, base );
848 }
850 render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
851 {
852 if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
853 render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
854 buffer->address = addr;
855 return buffer;
856 }
857 return NULL;
858 }
860 void pvr2_destroy_render_buffer( render_buffer_t buffer )
861 {
862 if( !buffer->flushed )
863 pvr2_render_buffer_copy_to_sh4( buffer );
864 display_driver->destroy_render_buffer( buffer );
865 }
867 void pvr2_finish_render_buffer( render_buffer_t buffer )
868 {
869 display_driver->finish_render( buffer );
870 }
872 /**
873 * Find the render buffer corresponding to the requested output frame
874 * (does not consider texture renders).
875 * @return the render_buffer if found, or null if no such buffer.
876 *
877 * Note: Currently does not consider "partial matches", ie partial
878 * frame overlap - it probably needs to do this.
879 */
880 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
881 {
882 int i;
883 for( i=0; i<render_buffer_count; i++ ) {
884 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
885 return render_buffers[i];
886 }
887 }
888 return NULL;
889 }
891 /**
892 * Allocate a render buffer with the requested parameters.
893 * The order of preference is:
894 * 1. An existing buffer with the same address. (not flushed unless the new
895 * size is smaller than the old one).
896 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
897 * is flushed to vram.
898 * 3. A new buffer if one can be created.
899 * 4. The current display buff
900 * Note: The current display field(s) will never be overwritten except as a last
901 * resort.
902 */
903 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
904 {
905 int i;
906 render_buffer_t result = NULL;
908 /* Check existing buffers for an available buffer */
909 for( i=0; i<render_buffer_count; i++ ) {
910 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
911 /* needs to be the right dimensions */
912 if( render_buffers[i]->address == render_addr ) {
913 if( displayed_render_buffer == render_buffers[i] ) {
914 /* Same address, but we can't use it because the
915 * display has it. Mark it as unaddressed for later.
916 */
917 render_buffers[i]->address = -1;
918 } else {
919 /* perfect */
920 result = render_buffers[i];
921 break;
922 }
923 } else if( render_buffers[i]->address == -1 && result == NULL &&
924 displayed_render_buffer != render_buffers[i] ) {
925 result = render_buffers[i];
926 }
928 } else if( render_buffers[i]->address == render_addr ) {
929 /* right address, wrong size - if it's larger, flush it, otherwise
930 * nuke it quietly */
931 if( render_buffers[i]->width * render_buffers[i]->height >
932 width*height ) {
933 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
934 }
935 render_buffers[i]->address = -1;
936 }
937 }
939 /* Nothing available - make one */
940 if( result == NULL ) {
941 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
942 /* maximum buffers reached - need to throw one away */
943 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
944 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
945 for( i=0; i<render_buffer_count; i++ ) {
946 if( render_buffers[i]->address != field1_addr &&
947 render_buffers[i]->address != field2_addr &&
948 render_buffers[i] != displayed_render_buffer ) {
949 /* Never throw away the current "front buffer(s)" */
950 result = render_buffers[i];
951 if( !result->flushed && result->address != -1 ) {
952 pvr2_render_buffer_copy_to_sh4( result );
953 }
954 if( result->width != width || result->height != height ) {
955 display_driver->destroy_render_buffer(render_buffers[i]);
956 result = display_driver->create_render_buffer(width,height,0);
957 render_buffers[i] = result;
958 }
959 break;
960 }
961 }
962 } else {
963 result = display_driver->create_render_buffer(width,height,0);
964 if( result != NULL ) {
965 render_buffers[render_buffer_count++] = result;
966 }
967 }
968 }
970 if( result != NULL ) {
971 result->address = render_addr;
972 }
973 return result;
974 }
976 /**
977 * Allocate a render buffer based on the current rendering settings
978 */
979 render_buffer_t pvr2_next_render_buffer()
980 {
981 render_buffer_t result = NULL;
982 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
983 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
984 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
985 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
987 int width = pvr2_scene_buffer_width();
988 int height = pvr2_scene_buffer_height();
989 int colour_format = render_colour_formats[render_mode&0x07];
991 if( render_addr & 0x01000000 ) { /* vram64 */
992 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
993 } else { /* vram32 */
994 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
995 }
996 result = pvr2_alloc_render_buffer( render_addr, width, height );
998 /* Setup the buffer */
999 if( result != NULL ) {
1000 result->rowstride = render_stride;
1001 result->colour_format = colour_format;
1002 result->scale = render_scale;
1003 result->size = width * height * colour_formats[colour_format].bpp;
1004 result->flushed = FALSE;
1005 result->inverted = TRUE; // render buffers are inverted normally
1006 }
1007 return result;
1008 }
1010 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
1011 {
1012 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
1013 if( result != NULL ) {
1014 int bpp = colour_formats[frame->colour_format].bpp;
1015 result->rowstride = frame->rowstride;
1016 result->colour_format = frame->colour_format;
1017 result->scale = 0x400;
1018 result->size = frame->width * frame->height * bpp;
1019 result->flushed = TRUE;
1020 result->inverted = frame->inverted;
1021 display_driver->load_frame_buffer( frame, result );
1022 }
1023 return result;
1024 }
1027 /**
1028 * Invalidate any caching on the supplied address. Specifically, if it falls
1029 * within any of the render buffers, flush the buffer back to PVR2 ram.
1030 */
1031 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
1032 {
1033 int i;
1034 address = address & 0x1FFFFFFF;
1035 for( i=0; i<render_buffer_count; i++ ) {
1036 uint32_t bufaddr = render_buffers[i]->address;
1037 if( bufaddr != -1 && bufaddr <= address &&
1038 (bufaddr + render_buffers[i]->size) > address ) {
1039 if( !render_buffers[i]->flushed ) {
1040 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
1041 }
1042 if( isWrite ) {
1043 render_buffers[i]->address = -1; /* Invalid */
1044 }
1045 return TRUE; /* should never have overlapping buffers */
1046 }
1047 }
1048 return FALSE;
1049 }
.