lxdream.org :: lxdream/src/sh4/sh4core.c r587:739a3136f269

tree revision 593:6c710c7c6835

filename	src/sh4/sh4core.c
changeset	587:739a3136f269
prev	586:2a3ba82cf243
next	617:476a717a54f3
author	nkeynes
date	Thu Jan 17 21:26:58 2008 +0000 (16 years ago)
permissions	-rw-r--r--
last change	Fix block overruns from long epilogues

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     1 /**

     2  * $Id$

     3  *

     4  * SH4 emulation core, and parent module for all the SH4 peripheral

     5  * modules.

     6  *

     7  * Copyright (c) 2005 Nathan Keynes.

     8  *

     9  * This program is free software; you can redistribute it and/or modify

    10  * it under the terms of the GNU General Public License as published by

    11  * the Free Software Foundation; either version 2 of the License, or

    12  * (at your option) any later version.

    13  *

    14  * This program is distributed in the hope that it will be useful,

    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  * GNU General Public License for more details.

    18  */

    20 #define MODULE sh4_module

    21 #include <assert.h>

    22 #include <math.h>

    23 #include "dream.h"

    24 #include "dreamcast.h"

    25 #include "eventq.h"

    26 #include "mem.h"

    27 #include "clock.h"

    28 #include "syscall.h"

    29 #include "sh4/sh4core.h"

    30 #include "sh4/sh4mmio.h"

    31 #include "sh4/intc.h"

    33 #define SH4_CALLTRACE 1

    35 #define MAX_INT 0x7FFFFFFF

    36 #define MIN_INT 0x80000000

    37 #define MAX_INTF 2147483647.0

    38 #define MIN_INTF -2147483648.0

    40 /********************** SH4 Module Definition ****************************/

    42 uint32_t sh4_run_slice( uint32_t nanosecs )

    43 {

    44     int i;

    45     sh4r.slice_cycle = 0;

    47     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {

    48 	if( sh4r.event_pending < nanosecs ) {

    49 	    sh4r.sh4_state = SH4_STATE_RUNNING;

    50 	    sh4r.slice_cycle = sh4r.event_pending;

    51 	}

    52     }

    54     if( sh4_breakpoint_count == 0 ) {

    55 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

    56 	    if( SH4_EVENT_PENDING() ) {

    57 		if( sh4r.event_types & PENDING_EVENT ) {

    58 		    event_execute();

    59 		}

    60 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

    61 		if( sh4r.event_types & PENDING_IRQ ) {

    62 		    sh4_accept_interrupt();

    63 		}

    64 	    }

    65 	    if( !sh4_execute_instruction() ) {

    66 		break;

    67 	    }

    68 	}

    69     } else {

    70 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

    71 	    if( SH4_EVENT_PENDING() ) {

    72 		if( sh4r.event_types & PENDING_EVENT ) {

    73 		    event_execute();

    74 		}

    75 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

    76 		if( sh4r.event_types & PENDING_IRQ ) {

    77 		    sh4_accept_interrupt();

    78 		}

    79 	    }

    81 	    if( !sh4_execute_instruction() )

    82 		break;

    83 #ifdef ENABLE_DEBUG_MODE

    84 	    for( i=0; i<sh4_breakpoint_count; i++ ) {

    85 		if( sh4_breakpoints[i].address == sh4r.pc ) {

    86 		    break;

    87 		}

    88 	    }

    89 	    if( i != sh4_breakpoint_count ) {

    90 		dreamcast_stop();

    91 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )

    92 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );

    93 		break;

    94 	    }

    95 #endif

    96 	}

    97     }

    99     /* If we aborted early, but the cpu is still technically running,

   100      * we're doing a hard abort - cut the timeslice back to what we

   101      * actually executed

   102      */

   103     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {

   104 	nanosecs = sh4r.slice_cycle;

   105     }

   106     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {

   107 	TMU_run_slice( nanosecs );

   108 	SCIF_run_slice( nanosecs );

   109     }

   110     return nanosecs;

   111 }

   113 /********************** SH4 emulation core  ****************************/

   115 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)

   116 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)

   118 #if(SH4_CALLTRACE == 1)

   119 #define MAX_CALLSTACK 32

   120 static struct call_stack {

   121     sh4addr_t call_addr;

   122     sh4addr_t target_addr;

   123     sh4addr_t stack_pointer;

   124 } call_stack[MAX_CALLSTACK];

   126 static int call_stack_depth = 0;

   127 int sh4_call_trace_on = 0;

   129 static inline void trace_call( sh4addr_t source, sh4addr_t dest )

   130 {

   131     if( call_stack_depth < MAX_CALLSTACK ) {

   132 	call_stack[call_stack_depth].call_addr = source;

   133 	call_stack[call_stack_depth].target_addr = dest;

   134 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];

   135     }

   136     call_stack_depth++;

   137 }

   139 static inline void trace_return( sh4addr_t source, sh4addr_t dest )

   140 {

   141     if( call_stack_depth > 0 ) {

   142 	call_stack_depth--;

   143     }

   144 }

   146 void fprint_stack_trace( FILE *f )

   147 {

   148     int i = call_stack_depth -1;

   149     if( i >= MAX_CALLSTACK )

   150 	i = MAX_CALLSTACK - 1;

   151     for( ; i >= 0; i-- ) {

   152 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",

   153 		 (call_stack_depth - i), call_stack[i].call_addr,

   154 		 call_stack[i].target_addr, call_stack[i].stack_pointer );

   155     }

   156 }

   158 #define TRACE_CALL( source, dest ) trace_call(source, dest)

   159 #define TRACE_RETURN( source, dest ) trace_return(source, dest)

   160 #else

   161 #define TRACE_CALL( dest, rts )

   162 #define TRACE_RETURN( source, dest )

   163 #endif

   165 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }

   166 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }

   167 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }

   168 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }

   169 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }

   170 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }

   172 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)

   174 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );

   175 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );

   177 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )

   178 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

   179 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

   180 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

   181 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

   183 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }

   184 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }

   185 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)

   187 static void sh4_write_float( uint32_t addr, int reg )

   188 {

   189     if( IS_FPU_DOUBLESIZE() ) {

   190 	if( reg & 1 ) {

   191 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );

   192 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );

   193 	} else {

   194 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) );

   195 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );

   196 	}

   197     } else {

   198 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );

   199     }

   200 }

   202 static void sh4_read_float( uint32_t addr, int reg )

   203 {

   204     if( IS_FPU_DOUBLESIZE() ) {

   205 	if( reg & 1 ) {

   206 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);

   207 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);

   208 	} else {

   209 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);

   210 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);

   211 	}

   212     } else {

   213 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);

   214     }

   215 }

   217 gboolean sh4_execute_instruction( void )

   218 {

   219     uint32_t pc;

   220     unsigned short ir;

   221     uint32_t tmp;

   222     float ftmp;

   223     double dtmp;

   224     int64_t memtmp; // temporary holder for memory reads

   226 #define R0 sh4r.r[0]

   227     pc = sh4r.pc;

   228     if( pc > 0xFFFFFF00 ) {

   229 	/* SYSCALL Magic */

   230 	syscall_invoke( pc );

   231 	sh4r.in_delay_slot = 0;

   232 	pc = sh4r.pc = sh4r.pr;

   233 	sh4r.new_pc = sh4r.pc + 2;

   234     }

   235     CHECKRALIGN16(pc);

   237     /* Read instruction */

   238     if( !IS_IN_ICACHE(pc) ) {

   239 	if( !mmu_update_icache(pc) ) {

   240 	    // Fault - look for the fault handler

   241 	    if( !mmu_update_icache(sh4r.pc) ) {

   242 		// double fault - halt

   243 		ERROR( "Double fault - halting" );

   244 		dreamcast_stop();

   245 		return FALSE;

   246 	    }

   247 	}

   248 	pc = sh4r.pc;

   249     }

   250     assert( IS_IN_ICACHE(pc) );

   251     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);

   252         switch( (ir&0xF000) >> 12 ) {

   253             case 0x0:

   254                 switch( ir&0xF ) {

   255                     case 0x2:

   256                         switch( (ir&0x80) >> 7 ) {

   257                             case 0x0:

   258                                 switch( (ir&0x70) >> 4 ) {

   259                                     case 0x0:

   260                                         { /* STC SR, Rn */

   261                                         uint32_t Rn = ((ir>>8)&0xF);

   262                                         CHECKPRIV();

   263                                         sh4r.r[Rn] = sh4_read_sr();

   264                                         }

   265                                         break;

   266                                     case 0x1:

   267                                         { /* STC GBR, Rn */

   268                                         uint32_t Rn = ((ir>>8)&0xF);

   269                                         CHECKPRIV();

   270                                         sh4r.r[Rn] = sh4r.gbr;

   271                                         }

   272                                         break;

   273                                     case 0x2:

   274                                         { /* STC VBR, Rn */

   275                                         uint32_t Rn = ((ir>>8)&0xF);

   276                                         CHECKPRIV();

   277                                         sh4r.r[Rn] = sh4r.vbr;

   278                                         }

   279                                         break;

   280                                     case 0x3:

   281                                         { /* STC SSR, Rn */

   282                                         uint32_t Rn = ((ir>>8)&0xF);

   283                                         CHECKPRIV();

   284                                         sh4r.r[Rn] = sh4r.ssr;

   285                                         }

   286                                         break;

   287                                     case 0x4:

   288                                         { /* STC SPC, Rn */

   289                                         uint32_t Rn = ((ir>>8)&0xF);

   290                                         CHECKPRIV();

   291                                         sh4r.r[Rn] = sh4r.spc;

   292                                         }

   293                                         break;

   294                                     default:

   295                                         UNDEF();

   296                                         break;

   297                                 }

   298                                 break;

   299                             case 0x1:

   300                                 { /* STC Rm_BANK, Rn */

   301                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

   302                                 CHECKPRIV();

   303                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];

   304                                 }

   305                                 break;

   306                         }

   307                         break;

   308                     case 0x3:

   309                         switch( (ir&0xF0) >> 4 ) {

   310                             case 0x0:

   311                                 { /* BSRF Rn */

   312                                 uint32_t Rn = ((ir>>8)&0xF);

   313                                 CHECKSLOTILLEGAL();

   314                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );

   315                                 sh4r.in_delay_slot = 1;

   316                                 sh4r.pr = sh4r.pc + 4;

   317                                 sh4r.pc = sh4r.new_pc;

   318                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];

   319                                 TRACE_CALL( pc, sh4r.new_pc );

   320                                 return TRUE;

   321                                 }

   322                                 break;

   323                             case 0x2:

   324                                 { /* BRAF Rn */

   325                                 uint32_t Rn = ((ir>>8)&0xF);

   326                                 CHECKSLOTILLEGAL();

   327                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );

   328                                 sh4r.in_delay_slot = 1;

   329                                 sh4r.pc = sh4r.new_pc;

   330                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];

   331                                 return TRUE;

   332                                 }

   333                                 break;

   334                             case 0x8:

   335                                 { /* PREF @Rn */

   336                                 uint32_t Rn = ((ir>>8)&0xF);

   337                                 tmp = sh4r.r[Rn];

   338                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {

   339                            	 sh4_flush_store_queue(tmp);

   340                                 }

   341                                 }

   342                                 break;

   343                             case 0x9:

   344                                 { /* OCBI @Rn */

   345                                 uint32_t Rn = ((ir>>8)&0xF);

   346                                 }

   347                                 break;

   348                             case 0xA:

   349                                 { /* OCBP @Rn */

   350                                 uint32_t Rn = ((ir>>8)&0xF);

   351                                 }

   352                                 break;

   353                             case 0xB:

   354                                 { /* OCBWB @Rn */

   355                                 uint32_t Rn = ((ir>>8)&0xF);

   356                                 }

   357                                 break;

   358                             case 0xC:

   359                                 { /* MOVCA.L R0, @Rn */

   360                                 uint32_t Rn = ((ir>>8)&0xF);

   361                                 tmp = sh4r.r[Rn];

   362                                 CHECKWALIGN32(tmp);

   363                                 MEM_WRITE_LONG( tmp, R0 );

   364                                 }

   365                                 break;

   366                             default:

   367                                 UNDEF();

   368                                 break;

   369                         }

   370                         break;

   371                     case 0x4:

   372                         { /* MOV.B Rm, @(R0, Rn) */

   373                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   374                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   375                         }

   376                         break;

   377                     case 0x5:

   378                         { /* MOV.W Rm, @(R0, Rn) */

   379                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   380                         CHECKWALIGN16( R0 + sh4r.r[Rn] );

   381                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   382                         }

   383                         break;

   384                     case 0x6:

   385                         { /* MOV.L Rm, @(R0, Rn) */

   386                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   387                         CHECKWALIGN32( R0 + sh4r.r[Rn] );

   388                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   389                         }

   390                         break;

   391                     case 0x7:

   392                         { /* MUL.L Rm, Rn */

   393                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   394                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   395                                                (sh4r.r[Rm] * sh4r.r[Rn]);

   396                         }

   397                         break;

   398                     case 0x8:

   399                         switch( (ir&0xFF0) >> 4 ) {

   400                             case 0x0:

   401                                 { /* CLRT */

   402                                 sh4r.t = 0;

   403                                 }

   404                                 break;

   405                             case 0x1:

   406                                 { /* SETT */

   407                                 sh4r.t = 1;

   408                                 }

   409                                 break;

   410                             case 0x2:

   411                                 { /* CLRMAC */

   412                                 sh4r.mac = 0;

   413                                 }

   414                                 break;

   415                             case 0x3:

   416                                 { /* LDTLB */

   417                                 MMU_ldtlb();

   418                                 }

   419                                 break;

   420                             case 0x4:

   421                                 { /* CLRS */

   422                                 sh4r.s = 0;

   423                                 }

   424                                 break;

   425                             case 0x5:

   426                                 { /* SETS */

   427                                 sh4r.s = 1;

   428                                 }

   429                                 break;

   430                             default:

   431                                 UNDEF();

   432                                 break;

   433                         }

   434                         break;

   435                     case 0x9:

   436                         switch( (ir&0xF0) >> 4 ) {

   437                             case 0x0:

   438                                 { /* NOP */

   439                                 /* NOP */

   440                                 }

   441                                 break;

   442                             case 0x1:

   443                                 { /* DIV0U */

   444                                 sh4r.m = sh4r.q = sh4r.t = 0;

   445                                 }

   446                                 break;

   447                             case 0x2:

   448                                 { /* MOVT Rn */

   449                                 uint32_t Rn = ((ir>>8)&0xF);

   450                                 sh4r.r[Rn] = sh4r.t;

   451                                 }

   452                                 break;

   453                             default:

   454                                 UNDEF();

   455                                 break;

   456                         }

   457                         break;

   458                     case 0xA:

   459                         switch( (ir&0xF0) >> 4 ) {

   460                             case 0x0:

   461                                 { /* STS MACH, Rn */

   462                                 uint32_t Rn = ((ir>>8)&0xF);

   463                                 sh4r.r[Rn] = (sh4r.mac>>32);

   464                                 }

   465                                 break;

   466                             case 0x1:

   467                                 { /* STS MACL, Rn */

   468                                 uint32_t Rn = ((ir>>8)&0xF);

   469                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;

   470                                 }

   471                                 break;

   472                             case 0x2:

   473                                 { /* STS PR, Rn */

   474                                 uint32_t Rn = ((ir>>8)&0xF);

   475                                 sh4r.r[Rn] = sh4r.pr;

   476                                 }

   477                                 break;

   478                             case 0x3:

   479                                 { /* STC SGR, Rn */

   480                                 uint32_t Rn = ((ir>>8)&0xF);

   481                                 CHECKPRIV();

   482                                 sh4r.r[Rn] = sh4r.sgr;

   483                                 }

   484                                 break;

   485                             case 0x5:

   486                                 { /* STS FPUL, Rn */

   487                                 uint32_t Rn = ((ir>>8)&0xF);

   488                                 sh4r.r[Rn] = sh4r.fpul;

   489                                 }

   490                                 break;

   491                             case 0x6:

   492                                 { /* STS FPSCR, Rn */

   493                                 uint32_t Rn = ((ir>>8)&0xF);

   494                                 sh4r.r[Rn] = sh4r.fpscr;

   495                                 }

   496                                 break;

   497                             case 0xF:

   498                                 { /* STC DBR, Rn */

   499                                 uint32_t Rn = ((ir>>8)&0xF);

   500                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;

   501                                 }

   502                                 break;

   503                             default:

   504                                 UNDEF();

   505                                 break;

   506                         }

   507                         break;

   508                     case 0xB:

   509                         switch( (ir&0xFF0) >> 4 ) {

   510                             case 0x0:

   511                                 { /* RTS */

   512                                 CHECKSLOTILLEGAL();

   513                                 CHECKDEST( sh4r.pr );

   514                                 sh4r.in_delay_slot = 1;

   515                                 sh4r.pc = sh4r.new_pc;

   516                                 sh4r.new_pc = sh4r.pr;

   517                                 TRACE_RETURN( pc, sh4r.new_pc );

   518                                 return TRUE;

   519                                 }

   520                                 break;

   521                             case 0x1:

   522                                 { /* SLEEP */

   523                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {

   524                             	sh4r.sh4_state = SH4_STATE_STANDBY;

   525                                 } else {

   526                             	sh4r.sh4_state = SH4_STATE_SLEEP;

   527                                 }

   528                                 return FALSE; /* Halt CPU */

   529                                 }

   530                                 break;

   531                             case 0x2:

   532                                 { /* RTE */

   533                                 CHECKPRIV();

   534                                 CHECKDEST( sh4r.spc );

   535                                 CHECKSLOTILLEGAL();

   536                                 sh4r.in_delay_slot = 1;

   537                                 sh4r.pc = sh4r.new_pc;

   538                                 sh4r.new_pc = sh4r.spc;

   539                                 sh4_write_sr( sh4r.ssr );

   540                                 return TRUE;

   541                                 }

   542                                 break;

   543                             default:

   544                                 UNDEF();

   545                                 break;

   546                         }

   547                         break;

   548                     case 0xC:

   549                         { /* MOV.B @(R0, Rm), Rn */

   550                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   551                         MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] );

   552                         }

   553                         break;

   554                     case 0xD:

   555                         { /* MOV.W @(R0, Rm), Rn */

   556                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   557                         CHECKRALIGN16( R0 + sh4r.r[Rm] );

   558                            MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );

   559                         }

   560                         break;

   561                     case 0xE:

   562                         { /* MOV.L @(R0, Rm), Rn */

   563                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   564                         CHECKRALIGN32( R0 + sh4r.r[Rm] );

   565                            MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );

   566                         }

   567                         break;

   568                     case 0xF:

   569                         { /* MAC.L @Rm+, @Rn+ */

   570                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   571                         int64_t tmpl;

   572                         if( Rm == Rn ) {

   573                     	CHECKRALIGN32( sh4r.r[Rn] );

   574                     	MEM_READ_LONG(sh4r.r[Rn], tmp);

   575                     	tmpl = SIGNEXT32(tmp);

   576                     	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);

   577                     	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;

   578                     	sh4r.r[Rn] += 8;

   579                         } else {

   580                     	CHECKRALIGN32( sh4r.r[Rm] );

   581                     	CHECKRALIGN32( sh4r.r[Rn] );

   582                     	MEM_READ_LONG(sh4r.r[Rn], tmp);

   583                     	tmpl = SIGNEXT32(tmp);

   584                     	MEM_READ_LONG(sh4r.r[Rm], tmp);

   585                     	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;

   586                     	sh4r.r[Rn] += 4;

   587                     	sh4r.r[Rm] += 4;

   588                         }

   589                         if( sh4r.s ) {

   590                             /* 48-bit Saturation. Yuch */

   591                             if( tmpl < (int64_t)0xFFFF800000000000LL )

   592                                 tmpl = 0xFFFF800000000000LL;

   593                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )

   594                                 tmpl = 0x00007FFFFFFFFFFFLL;

   595                         }

   596                         sh4r.mac = tmpl;

   597                         }

   598                         break;

   599                     default:

   600                         UNDEF();

   601                         break;

   602                 }

   603                 break;

   604             case 0x1:

   605                 { /* MOV.L Rm, @(disp, Rn) */

   606                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

   607                 tmp = sh4r.r[Rn] + disp;

   608                 CHECKWALIGN32( tmp );

   609                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );

   610                 }

   611                 break;

   612             case 0x2:

   613                 switch( ir&0xF ) {

   614                     case 0x0:

   615                         { /* MOV.B Rm, @Rn */

   616                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   617                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );

   618                         }

   619                         break;

   620                     case 0x1:

   621                         { /* MOV.W Rm, @Rn */

   622                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   623                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );

   624                         }

   625                         break;

   626                     case 0x2:

   627                         { /* MOV.L Rm, @Rn */

   628                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   629                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );

   630                         }

   631                         break;

   632                     case 0x4:

   633                         { /* MOV.B Rm, @-Rn */

   634                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   635                         MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--;

   636                         }

   637                         break;

   638                     case 0x5:

   639                         { /* MOV.W Rm, @-Rn */

   640                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   641                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2;

   642                         }

   643                         break;

   644                     case 0x6:

   645                         { /* MOV.L Rm, @-Rn */

   646                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   647                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4;

   648                         }

   649                         break;

   650                     case 0x7:

   651                         { /* DIV0S Rm, Rn */

   652                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   653                         sh4r.q = sh4r.r[Rn]>>31;

   654                         sh4r.m = sh4r.r[Rm]>>31;

   655                         sh4r.t = sh4r.q ^ sh4r.m;

   656                         }

   657                         break;

   658                     case 0x8:

   659                         { /* TST Rm, Rn */

   660                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   661                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);

   662                         }

   663                         break;

   664                     case 0x9:

   665                         { /* AND Rm, Rn */

   666                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   667                         sh4r.r[Rn] &= sh4r.r[Rm];

   668                         }

   669                         break;

   670                     case 0xA:

   671                         { /* XOR Rm, Rn */

   672                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   673                         sh4r.r[Rn] ^= sh4r.r[Rm];

   674                         }

   675                         break;

   676                     case 0xB:

   677                         { /* OR Rm, Rn */

   678                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   679                         sh4r.r[Rn] |= sh4r.r[Rm];

   680                         }

   681                         break;

   682                     case 0xC:

   683                         { /* CMP/STR Rm, Rn */

   684                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   685                         /* set T = 1 if any byte in RM & RN is the same */

   686                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];

   687                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||

   688                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;

   689                         }

   690                         break;

   691                     case 0xD:

   692                         { /* XTRCT Rm, Rn */

   693                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   694                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);

   695                         }

   696                         break;

   697                     case 0xE:

   698                         { /* MULU.W Rm, Rn */

   699                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   700                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   701                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));

   702                         }

   703                         break;

   704                     case 0xF:

   705                         { /* MULS.W Rm, Rn */

   706                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   707                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   708                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));

   709                         }

   710                         break;

   711                     default:

   712                         UNDEF();

   713                         break;

   714                 }

   715                 break;

   716             case 0x3:

   717                 switch( ir&0xF ) {

   718                     case 0x0:

   719                         { /* CMP/EQ Rm, Rn */

   720                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   721                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );

   722                         }

   723                         break;

   724                     case 0x2:

   725                         { /* CMP/HS Rm, Rn */

   726                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   727                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );

   728                         }

   729                         break;

   730                     case 0x3:

   731                         { /* CMP/GE Rm, Rn */

   732                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   733                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

   734                         }

   735                         break;

   736                     case 0x4:

   737                         { /* DIV1 Rm, Rn */

   738                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   739                         /* This is derived from the sh4 manual with some simplifications */

   740                         uint32_t tmp0, tmp1, tmp2, dir;

   742                         dir = sh4r.q ^ sh4r.m;

   743                         sh4r.q = (sh4r.r[Rn] >> 31);

   744                         tmp2 = sh4r.r[Rm];

   745                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;

   746                         tmp0 = sh4r.r[Rn];

   747                         if( dir ) {

   748                              sh4r.r[Rn] += tmp2;

   749                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );

   750                         } else {

   751                              sh4r.r[Rn] -= tmp2;

   752                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );

   753                         }

   754                         sh4r.q ^= sh4r.m ^ tmp1;

   755                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );

   756                         }

   757                         break;

   758                     case 0x5:

   759                         { /* DMULU.L Rm, Rn */

   760                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   761                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);

   762                         }

   763                         break;

   764                     case 0x6:

   765                         { /* CMP/HI Rm, Rn */

   766                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   767                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );

   768                         }

   769                         break;

   770                     case 0x7:

   771                         { /* CMP/GT Rm, Rn */

   772                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   773                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

   774                         }

   775                         break;

   776                     case 0x8:

   777                         { /* SUB Rm, Rn */

   778                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   779                         sh4r.r[Rn] -= sh4r.r[Rm];

   780                         }

   781                         break;

   782                     case 0xA:

   783                         { /* SUBC Rm, Rn */

   784                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   785                         tmp = sh4r.r[Rn];

   786                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;

   787                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));

   788                         }

   789                         break;

   790                     case 0xB:

   791                         UNIMP(ir); /* SUBV Rm, Rn */

   792                         break;

   793                     case 0xC:

   794                         { /* ADD Rm, Rn */

   795                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   796                         sh4r.r[Rn] += sh4r.r[Rm];

   797                         }

   798                         break;

   799                     case 0xD:

   800                         { /* DMULS.L Rm, Rn */

   801                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   802                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);

   803                         }

   804                         break;

   805                     case 0xE:

   806                         { /* ADDC Rm, Rn */

   807                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   808                         tmp = sh4r.r[Rn];

   809                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;

   810                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );

   811                         }

   812                         break;

   813                     case 0xF:

   814                         { /* ADDV Rm, Rn */

   815                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   816                         tmp = sh4r.r[Rn] + sh4r.r[Rm];

   817                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );

   818                         sh4r.r[Rn] = tmp;

   819                         }

   820                         break;

   821                     default:

   822                         UNDEF();

   823                         break;

   824                 }

   825                 break;

   826             case 0x4:

   827                 switch( ir&0xF ) {

   828                     case 0x0:

   829                         switch( (ir&0xF0) >> 4 ) {

   830                             case 0x0:

   831                                 { /* SHLL Rn */

   832                                 uint32_t Rn = ((ir>>8)&0xF);

   833                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;

   834                                 }

   835                                 break;

   836                             case 0x1:

   837                                 { /* DT Rn */

   838                                 uint32_t Rn = ((ir>>8)&0xF);

   839                                 sh4r.r[Rn] --;

   840                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );

   841                                 }

   842                                 break;

   843                             case 0x2:

   844                                 { /* SHAL Rn */

   845                                 uint32_t Rn = ((ir>>8)&0xF);

   846                                 sh4r.t = sh4r.r[Rn] >> 31;

   847                                 sh4r.r[Rn] <<= 1;

   848                                 }

   849                                 break;

   850                             default:

   851                                 UNDEF();

   852                                 break;

   853                         }

   854                         break;

   855                     case 0x1:

   856                         switch( (ir&0xF0) >> 4 ) {

   857                             case 0x0:

   858                                 { /* SHLR Rn */

   859                                 uint32_t Rn = ((ir>>8)&0xF);

   860                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;

   861                                 }

   862                                 break;

   863                             case 0x1:

   864                                 { /* CMP/PZ Rn */

   865                                 uint32_t Rn = ((ir>>8)&0xF);

   866                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );

   867                                 }

   868                                 break;

   869                             case 0x2:

   870                                 { /* SHAR Rn */

   871                                 uint32_t Rn = ((ir>>8)&0xF);

   872                                 sh4r.t = sh4r.r[Rn] & 0x00000001;

   873                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;

   874                                 }

   875                                 break;

   876                             default:

   877                                 UNDEF();

   878                                 break;

   879                         }

   880                         break;

   881                     case 0x2:

   882                         switch( (ir&0xF0) >> 4 ) {

   883                             case 0x0:

   884                                 { /* STS.L MACH, @-Rn */

   885                                 uint32_t Rn = ((ir>>8)&0xF);

   886                                 CHECKWALIGN32( sh4r.r[Rn] );

   887                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );

   888                                 sh4r.r[Rn] -= 4;

   889                                 }

   890                                 break;

   891                             case 0x1:

   892                                 { /* STS.L MACL, @-Rn */

   893                                 uint32_t Rn = ((ir>>8)&0xF);

   894                                 CHECKWALIGN32( sh4r.r[Rn] );

   895                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );

   896                                 sh4r.r[Rn] -= 4;

   897                                 }

   898                                 break;

   899                             case 0x2:

   900                                 { /* STS.L PR, @-Rn */

   901                                 uint32_t Rn = ((ir>>8)&0xF);

   902                                 CHECKWALIGN32( sh4r.r[Rn] );

   903                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );

   904                                 sh4r.r[Rn] -= 4;

   905                                 }

   906                                 break;

   907                             case 0x3:

   908                                 { /* STC.L SGR, @-Rn */

   909                                 uint32_t Rn = ((ir>>8)&0xF);

   910                                 CHECKPRIV();

   911                                 CHECKWALIGN32( sh4r.r[Rn] );

   912                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );

   913                                 sh4r.r[Rn] -= 4;

   914                                 }

   915                                 break;

   916                             case 0x5:

   917                                 { /* STS.L FPUL, @-Rn */

   918                                 uint32_t Rn = ((ir>>8)&0xF);

   919                                 CHECKWALIGN32( sh4r.r[Rn] );

   920                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );

   921                                 sh4r.r[Rn] -= 4;

   922                                 }

   923                                 break;

   924                             case 0x6:

   925                                 { /* STS.L FPSCR, @-Rn */

   926                                 uint32_t Rn = ((ir>>8)&0xF);

   927                                 CHECKWALIGN32( sh4r.r[Rn] );

   928                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );

   929                                 sh4r.r[Rn] -= 4;

   930                                 }

   931                                 break;

   932                             case 0xF:

   933                                 { /* STC.L DBR, @-Rn */

   934                                 uint32_t Rn = ((ir>>8)&0xF);

   935                                 CHECKPRIV();

   936                                 CHECKWALIGN32( sh4r.r[Rn] );

   937                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );

   938                                 sh4r.r[Rn] -= 4;

   939                                 }

   940                                 break;

   941                             default:

   942                                 UNDEF();

   943                                 break;

   944                         }

   945                         break;

   946                     case 0x3:

   947                         switch( (ir&0x80) >> 7 ) {

   948                             case 0x0:

   949                                 switch( (ir&0x70) >> 4 ) {

   950                                     case 0x0:

   951                                         { /* STC.L SR, @-Rn */

   952                                         uint32_t Rn = ((ir>>8)&0xF);

   953                                         CHECKPRIV();

   954                                         CHECKWALIGN32( sh4r.r[Rn] );

   955                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );

   956                                         sh4r.r[Rn] -= 4;

   957                                         }

   958                                         break;

   959                                     case 0x1:

   960                                         { /* STC.L GBR, @-Rn */

   961                                         uint32_t Rn = ((ir>>8)&0xF);

   962                                         CHECKWALIGN32( sh4r.r[Rn] );

   963                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );

   964                                         sh4r.r[Rn] -= 4;

   965                                         }

   966                                         break;

   967                                     case 0x2:

   968                                         { /* STC.L VBR, @-Rn */

   969                                         uint32_t Rn = ((ir>>8)&0xF);

   970                                         CHECKPRIV();

   971                                         CHECKWALIGN32( sh4r.r[Rn] );

   972                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );

   973                                         sh4r.r[Rn] -= 4;

   974                                         }

   975                                         break;

   976                                     case 0x3:

   977                                         { /* STC.L SSR, @-Rn */

   978                                         uint32_t Rn = ((ir>>8)&0xF);

   979                                         CHECKPRIV();

   980                                         CHECKWALIGN32( sh4r.r[Rn] );

   981                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );

   982                                         sh4r.r[Rn] -= 4;

   983                                         }

   984                                         break;

   985                                     case 0x4:

   986                                         { /* STC.L SPC, @-Rn */

   987                                         uint32_t Rn = ((ir>>8)&0xF);

   988                                         CHECKPRIV();

   989                                         CHECKWALIGN32( sh4r.r[Rn] );

   990                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );

   991                                         sh4r.r[Rn] -= 4;

   992                                         }

   993                                         break;

   994                                     default:

   995                                         UNDEF();

   996                                         break;

   997                                 }

   998                                 break;

   999                             case 0x1:

  1000                                 { /* STC.L Rm_BANK, @-Rn */

  1001                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

  1002                                 CHECKPRIV();

  1003                                 CHECKWALIGN32( sh4r.r[Rn] );

  1004                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );

  1005                                 sh4r.r[Rn] -= 4;

  1006                                 }

  1007                                 break;

  1008                         }

  1009                         break;

  1010                     case 0x4:

  1011                         switch( (ir&0xF0) >> 4 ) {

  1012                             case 0x0:

  1013                                 { /* ROTL Rn */

  1014                                 uint32_t Rn = ((ir>>8)&0xF);

  1015                                 sh4r.t = sh4r.r[Rn] >> 31;

  1016                                 sh4r.r[Rn] <<= 1;

  1017                                 sh4r.r[Rn] |= sh4r.t;

  1018                                 }

  1019                                 break;

  1020                             case 0x2:

  1021                                 { /* ROTCL Rn */

  1022                                 uint32_t Rn = ((ir>>8)&0xF);

  1023                                 tmp = sh4r.r[Rn] >> 31;

  1024                                 sh4r.r[Rn] <<= 1;

  1025                                 sh4r.r[Rn] |= sh4r.t;

  1026                                 sh4r.t = tmp;

  1027                                 }

  1028                                 break;

  1029                             default:

  1030                                 UNDEF();

  1031                                 break;

  1032                         }

  1033                         break;

  1034                     case 0x5:

  1035                         switch( (ir&0xF0) >> 4 ) {

  1036                             case 0x0:

  1037                                 { /* ROTR Rn */

  1038                                 uint32_t Rn = ((ir>>8)&0xF);

  1039                                 sh4r.t = sh4r.r[Rn] & 0x00000001;

  1040                                 sh4r.r[Rn] >>= 1;

  1041                                 sh4r.r[Rn] |= (sh4r.t << 31);

  1042                                 }

  1043                                 break;

  1044                             case 0x1:

  1045                                 { /* CMP/PL Rn */

  1046                                 uint32_t Rn = ((ir>>8)&0xF);

  1047                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );

  1048                                 }

  1049                                 break;

  1050                             case 0x2:

  1051                                 { /* ROTCR Rn */

  1052                                 uint32_t Rn = ((ir>>8)&0xF);

  1053                                 tmp = sh4r.r[Rn] & 0x00000001;

  1054                                 sh4r.r[Rn] >>= 1;

  1055                                 sh4r.r[Rn] |= (sh4r.t << 31 );

  1056                                 sh4r.t = tmp;

  1057                                 }

  1058                                 break;

  1059                             default:

  1060                                 UNDEF();

  1061                                 break;

  1062                         }

  1063                         break;

  1064                     case 0x6:

  1065                         switch( (ir&0xF0) >> 4 ) {

  1066                             case 0x0:

  1067                                 { /* LDS.L @Rm+, MACH */

  1068                                 uint32_t Rm = ((ir>>8)&0xF);

  1069                                 CHECKRALIGN32( sh4r.r[Rm] );

  1070                                 MEM_READ_LONG(sh4r.r[Rm], tmp);

  1071                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

  1072                             	(((uint64_t)tmp)<<32);

  1073                                 sh4r.r[Rm] += 4;

  1074                                 }

  1075                                 break;

  1076                             case 0x1:

  1077                                 { /* LDS.L @Rm+, MACL */

  1078                                 uint32_t Rm = ((ir>>8)&0xF);

  1079                                 CHECKRALIGN32( sh4r.r[Rm] );

  1080                                 MEM_READ_LONG(sh4r.r[Rm], tmp);

  1081                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1082                                            (uint64_t)((uint32_t)tmp);

  1083                                 sh4r.r[Rm] += 4;

  1084                                 }

  1085                                 break;

  1086                             case 0x2:

  1087                                 { /* LDS.L @Rm+, PR */

  1088                                 uint32_t Rm = ((ir>>8)&0xF);

  1089                                 CHECKRALIGN32( sh4r.r[Rm] );

  1090                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );

  1091                                 sh4r.r[Rm] += 4;

  1092                                 }

  1093                                 break;

  1094                             case 0x3:

  1095                                 { /* LDC.L @Rm+, SGR */

  1096                                 uint32_t Rm = ((ir>>8)&0xF);

  1097                                 CHECKPRIV();

  1098                                 CHECKRALIGN32( sh4r.r[Rm] );

  1099                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);

  1100                                 sh4r.r[Rm] +=4;

  1101                                 }

  1102                                 break;

  1103                             case 0x5:

  1104                                 { /* LDS.L @Rm+, FPUL */

  1105                                 uint32_t Rm = ((ir>>8)&0xF);

  1106                                 CHECKRALIGN32( sh4r.r[Rm] );

  1107                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);

  1108                                 sh4r.r[Rm] +=4;

  1109                                 }

  1110                                 break;

  1111                             case 0x6:

  1112                                 { /* LDS.L @Rm+, FPSCR */

  1113                                 uint32_t Rm = ((ir>>8)&0xF);

  1114                                 CHECKRALIGN32( sh4r.r[Rm] );

  1115                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);

  1116                                 sh4r.r[Rm] +=4;

  1117                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];

  1118                                 }

  1119                                 break;

  1120                             case 0xF:

  1121                                 { /* LDC.L @Rm+, DBR */

  1122                                 uint32_t Rm = ((ir>>8)&0xF);

  1123                                 CHECKPRIV();

  1124                                 CHECKRALIGN32( sh4r.r[Rm] );

  1125                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);

  1126                                 sh4r.r[Rm] +=4;

  1127                                 }

  1128                                 break;

  1129                             default:

  1130                                 UNDEF();

  1131                                 break;

  1132                         }

  1133                         break;

  1134                     case 0x7:

  1135                         switch( (ir&0x80) >> 7 ) {

  1136                             case 0x0:

  1137                                 switch( (ir&0x70) >> 4 ) {

  1138                                     case 0x0:

  1139                                         { /* LDC.L @Rm+, SR */

  1140                                         uint32_t Rm = ((ir>>8)&0xF);

  1141                                         CHECKSLOTILLEGAL();

  1142                                         CHECKPRIV();

  1143                                         CHECKWALIGN32( sh4r.r[Rm] );

  1144                                         MEM_READ_LONG(sh4r.r[Rm], tmp);

  1145                                         sh4_write_sr( tmp );

  1146                                         sh4r.r[Rm] +=4;

  1147                                         }

  1148                                         break;

  1149                                     case 0x1:

  1150                                         { /* LDC.L @Rm+, GBR */

  1151                                         uint32_t Rm = ((ir>>8)&0xF);

  1152                                         CHECKRALIGN32( sh4r.r[Rm] );

  1153                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);

  1154                                         sh4r.r[Rm] +=4;

  1155                                         }

  1156                                         break;

  1157                                     case 0x2:

  1158                                         { /* LDC.L @Rm+, VBR */

  1159                                         uint32_t Rm = ((ir>>8)&0xF);

  1160                                         CHECKPRIV();

  1161                                         CHECKRALIGN32( sh4r.r[Rm] );

  1162                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);

  1163                                         sh4r.r[Rm] +=4;

  1164                                         }

  1165                                         break;

  1166                                     case 0x3:

  1167                                         { /* LDC.L @Rm+, SSR */

  1168                                         uint32_t Rm = ((ir>>8)&0xF);

  1169                                         CHECKPRIV();

  1170                                         CHECKRALIGN32( sh4r.r[Rm] );

  1171                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);

  1172                                         sh4r.r[Rm] +=4;

  1173                                         }

  1174                                         break;

  1175                                     case 0x4:

  1176                                         { /* LDC.L @Rm+, SPC */

  1177                                         uint32_t Rm = ((ir>>8)&0xF);

  1178                                         CHECKPRIV();

  1179                                         CHECKRALIGN32( sh4r.r[Rm] );

  1180                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);

  1181                                         sh4r.r[Rm] +=4;

  1182                                         }

  1183                                         break;

  1184                                     default:

  1185                                         UNDEF();

  1186                                         break;

  1187                                 }

  1188                                 break;

  1189                             case 0x1:

  1190                                 { /* LDC.L @Rm+, Rn_BANK */

  1191                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1192                                 CHECKPRIV();

  1193                                 CHECKRALIGN32( sh4r.r[Rm] );

  1194                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );

  1195                                 sh4r.r[Rm] += 4;

  1196                                 }

  1197                                 break;

  1198                         }

  1199                         break;

  1200                     case 0x8:

  1201                         switch( (ir&0xF0) >> 4 ) {

  1202                             case 0x0:

  1203                                 { /* SHLL2 Rn */

  1204                                 uint32_t Rn = ((ir>>8)&0xF);

  1205                                 sh4r.r[Rn] <<= 2;

  1206                                 }

  1207                                 break;

  1208                             case 0x1:

  1209                                 { /* SHLL8 Rn */

  1210                                 uint32_t Rn = ((ir>>8)&0xF);

  1211                                 sh4r.r[Rn] <<= 8;

  1212                                 }

  1213                                 break;

  1214                             case 0x2:

  1215                                 { /* SHLL16 Rn */

  1216                                 uint32_t Rn = ((ir>>8)&0xF);

  1217                                 sh4r.r[Rn] <<= 16;

  1218                                 }

  1219                                 break;

  1220                             default:

  1221                                 UNDEF();

  1222                                 break;

  1223                         }

  1224                         break;

  1225                     case 0x9:

  1226                         switch( (ir&0xF0) >> 4 ) {

  1227                             case 0x0:

  1228                                 { /* SHLR2 Rn */

  1229                                 uint32_t Rn = ((ir>>8)&0xF);

  1230                                 sh4r.r[Rn] >>= 2;

  1231                                 }

  1232                                 break;

  1233                             case 0x1:

  1234                                 { /* SHLR8 Rn */

  1235                                 uint32_t Rn = ((ir>>8)&0xF);

  1236                                 sh4r.r[Rn] >>= 8;

  1237                                 }

  1238                                 break;

  1239                             case 0x2:

  1240                                 { /* SHLR16 Rn */

  1241                                 uint32_t Rn = ((ir>>8)&0xF);

  1242                                 sh4r.r[Rn] >>= 16;

  1243                                 }

  1244                                 break;

  1245                             default:

  1246                                 UNDEF();

  1247                                 break;

  1248                         }

  1249                         break;

  1250                     case 0xA:

  1251                         switch( (ir&0xF0) >> 4 ) {

  1252                             case 0x0:

  1253                                 { /* LDS Rm, MACH */

  1254                                 uint32_t Rm = ((ir>>8)&0xF);

  1255                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

  1256                                            (((uint64_t)sh4r.r[Rm])<<32);

  1257                                 }

  1258                                 break;

  1259                             case 0x1:

  1260                                 { /* LDS Rm, MACL */

  1261                                 uint32_t Rm = ((ir>>8)&0xF);

  1262                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1263                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));

  1264                                 }

  1265                                 break;

  1266                             case 0x2:

  1267                                 { /* LDS Rm, PR */

  1268                                 uint32_t Rm = ((ir>>8)&0xF);

  1269                                 sh4r.pr = sh4r.r[Rm];

  1270                                 }

  1271                                 break;

  1272                             case 0x3:

  1273                                 { /* LDC Rm, SGR */

  1274                                 uint32_t Rm = ((ir>>8)&0xF);

  1275                                 CHECKPRIV();

  1276                                 sh4r.sgr = sh4r.r[Rm];

  1277                                 }

  1278                                 break;

  1279                             case 0x5:

  1280                                 { /* LDS Rm, FPUL */

  1281                                 uint32_t Rm = ((ir>>8)&0xF);

  1282                                 sh4r.fpul = sh4r.r[Rm];

  1283                                 }

  1284                                 break;

  1285                             case 0x6:

  1286                                 { /* LDS Rm, FPSCR */

  1287                                 uint32_t Rm = ((ir>>8)&0xF);

  1288                                 sh4r.fpscr = sh4r.r[Rm];

  1289                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];

  1290                                 }

  1291                                 break;

  1292                             case 0xF:

  1293                                 { /* LDC Rm, DBR */

  1294                                 uint32_t Rm = ((ir>>8)&0xF);

  1295                                 CHECKPRIV();

  1296                                 sh4r.dbr = sh4r.r[Rm];

  1297                                 }

  1298                                 break;

  1299                             default:

  1300                                 UNDEF();

  1301                                 break;

  1302                         }

  1303                         break;

  1304                     case 0xB:

  1305                         switch( (ir&0xF0) >> 4 ) {

  1306                             case 0x0:

  1307                                 { /* JSR @Rn */

  1308                                 uint32_t Rn = ((ir>>8)&0xF);

  1309                                 CHECKDEST( sh4r.r[Rn] );

  1310                                 CHECKSLOTILLEGAL();

  1311                                 sh4r.in_delay_slot = 1;

  1312                                 sh4r.pc = sh4r.new_pc;

  1313                                 sh4r.new_pc = sh4r.r[Rn];

  1314                                 sh4r.pr = pc + 4;

  1315                                 TRACE_CALL( pc, sh4r.new_pc );

  1316                                 return TRUE;

  1317                                 }

  1318                                 break;

  1319                             case 0x1:

  1320                                 { /* TAS.B @Rn */

  1321                                 uint32_t Rn = ((ir>>8)&0xF);

  1322                                 MEM_READ_BYTE( sh4r.r[Rn], tmp );

  1323                                 sh4r.t = ( tmp == 0 ? 1 : 0 );

  1324                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );

  1325                                 }

  1326                                 break;

  1327                             case 0x2:

  1328                                 { /* JMP @Rn */

  1329                                 uint32_t Rn = ((ir>>8)&0xF);

  1330                                 CHECKDEST( sh4r.r[Rn] );

  1331                                 CHECKSLOTILLEGAL();

  1332                                 sh4r.in_delay_slot = 1;

  1333                                 sh4r.pc = sh4r.new_pc;

  1334                                 sh4r.new_pc = sh4r.r[Rn];

  1335                                 return TRUE;

  1336                                 }

  1337                                 break;

  1338                             default:

  1339                                 UNDEF();

  1340                                 break;

  1341                         }

  1342                         break;

  1343                     case 0xC:

  1344                         { /* SHAD Rm, Rn */

  1345                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1346                         tmp = sh4r.r[Rm];

  1347                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

  1348                         else if( (tmp & 0x1F) == 0 )

  1349                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;

  1350                         else

  1351                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);

  1352                         }

  1353                         break;

  1354                     case 0xD:

  1355                         { /* SHLD Rm, Rn */

  1356                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1357                         tmp = sh4r.r[Rm];

  1358                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

  1359                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;

  1360                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);

  1361                         }

  1362                         break;

  1363                     case 0xE:

  1364                         switch( (ir&0x80) >> 7 ) {

  1365                             case 0x0:

  1366                                 switch( (ir&0x70) >> 4 ) {

  1367                                     case 0x0:

  1368                                         { /* LDC Rm, SR */

  1369                                         uint32_t Rm = ((ir>>8)&0xF);

  1370                                         CHECKSLOTILLEGAL();

  1371                                         CHECKPRIV();

  1372                                         sh4_write_sr( sh4r.r[Rm] );

  1373                                         }

  1374                                         break;

  1375                                     case 0x1:

  1376                                         { /* LDC Rm, GBR */

  1377                                         uint32_t Rm = ((ir>>8)&0xF);

  1378                                         sh4r.gbr = sh4r.r[Rm];

  1379                                         }

  1380                                         break;

  1381                                     case 0x2:

  1382                                         { /* LDC Rm, VBR */

  1383                                         uint32_t Rm = ((ir>>8)&0xF);

  1384                                         CHECKPRIV();

  1385                                         sh4r.vbr = sh4r.r[Rm];

  1386                                         }

  1387                                         break;

  1388                                     case 0x3:

  1389                                         { /* LDC Rm, SSR */

  1390                                         uint32_t Rm = ((ir>>8)&0xF);

  1391                                         CHECKPRIV();

  1392                                         sh4r.ssr = sh4r.r[Rm];

  1393                                         }

  1394                                         break;

  1395                                     case 0x4:

  1396                                         { /* LDC Rm, SPC */

  1397                                         uint32_t Rm = ((ir>>8)&0xF);

  1398                                         CHECKPRIV();

  1399                                         sh4r.spc = sh4r.r[Rm];

  1400                                         }

  1401                                         break;

  1402                                     default:

  1403                                         UNDEF();

  1404                                         break;

  1405                                 }

  1406                                 break;

  1407                             case 0x1:

  1408                                 { /* LDC Rm, Rn_BANK */

  1409                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1410                                 CHECKPRIV();

  1411                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];

  1412                                 }

  1413                                 break;

  1414                         }

  1415                         break;

  1416                     case 0xF:

  1417                         { /* MAC.W @Rm+, @Rn+ */

  1418                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1419                         int32_t stmp;

  1420                         if( Rm == Rn ) {

  1421                     	CHECKRALIGN16(sh4r.r[Rn]);

  1422                     	MEM_READ_WORD( sh4r.r[Rn], tmp );

  1423                     	stmp = SIGNEXT16(tmp);

  1424                     	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );

  1425                     	stmp *= SIGNEXT16(tmp);

  1426                     	sh4r.r[Rn] += 4;

  1427                         } else {

  1428                     	CHECKRALIGN16( sh4r.r[Rn] );

  1429                     	CHECKRALIGN16( sh4r.r[Rm] );

  1430                     	MEM_READ_WORD(sh4r.r[Rn], tmp);

  1431                     	stmp = SIGNEXT16(tmp);

  1432                     	MEM_READ_WORD(sh4r.r[Rm], tmp);

  1433                     	stmp = stmp * SIGNEXT16(tmp);

  1434                     	sh4r.r[Rn] += 2;

  1435                     	sh4r.r[Rm] += 2;

  1436                         }

  1437                         if( sh4r.s ) {

  1438                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;

  1439                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {

  1440                     	    sh4r.mac = 0x000000017FFFFFFFLL;

  1441                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {

  1442                     	    sh4r.mac = 0x0000000180000000LL;

  1443                     	} else {

  1444                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1445                     		((uint32_t)(sh4r.mac + stmp));

  1446                     	}

  1447                         } else {

  1448                     	sh4r.mac += SIGNEXT32(stmp);

  1449                         }

  1450                         }

  1451                         break;

  1452                 }

  1453                 break;

  1454             case 0x5:

  1455                 { /* MOV.L @(disp, Rm), Rn */

  1456                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

  1457                 tmp = sh4r.r[Rm] + disp;

  1458                 CHECKRALIGN32( tmp );

  1459                 MEM_READ_LONG( tmp, sh4r.r[Rn] );

  1460                 }

  1461                 break;

  1462             case 0x6:

  1463                 switch( ir&0xF ) {

  1464                     case 0x0:

  1465                         { /* MOV.B @Rm, Rn */

  1466                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1467                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] );

  1468                         }

  1469                         break;

  1470                     case 0x1:

  1471                         { /* MOV.W @Rm, Rn */

  1472                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1473                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] );

  1474                         }

  1475                         break;

  1476                     case 0x2:

  1477                         { /* MOV.L @Rm, Rn */

  1478                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1479                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] );

  1480                         }

  1481                         break;

  1482                     case 0x3:

  1483                         { /* MOV Rm, Rn */

  1484                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1485                         sh4r.r[Rn] = sh4r.r[Rm];

  1486                         }

  1487                         break;

  1488                     case 0x4:

  1489                         { /* MOV.B @Rm+, Rn */

  1490                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1491                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++;

  1492                         }

  1493                         break;

  1494                     case 0x5:

  1495                         { /* MOV.W @Rm+, Rn */

  1496                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1497                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2;

  1498                         }

  1499                         break;

  1500                     case 0x6:

  1501                         { /* MOV.L @Rm+, Rn */

  1502                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1503                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4;

  1504                         }

  1505                         break;

  1506                     case 0x7:

  1507                         { /* NOT Rm, Rn */

  1508                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1509                         sh4r.r[Rn] = ~sh4r.r[Rm];

  1510                         }

  1511                         break;

  1512                     case 0x8:

  1513                         { /* SWAP.B Rm, Rn */

  1514                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1515                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);

  1516                         }

  1517                         break;

  1518                     case 0x9:

  1519                         { /* SWAP.W Rm, Rn */

  1520                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1521                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);

  1522                         }

  1523                         break;

  1524                     case 0xA:

  1525                         { /* NEGC Rm, Rn */

  1526                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1527                         tmp = 0 - sh4r.r[Rm];

  1528                         sh4r.r[Rn] = tmp - sh4r.t;

  1529                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );

  1530                         }

  1531                         break;

  1532                     case 0xB:

  1533                         { /* NEG Rm, Rn */

  1534                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1535                         sh4r.r[Rn] = 0 - sh4r.r[Rm];

  1536                         }

  1537                         break;

  1538                     case 0xC:

  1539                         { /* EXTU.B Rm, Rn */

  1540                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1541                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;

  1542                         }

  1543                         break;

  1544                     case 0xD:

  1545                         { /* EXTU.W Rm, Rn */

  1546                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1547                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;

  1548                         }

  1549                         break;

  1550                     case 0xE:

  1551                         { /* EXTS.B Rm, Rn */

  1552                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1553                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );

  1554                         }

  1555                         break;

  1556                     case 0xF:

  1557                         { /* EXTS.W Rm, Rn */

  1558                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1559                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );

  1560                         }

  1561                         break;

  1562                 }

  1563                 break;

  1564             case 0x7:

  1565                 { /* ADD #imm, Rn */

  1566                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1567                 sh4r.r[Rn] += imm;

  1568                 }

  1569                 break;

  1570             case 0x8:

  1571                 switch( (ir&0xF00) >> 8 ) {

  1572                     case 0x0:

  1573                         { /* MOV.B R0, @(disp, Rn) */

  1574                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1575                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );

  1576                         }

  1577                         break;

  1578                     case 0x1:

  1579                         { /* MOV.W R0, @(disp, Rn) */

  1580                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1581                         tmp = sh4r.r[Rn] + disp;

  1582                         CHECKWALIGN16( tmp );

  1583                         MEM_WRITE_WORD( tmp, R0 );

  1584                         }

  1585                         break;

  1586                     case 0x4:

  1587                         { /* MOV.B @(disp, Rm), R0 */

  1588                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1589                         MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 );

  1590                         }

  1591                         break;

  1592                     case 0x5:

  1593                         { /* MOV.W @(disp, Rm), R0 */

  1594                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1595                         tmp = sh4r.r[Rm] + disp;

  1596                         CHECKRALIGN16( tmp );

  1597                         MEM_READ_WORD( tmp, R0 );

  1598                         }

  1599                         break;

  1600                     case 0x8:

  1601                         { /* CMP/EQ #imm, R0 */

  1602                         int32_t imm = SIGNEXT8(ir&0xFF);

  1603                         sh4r.t = ( R0 == imm ? 1 : 0 );

  1604                         }

  1605                         break;

  1606                     case 0x9:

  1607                         { /* BT disp */

  1608                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1609                         CHECKSLOTILLEGAL();

  1610                         if( sh4r.t ) {

  1611                             CHECKDEST( sh4r.pc + disp + 4 )

  1612                             sh4r.pc += disp + 4;

  1613                             sh4r.new_pc = sh4r.pc + 2;

  1614                             return TRUE;

  1615                         }

  1616                         }

  1617                         break;

  1618                     case 0xB:

  1619                         { /* BF disp */

  1620                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1621                         CHECKSLOTILLEGAL();

  1622                         if( !sh4r.t ) {

  1623                             CHECKDEST( sh4r.pc + disp + 4 )

  1624                             sh4r.pc += disp + 4;

  1625                             sh4r.new_pc = sh4r.pc + 2;

  1626                             return TRUE;

  1627                         }

  1628                         }

  1629                         break;

  1630                     case 0xD:

  1631                         { /* BT/S disp */

  1632                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1633                         CHECKSLOTILLEGAL();

  1634                         if( sh4r.t ) {

  1635                             CHECKDEST( sh4r.pc + disp + 4 )

  1636                             sh4r.in_delay_slot = 1;

  1637                             sh4r.pc = sh4r.new_pc;

  1638                             sh4r.new_pc = pc + disp + 4;

  1639                             sh4r.in_delay_slot = 1;

  1640                             return TRUE;

  1641                         }

  1642                         }

  1643                         break;

  1644                     case 0xF:

  1645                         { /* BF/S disp */

  1646                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1647                         CHECKSLOTILLEGAL();

  1648                         if( !sh4r.t ) {

  1649                             CHECKDEST( sh4r.pc + disp + 4 )

  1650                             sh4r.in_delay_slot = 1;

  1651                             sh4r.pc = sh4r.new_pc;

  1652                             sh4r.new_pc = pc + disp + 4;

  1653                             return TRUE;

  1654                         }

  1655                         }

  1656                         break;

  1657                     default:

  1658                         UNDEF();

  1659                         break;

  1660                 }

  1661                 break;

  1662             case 0x9:

  1663                 { /* MOV.W @(disp, PC), Rn */

  1664                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;

  1665                 CHECKSLOTILLEGAL();

  1666                 tmp = pc + 4 + disp;

  1667                 MEM_READ_WORD( tmp, sh4r.r[Rn] );

  1668                 }

  1669                 break;

  1670             case 0xA:

  1671                 { /* BRA disp */

  1672                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1673                 CHECKSLOTILLEGAL();

  1674                 CHECKDEST( sh4r.pc + disp + 4 );

  1675                 sh4r.in_delay_slot = 1;

  1676                 sh4r.pc = sh4r.new_pc;

  1677                 sh4r.new_pc = pc + 4 + disp;

  1678                 return TRUE;

  1679                 }

  1680                 break;

  1681             case 0xB:

  1682                 { /* BSR disp */

  1683                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1684                 CHECKDEST( sh4r.pc + disp + 4 );

  1685                 CHECKSLOTILLEGAL();

  1686                 sh4r.in_delay_slot = 1;

  1687                 sh4r.pr = pc + 4;

  1688                 sh4r.pc = sh4r.new_pc;

  1689                 sh4r.new_pc = pc + 4 + disp;

  1690                 TRACE_CALL( pc, sh4r.new_pc );

  1691                 return TRUE;

  1692                 }

  1693                 break;

  1694             case 0xC:

  1695                 switch( (ir&0xF00) >> 8 ) {

  1696                     case 0x0:

  1697                         { /* MOV.B R0, @(disp, GBR) */

  1698                         uint32_t disp = (ir&0xFF);

  1699                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );

  1700                         }

  1701                         break;

  1702                     case 0x1:

  1703                         { /* MOV.W R0, @(disp, GBR) */

  1704                         uint32_t disp = (ir&0xFF)<<1;

  1705                         tmp = sh4r.gbr + disp;

  1706                         CHECKWALIGN16( tmp );

  1707                         MEM_WRITE_WORD( tmp, R0 );

  1708                         }

  1709                         break;

  1710                     case 0x2:

  1711                         { /* MOV.L R0, @(disp, GBR) */

  1712                         uint32_t disp = (ir&0xFF)<<2;

  1713                         tmp = sh4r.gbr + disp;

  1714                         CHECKWALIGN32( tmp );

  1715                         MEM_WRITE_LONG( tmp, R0 );

  1716                         }

  1717                         break;

  1718                     case 0x3:

  1719                         { /* TRAPA #imm */

  1720                         uint32_t imm = (ir&0xFF);

  1721                         CHECKSLOTILLEGAL();

  1722                         sh4r.pc += 2;

  1723                         sh4_raise_trap( imm );

  1724                         return TRUE;

  1725                         }

  1726                         break;

  1727                     case 0x4:

  1728                         { /* MOV.B @(disp, GBR), R0 */

  1729                         uint32_t disp = (ir&0xFF);

  1730                         MEM_READ_BYTE( sh4r.gbr + disp, R0 );

  1731                         }

  1732                         break;

  1733                     case 0x5:

  1734                         { /* MOV.W @(disp, GBR), R0 */

  1735                         uint32_t disp = (ir&0xFF)<<1;

  1736                         tmp = sh4r.gbr + disp;

  1737                         CHECKRALIGN16( tmp );

  1738                         MEM_READ_WORD( tmp, R0 );

  1739                         }

  1740                         break;

  1741                     case 0x6:

  1742                         { /* MOV.L @(disp, GBR), R0 */

  1743                         uint32_t disp = (ir&0xFF)<<2;

  1744                         tmp = sh4r.gbr + disp;

  1745                         CHECKRALIGN32( tmp );

  1746                         MEM_READ_LONG( tmp, R0 );

  1747                         }

  1748                         break;

  1749                     case 0x7:

  1750                         { /* MOVA @(disp, PC), R0 */

  1751                         uint32_t disp = (ir&0xFF)<<2;

  1752                         CHECKSLOTILLEGAL();

  1753                         R0 = (pc&0xFFFFFFFC) + disp + 4;

  1754                         }

  1755                         break;

  1756                     case 0x8:

  1757                         { /* TST #imm, R0 */

  1758                         uint32_t imm = (ir&0xFF);

  1759                         sh4r.t = (R0 & imm ? 0 : 1);

  1760                         }

  1761                         break;

  1762                     case 0x9:

  1763                         { /* AND #imm, R0 */

  1764                         uint32_t imm = (ir&0xFF);

  1765                         R0 &= imm;

  1766                         }

  1767                         break;

  1768                     case 0xA:

  1769                         { /* XOR #imm, R0 */

  1770                         uint32_t imm = (ir&0xFF);

  1771                         R0 ^= imm;

  1772                         }

  1773                         break;

  1774                     case 0xB:

  1775                         { /* OR #imm, R0 */

  1776                         uint32_t imm = (ir&0xFF);

  1777                         R0 |= imm;

  1778                         }

  1779                         break;

  1780                     case 0xC:

  1781                         { /* TST.B #imm, @(R0, GBR) */

  1782                         uint32_t imm = (ir&0xFF);

  1783                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 );

  1784                         }

  1785                         break;

  1786                     case 0xD:

  1787                         { /* AND.B #imm, @(R0, GBR) */

  1788                         uint32_t imm = (ir&0xFF);

  1789                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp );

  1790                         }

  1791                         break;

  1792                     case 0xE:

  1793                         { /* XOR.B #imm, @(R0, GBR) */

  1794                         uint32_t imm = (ir&0xFF);

  1795                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp );

  1796                         }

  1797                         break;

  1798                     case 0xF:

  1799                         { /* OR.B #imm, @(R0, GBR) */

  1800                         uint32_t imm = (ir&0xFF);

  1801                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp );

  1802                         }

  1803                         break;

  1804                 }

  1805                 break;

  1806             case 0xD:

  1807                 { /* MOV.L @(disp, PC), Rn */

  1808                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;

  1809                 CHECKSLOTILLEGAL();

  1810                 tmp = (pc&0xFFFFFFFC) + disp + 4;

  1811                 MEM_READ_LONG( tmp, sh4r.r[Rn] );

  1812                 }

  1813                 break;

  1814             case 0xE:

  1815                 { /* MOV #imm, Rn */

  1816                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1817                 sh4r.r[Rn] = imm;

  1818                 }

  1819                 break;

  1820             case 0xF:

  1821                 switch( ir&0xF ) {

  1822                     case 0x0:

  1823                         { /* FADD FRm, FRn */

  1824                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1825                         CHECKFPUEN();

  1826                         if( IS_FPU_DOUBLEPREC() ) {

  1827                     	DR(FRn) += DR(FRm);

  1828                         } else {

  1829                     	FR(FRn) += FR(FRm);

  1830                         }

  1831                         }

  1832                         break;

  1833                     case 0x1:

  1834                         { /* FSUB FRm, FRn */

  1835                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1836                         CHECKFPUEN();

  1837                         if( IS_FPU_DOUBLEPREC() ) {

  1838                     	DR(FRn) -= DR(FRm);

  1839                         } else {

  1840                     	FR(FRn) -= FR(FRm);

  1841                         }

  1842                         }

  1843                         break;

  1844                     case 0x2:

  1845                         { /* FMUL FRm, FRn */

  1846                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1847                         CHECKFPUEN();

  1848                         if( IS_FPU_DOUBLEPREC() ) {

  1849                     	DR(FRn) *= DR(FRm);

  1850                         } else {

  1851                     	FR(FRn) *= FR(FRm);

  1852                         }

  1853                         }

  1854                         break;

  1855                     case 0x3:

  1856                         { /* FDIV FRm, FRn */

  1857                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1858                         CHECKFPUEN();

  1859                         if( IS_FPU_DOUBLEPREC() ) {

  1860                     	DR(FRn) /= DR(FRm);

  1861                         } else {

  1862                     	FR(FRn) /= FR(FRm);

  1863                         }

  1864                         }

  1865                         break;

  1866                     case 0x4:

  1867                         { /* FCMP/EQ FRm, FRn */

  1868                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1869                         CHECKFPUEN();

  1870                         if( IS_FPU_DOUBLEPREC() ) {

  1871                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );

  1872                         } else {

  1873                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );

  1874                         }

  1875                         }

  1876                         break;

  1877                     case 0x5:

  1878                         { /* FCMP/GT FRm, FRn */

  1879                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1880                         CHECKFPUEN();

  1881                         if( IS_FPU_DOUBLEPREC() ) {

  1882                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );

  1883                         } else {

  1884                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );

  1885                         }

  1886                         }

  1887                         break;

  1888                     case 0x6:

  1889                         { /* FMOV @(R0, Rm), FRn */

  1890                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1891                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );

  1892                         }

  1893                         break;

  1894                     case 0x7:

  1895                         { /* FMOV FRm, @(R0, Rn) */

  1896                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1897                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );

  1898                         }

  1899                         break;

  1900                     case 0x8:

  1901                         { /* FMOV @Rm, FRn */

  1902                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1903                         MEM_FP_READ( sh4r.r[Rm], FRn );

  1904                         }

  1905                         break;

  1906                     case 0x9:

  1907                         { /* FMOV @Rm+, FRn */

  1908                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1909                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;

  1910                         }

  1911                         break;

  1912                     case 0xA:

  1913                         { /* FMOV FRm, @Rn */

  1914                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1915                         MEM_FP_WRITE( sh4r.r[Rn], FRm );

  1916                         }

  1917                         break;

  1918                     case 0xB:

  1919                         { /* FMOV FRm, @-Rn */

  1920                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1921                         MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH;

  1922                         }

  1923                         break;

  1924                     case 0xC:

  1925                         { /* FMOV FRm, FRn */

  1926                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1927                         if( IS_FPU_DOUBLESIZE() )

  1928                     	DR(FRn) = DR(FRm);

  1929                         else

  1930                     	FR(FRn) = FR(FRm);

  1931                         }

  1932                         break;

  1933                     case 0xD:

  1934                         switch( (ir&0xF0) >> 4 ) {

  1935                             case 0x0:

  1936                                 { /* FSTS FPUL, FRn */

  1937                                 uint32_t FRn = ((ir>>8)&0xF);

  1938                                 CHECKFPUEN(); FR(FRn) = FPULf;

  1939                                 }

  1940                                 break;

  1941                             case 0x1:

  1942                                 { /* FLDS FRm, FPUL */

  1943                                 uint32_t FRm = ((ir>>8)&0xF);

  1944                                 CHECKFPUEN(); FPULf = FR(FRm);

  1945                                 }

  1946                                 break;

  1947                             case 0x2:

  1948                                 { /* FLOAT FPUL, FRn */

  1949                                 uint32_t FRn = ((ir>>8)&0xF);

  1950                                 CHECKFPUEN();

  1951                                 if( IS_FPU_DOUBLEPREC() ) {

  1952                             	if( FRn&1 ) { // No, really...

  1953                             	    dtmp = (double)FPULi;

  1954                             	    FR(FRn) = *(((float *)&dtmp)+1);

  1955                             	} else {

  1956                             	    DRF(FRn>>1) = (double)FPULi;

  1957                             	}

  1958                                 } else {

  1959                             	FR(FRn) = (float)FPULi;

  1960                                 }

  1961                                 }

  1962                                 break;

  1963                             case 0x3:

  1964                                 { /* FTRC FRm, FPUL */

  1965                                 uint32_t FRm = ((ir>>8)&0xF);

  1966                                 CHECKFPUEN();

  1967                                 if( IS_FPU_DOUBLEPREC() ) {

  1968                             	if( FRm&1 ) {

  1969                             	    dtmp = 0;

  1970                             	    *(((float *)&dtmp)+1) = FR(FRm);

  1971                             	} else {

  1972                             	    dtmp = DRF(FRm>>1);

  1973                             	}

  1974                                     if( dtmp >= MAX_INTF )

  1975                                         FPULi = MAX_INT;

  1976                                     else if( dtmp <= MIN_INTF )

  1977                                         FPULi = MIN_INT;

  1978                                     else

  1979                                         FPULi = (int32_t)dtmp;

  1980                                 } else {

  1981                             	ftmp = FR(FRm);

  1982                             	if( ftmp >= MAX_INTF )

  1983                             	    FPULi = MAX_INT;

  1984                             	else if( ftmp <= MIN_INTF )

  1985                             	    FPULi = MIN_INT;

  1986                             	else

  1987                             	    FPULi = (int32_t)ftmp;

  1988                                 }

  1989                                 }

  1990                                 break;

  1991                             case 0x4:

  1992                                 { /* FNEG FRn */

  1993                                 uint32_t FRn = ((ir>>8)&0xF);

  1994                                 CHECKFPUEN();

  1995                                 if( IS_FPU_DOUBLEPREC() ) {

  1996                             	DR(FRn) = -DR(FRn);

  1997                                 } else {

  1998                                     FR(FRn) = -FR(FRn);

  1999                                 }

  2000                                 }

  2001                                 break;

  2002                             case 0x5:

  2003                                 { /* FABS FRn */

  2004                                 uint32_t FRn = ((ir>>8)&0xF);

  2005                                 CHECKFPUEN();

  2006                                 if( IS_FPU_DOUBLEPREC() ) {

  2007                             	DR(FRn) = fabs(DR(FRn));

  2008                                 } else {

  2009                                     FR(FRn) = fabsf(FR(FRn));

  2010                                 }

  2011                                 }

  2012                                 break;

  2013                             case 0x6:

  2014                                 { /* FSQRT FRn */

  2015                                 uint32_t FRn = ((ir>>8)&0xF);

  2016                                 CHECKFPUEN();

  2017                                 if( IS_FPU_DOUBLEPREC() ) {

  2018                             	DR(FRn) = sqrt(DR(FRn));

  2019                                 } else {

  2020                                     FR(FRn) = sqrtf(FR(FRn));

  2021                                 }

  2022                                 }

  2023                                 break;

  2024                             case 0x7:

  2025                                 { /* FSRRA FRn */

  2026                                 uint32_t FRn = ((ir>>8)&0xF);

  2027                                 CHECKFPUEN();

  2028                                 if( !IS_FPU_DOUBLEPREC() ) {

  2029                             	FR(FRn) = 1.0/sqrtf(FR(FRn));

  2030                                 }

  2031                                 }

  2032                                 break;

  2033                             case 0x8:

  2034                                 { /* FLDI0 FRn */

  2035                                 uint32_t FRn = ((ir>>8)&0xF);

  2036                                 CHECKFPUEN();

  2037                                 if( IS_FPU_DOUBLEPREC() ) {

  2038                             	DR(FRn) = 0.0;

  2039                                 } else {

  2040                                     FR(FRn) = 0.0;

  2041                                 }

  2042                                 }

  2043                                 break;

  2044                             case 0x9:

  2045                                 { /* FLDI1 FRn */

  2046                                 uint32_t FRn = ((ir>>8)&0xF);

  2047                                 CHECKFPUEN();

  2048                                 if( IS_FPU_DOUBLEPREC() ) {

  2049                             	DR(FRn) = 1.0;

  2050                                 } else {

  2051                                     FR(FRn) = 1.0;

  2052                                 }

  2053                                 }

  2054                                 break;

  2055                             case 0xA:

  2056                                 { /* FCNVSD FPUL, FRn */

  2057                                 uint32_t FRn = ((ir>>8)&0xF);

  2058                                 CHECKFPUEN();

  2059                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

  2060                             	DR(FRn) = (double)FPULf;

  2061                                 }

  2062                                 }

  2063                                 break;

  2064                             case 0xB:

  2065                                 { /* FCNVDS FRm, FPUL */

  2066                                 uint32_t FRm = ((ir>>8)&0xF);

  2067                                 CHECKFPUEN();

  2068                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

  2069                             	FPULf = (float)DR(FRm);

  2070                                 }

  2071                                 }

  2072                                 break;

  2073                             case 0xE:

  2074                                 { /* FIPR FVm, FVn */

  2075                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);

  2076                                 CHECKFPUEN();

  2077                                 if( !IS_FPU_DOUBLEPREC() ) {

  2078                                     int tmp2 = FVn<<2;

  2079                                     tmp = FVm<<2;

  2080                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +

  2081                                         FR(tmp+1)*FR(tmp2+1) +

  2082                                         FR(tmp+2)*FR(tmp2+2) +

  2083                                         FR(tmp+3)*FR(tmp2+3);

  2084                                 }

  2085                                 }

  2086                                 break;

  2087                             case 0xF:

  2088                                 switch( (ir&0x100) >> 8 ) {

  2089                                     case 0x0:

  2090                                         { /* FSCA FPUL, FRn */

  2091                                         uint32_t FRn = ((ir>>9)&0x7)<<1;

  2092                                         CHECKFPUEN();

  2093                                         if( !IS_FPU_DOUBLEPREC() ) {

  2094                                     	sh4_fsca( FPULi, &(DRF(FRn>>1)) );

  2095                                     	/*

  2096                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;

  2097                                             FR(FRn) = sinf(angle);

  2098                                             FR((FRn)+1) = cosf(angle);

  2099                                     	*/

  2100                                         }

  2101                                         }

  2102                                         break;

  2103                                     case 0x1:

  2104                                         switch( (ir&0x200) >> 9 ) {

  2105                                             case 0x0:

  2106                                                 { /* FTRV XMTRX, FVn */

  2107                                                 uint32_t FVn = ((ir>>10)&0x3);

  2108                                                 CHECKFPUEN();

  2109                                                 if( !IS_FPU_DOUBLEPREC() ) {

  2110                                             	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);

  2111                                             	/*

  2112                                                     tmp = FVn<<2;

  2113                                             	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];

  2114                                                     float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };

  2115                                                     FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +

  2116                                             	    xf[9]*fv[2] + xf[13]*fv[3];

  2117                                                     FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +

  2118                                             	    xf[8]*fv[2] + xf[12]*fv[3];

  2119                                                     FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +

  2120                                             	    xf[11]*fv[2] + xf[15]*fv[3];

  2121                                                     FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +

  2122                                             	    xf[10]*fv[2] + xf[14]*fv[3];

  2123                                             	*/

  2124                                                 }

  2125                                                 }

  2126                                                 break;

  2127                                             case 0x1:

  2128                                                 switch( (ir&0xC00) >> 10 ) {

  2129                                                     case 0x0:

  2130                                                         { /* FSCHG */

  2131                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;

  2132                                                         }

  2133                                                         break;

  2134                                                     case 0x2:

  2135                                                         { /* FRCHG */

  2136                                                         CHECKFPUEN();

  2137                                                         sh4r.fpscr ^= FPSCR_FR;

  2138                                                         sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];

  2139                                                         }

  2140                                                         break;

  2141                                                     case 0x3:

  2142                                                         { /* UNDEF */

  2143                                                         UNDEF(ir);

  2144                                                         }

  2145                                                         break;

  2146                                                     default:

  2147                                                         UNDEF();

  2148                                                         break;

  2149                                                 }

  2150                                                 break;

  2151                                         }

  2152                                         break;

  2153                                 }

  2154                                 break;

  2155                             default:

  2156                                 UNDEF();

  2157                                 break;

  2158                         }

  2159                         break;

  2160                     case 0xE:

  2161                         { /* FMAC FR0, FRm, FRn */

  2162                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2163                         CHECKFPUEN();

  2164                         if( IS_FPU_DOUBLEPREC() ) {

  2165                             DR(FRn) += DR(FRm)*DR(0);

  2166                         } else {

  2167                     	FR(FRn) += FR(FRm)*FR(0);

  2168                         }

  2169                         }

  2170                         break;

  2171                     default:

  2172                         UNDEF();

  2173                         break;

  2174                 }

  2175                 break;

  2176         }

  2178     sh4r.pc = sh4r.new_pc;

  2179     sh4r.new_pc += 2;

  2180     sh4r.in_delay_slot = 0;

  2181     return TRUE;

  2182 }