lxdream.org :: lxdream/src/sh4/sh4mmio.c r1:eea311cfd33e

tree revision 6:6e3663e58565

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     1 #include "dream.h"

     2 #include "mem.h"

     3 #include "sh4core.h"

     4 #include "sh4mmio.h"

     5 #define MMIO_IMPL

     6 #include "sh4mmio.h"

     8 /********************************* MMU *************************************/

    10 MMIO_REGION_READ_STUBFN( MMU )

    12 void mmio_region_MMU_write( uint32_t reg, uint32_t val )

    13 {

    14     switch(reg) {

    15         case CCR:

    16             mem_set_cache_mode( val & (CCR_OIX|CCR_ORA) );

    17             INFO( "Cache mode set to %08X", val );

    18             break;

    19         default:

    20             break;

    21     }

    22     MMIO_WRITE( MMU, reg, val );

    23 }

    26 /********************************* BSC *************************************/

    28 uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;

    29 uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;

    30 uint32_t bsc_output = 0, bsc_input = 0x0300;

    32 void bsc_out( int output, int mask )

    33 {

    34     /* Go figure... The BIOS won't start without this mess though */

    35     if( ((output | (~mask)) & 0x03) == 3 ) {

    36         bsc_output |= 0x03;

    37     } else {

    38         bsc_output &= ~0x03;

    39     }

    40 }

    42 void mmio_region_BSC_write( uint32_t reg, uint32_t val )

    43 {

    44     int i;

    45     switch( reg ) {

    46         case PCTRA:

    47             bsc_input_mask_lo = bsc_output_mask_lo = 0;

    48             for( i=0; i<16; i++ ) {

    49                 int bits = (val >> (i<<1)) & 0x03;

    50                 if( bits == 2 ) bsc_input_mask_lo |= (1<<i);

    51                 else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);

    52             }

    53             bsc_output = (bsc_output&0x000F0000) |

    54                 (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);

    55             bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),

    56                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );

    57             break;

    58         case PCTRB:

    59             bsc_input_mask_hi = bsc_output_mask_hi = 0;

    60             for( i=0; i<4; i++ ) {

    61                 int bits = (val >> (i>>1)) & 0x03;

    62                 if( bits == 2 ) bsc_input_mask_hi |= (1<<i);

    63                 else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);

    64             }

    65             bsc_output = (bsc_output&0xFFFF) |

    66                 ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);

    67             break;

    68         case PDTRA:

    69             bsc_output = (bsc_output&0x000F0000) |

    70                 (val & bsc_output_mask_lo );

    71             bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),

    72                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );

    73             break;

    74         case PDTRB:

    75             bsc_output = (bsc_output&0xFFFF) |

    76                 ( (val & bsc_output_mask_hi)<<16 );

    77             break;

    78     }

    79     WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",

    80           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );

    81     MMIO_WRITE( BSC, reg, val );

    82 }

    84 int32_t mmio_region_BSC_read( uint32_t reg )

    85 {

    86     int32_t val;

    87     switch( reg ) {

    88         case PDTRA:

    89             val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);

    90             break;

    91         case PDTRB:

    92             val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);

    93             break;

    94         default:

    95             val = MMIO_READ( BSC, reg );

    96     }

    97     WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",

    98           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );

    99     return val;

   100 }

   102 /********************************* UBC *************************************/

   104 MMIO_REGION_STUBFNS( UBC )

   106 /********************************* CPG *************************************/

   108 MMIO_REGION_STUBFNS( CPG )

   110 /********************************* DMAC *************************************/

   112 MMIO_REGION_STUBFNS( DMAC )

   114 /********************************** RTC *************************************/

   116 MMIO_REGION_STUBFNS( RTC )

   118 /********************************** TMU *************************************/

   120 int timer_divider[3] = {16,16,16};

   121 MMIO_REGION_READ_DEFFN( TMU )

   123 int get_timer_div( int val )

   124 {

   125     switch( val & 0x07 ) {

   126         case 0: return 16; /* assume peripheral clock is IC/4 */

   127         case 1: return 64;

   128         case 2: return 256;

   129         case 3: return 1024;

   130         case 4: return 4096;

   131     }

   132     return 1;

   133 }

   135 void mmio_region_TMU_write( uint32_t reg, uint32_t val )

   136 {

   137     switch( reg ) {

   138         case TCR0:

   139             timer_divider[0] = get_timer_div(val);

   140             break;

   141         case TCR1:

   142             timer_divider[1] = get_timer_div(val);

   143             break;

   144         case TCR2:

   145             timer_divider[2] = get_timer_div(val);

   146             break;

   147     }

   148     MMIO_WRITE( TMU, reg, val );

   149 }

   151 void run_timers( int cycles )

   152 {

   153     int tcr = MMIO_READ( TMU, TSTR );

   154     cycles *= 16;

   155     if( tcr & 1 ) {

   156         int count = cycles / timer_divider[0];

   157         int *val = MMIO_REG( TMU, TCNT0 );

   158         if( *val < count ) {

   159             MMIO_READ( TMU, TCR0 ) |= 0x100;

   160             /* interrupt goes here */

   161             count -= *val;

   162             *val = MMIO_READ( TMU, TCOR0 ) - count;

   163         } else {

   164             *val -= count;

   165         }

   166     }

   167 }

   169 /********************************** SCI *************************************/

   171 MMIO_REGION_STUBFNS( SCI )

   173 /********************************* SCIF *************************************/

   175 MMIO_REGION_STUBFNS( SCIF )