4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
24 #include "dreamcast.h"
29 #include "sh4/sh4core.h"
30 #include "sh4/sh4mmio.h"
33 #define SH4_CALLTRACE 1
35 #define MAX_INT 0x7FFFFFFF
36 #define MIN_INT 0x80000000
37 #define MAX_INTF 2147483647.0
38 #define MIN_INTF -2147483648.0
40 /********************** SH4 Module Definition ****************************/
42 uint32_t sh4_run_slice( uint32_t nanosecs )
47 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
48 if( sh4r.event_pending < nanosecs ) {
49 sh4r.sh4_state = SH4_STATE_RUNNING;
50 sh4r.slice_cycle = sh4r.event_pending;
54 if( sh4_breakpoint_count == 0 ) {
55 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
56 if( SH4_EVENT_PENDING() ) {
57 if( sh4r.event_types & PENDING_EVENT ) {
60 /* Eventq execute may (quite likely) deliver an immediate IRQ */
61 if( sh4r.event_types & PENDING_IRQ ) {
62 sh4_accept_interrupt();
65 if( !sh4_execute_instruction() ) {
70 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
71 if( SH4_EVENT_PENDING() ) {
72 if( sh4r.event_types & PENDING_EVENT ) {
75 /* Eventq execute may (quite likely) deliver an immediate IRQ */
76 if( sh4r.event_types & PENDING_IRQ ) {
77 sh4_accept_interrupt();
81 if( !sh4_execute_instruction() )
83 #ifdef ENABLE_DEBUG_MODE
84 for( i=0; i<sh4_breakpoint_count; i++ ) {
85 if( sh4_breakpoints[i].address == sh4r.pc ) {
89 if( i != sh4_breakpoint_count ) {
91 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
92 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
99 /* If we aborted early, but the cpu is still technically running,
100 * we're doing a hard abort - cut the timeslice back to what we
103 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
104 nanosecs = sh4r.slice_cycle;
106 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
107 TMU_run_slice( nanosecs );
108 SCIF_run_slice( nanosecs );
113 /********************** SH4 emulation core ****************************/
115 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
116 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
118 #if(SH4_CALLTRACE == 1)
119 #define MAX_CALLSTACK 32
120 static struct call_stack {
122 sh4addr_t target_addr;
123 sh4addr_t stack_pointer;
124 } call_stack[MAX_CALLSTACK];
126 static int call_stack_depth = 0;
127 int sh4_call_trace_on = 0;
129 static inline void trace_call( sh4addr_t source, sh4addr_t dest )
131 if( call_stack_depth < MAX_CALLSTACK ) {
132 call_stack[call_stack_depth].call_addr = source;
133 call_stack[call_stack_depth].target_addr = dest;
134 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
139 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
141 if( call_stack_depth > 0 ) {
146 void fprint_stack_trace( FILE *f )
148 int i = call_stack_depth -1;
149 if( i >= MAX_CALLSTACK )
150 i = MAX_CALLSTACK - 1;
151 for( ; i >= 0; i-- ) {
152 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
153 (call_stack_depth - i), call_stack[i].call_addr,
154 call_stack[i].target_addr, call_stack[i].stack_pointer );
158 #define TRACE_CALL( source, dest ) trace_call(source, dest)
159 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
161 #define TRACE_CALL( dest, rts )
162 #define TRACE_RETURN( source, dest )
165 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
166 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
167 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
168 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
169 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
170 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
172 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
174 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
175 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
177 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
178 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
179 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
180 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
181 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
183 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
184 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
185 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
187 static void sh4_write_float( uint32_t addr, int reg )
189 if( IS_FPU_DOUBLESIZE() ) {
191 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
192 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
194 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
195 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
198 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
202 static void sh4_read_float( uint32_t addr, int reg )
204 if( IS_FPU_DOUBLESIZE() ) {
206 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
207 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
209 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
210 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
213 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
217 gboolean sh4_execute_instruction( void )
224 int64_t memtmp; // temporary holder for memory reads
228 if( pc > 0xFFFFFF00 ) {
230 syscall_invoke( pc );
231 sh4r.in_delay_slot = 0;
232 pc = sh4r.pc = sh4r.pr;
233 sh4r.new_pc = sh4r.pc + 2;
237 /* Read instruction */
238 if( !IS_IN_ICACHE(pc) ) {
239 if( !mmu_update_icache(pc) ) {
240 // Fault - look for the fault handler
241 if( !mmu_update_icache(sh4r.pc) ) {
242 // double fault - halt
243 ERROR( "Double fault - halting" );
250 assert( IS_IN_ICACHE(pc) );
251 ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
253 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
254 AND #imm, R0 {: R0 &= imm; :}
255 AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
256 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
257 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
258 OR #imm, R0 {: R0 |= imm; :}
259 OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
261 MEM_READ_BYTE( sh4r.r[Rn], tmp );
262 sh4r.t = ( tmp == 0 ? 1 : 0 );
263 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
265 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
266 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
267 TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
268 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
269 XOR #imm, R0 {: R0 ^= imm; :}
270 XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
271 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
274 sh4r.t = sh4r.r[Rn] >> 31;
276 sh4r.r[Rn] |= sh4r.t;
279 sh4r.t = sh4r.r[Rn] & 0x00000001;
281 sh4r.r[Rn] |= (sh4r.t << 31);
284 tmp = sh4r.r[Rn] >> 31;
286 sh4r.r[Rn] |= sh4r.t;
290 tmp = sh4r.r[Rn] & 0x00000001;
292 sh4r.r[Rn] |= (sh4r.t << 31 );
297 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
298 else if( (tmp & 0x1F) == 0 )
299 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
301 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
305 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
306 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
307 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
310 sh4r.t = sh4r.r[Rn] >> 31;
314 sh4r.t = sh4r.r[Rn] & 0x00000001;
315 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
317 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
318 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
319 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
320 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
321 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
322 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
323 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
324 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
326 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
327 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
328 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
329 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
330 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
331 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
333 CLRT {: sh4r.t = 0; :}
334 SETT {: sh4r.t = 1; :}
335 CLRMAC {: sh4r.mac = 0; :}
336 LDTLB {: MMU_ldtlb(); :}
337 CLRS {: sh4r.s = 0; :}
338 SETS {: sh4r.s = 1; :}
339 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
344 if( (tmp & 0xFC000000) == 0xE0000000 ) {
345 sh4_flush_store_queue(tmp);
354 MEM_WRITE_LONG( tmp, R0 );
356 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
357 MOV.W Rm, @(R0, Rn) {:
358 CHECKWALIGN16( R0 + sh4r.r[Rn] );
359 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
361 MOV.L Rm, @(R0, Rn) {:
362 CHECKWALIGN32( R0 + sh4r.r[Rn] );
363 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
365 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
366 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
367 MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
369 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
370 MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
372 MOV.L Rm, @(disp, Rn) {:
373 tmp = sh4r.r[Rn] + disp;
374 CHECKWALIGN32( tmp );
375 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
377 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
378 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
379 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
380 MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
381 MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
382 MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
383 MOV.L @(disp, Rm), Rn {:
384 tmp = sh4r.r[Rm] + disp;
385 CHECKRALIGN32( tmp );
386 MEM_READ_LONG( tmp, sh4r.r[Rn] );
388 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
389 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
390 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
391 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
392 MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
393 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
394 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
395 MOV.L @(disp, PC), Rn {:
397 tmp = (pc&0xFFFFFFFC) + disp + 4;
398 MEM_READ_LONG( tmp, sh4r.r[Rn] );
400 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
401 MOV.W R0, @(disp, GBR) {:
402 tmp = sh4r.gbr + disp;
403 CHECKWALIGN16( tmp );
404 MEM_WRITE_WORD( tmp, R0 );
406 MOV.L R0, @(disp, GBR) {:
407 tmp = sh4r.gbr + disp;
408 CHECKWALIGN32( tmp );
409 MEM_WRITE_LONG( tmp, R0 );
411 MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
412 MOV.W @(disp, GBR), R0 {:
413 tmp = sh4r.gbr + disp;
414 CHECKRALIGN16( tmp );
415 MEM_READ_WORD( tmp, R0 );
417 MOV.L @(disp, GBR), R0 {:
418 tmp = sh4r.gbr + disp;
419 CHECKRALIGN32( tmp );
420 MEM_READ_LONG( tmp, R0 );
422 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
423 MOV.W R0, @(disp, Rn) {:
424 tmp = sh4r.r[Rn] + disp;
425 CHECKWALIGN16( tmp );
426 MEM_WRITE_WORD( tmp, R0 );
428 MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
429 MOV.W @(disp, Rm), R0 {:
430 tmp = sh4r.r[Rm] + disp;
431 CHECKRALIGN16( tmp );
432 MEM_READ_WORD( tmp, R0 );
434 MOV.W @(disp, PC), Rn {:
437 MEM_READ_WORD( tmp, sh4r.r[Rn] );
439 MOVA @(disp, PC), R0 {:
441 R0 = (pc&0xFFFFFFFC) + disp + 4;
443 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
445 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
446 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
447 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
448 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
449 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
450 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
451 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
452 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
454 /* set T = 1 if any byte in RM & RN is the same */
455 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
456 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
457 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
460 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
461 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
464 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
465 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
468 tmp = sh4r.r[Rn] + sh4r.r[Rm];
469 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
472 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
474 sh4r.q = sh4r.r[Rn]>>31;
475 sh4r.m = sh4r.r[Rm]>>31;
476 sh4r.t = sh4r.q ^ sh4r.m;
479 /* This is derived from the sh4 manual with some simplifications */
480 uint32_t tmp0, tmp1, tmp2, dir;
482 dir = sh4r.q ^ sh4r.m;
483 sh4r.q = (sh4r.r[Rn] >> 31);
485 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
489 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
492 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
494 sh4r.q ^= sh4r.m ^ tmp1;
495 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
497 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
498 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
501 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
506 CHECKRALIGN16(sh4r.r[Rn]);
507 MEM_READ_WORD( sh4r.r[Rn], tmp );
508 stmp = SIGNEXT16(tmp);
509 MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
510 stmp *= SIGNEXT16(tmp);
513 CHECKRALIGN16( sh4r.r[Rn] );
514 CHECKRALIGN16( sh4r.r[Rm] );
515 MEM_READ_WORD(sh4r.r[Rn], tmp);
516 stmp = SIGNEXT16(tmp);
517 MEM_READ_WORD(sh4r.r[Rm], tmp);
518 stmp = stmp * SIGNEXT16(tmp);
523 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
524 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
525 sh4r.mac = 0x000000017FFFFFFFLL;
526 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
527 sh4r.mac = 0x0000000180000000LL;
529 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
530 ((uint32_t)(sh4r.mac + stmp));
533 sh4r.mac += SIGNEXT32(stmp);
539 CHECKRALIGN32( sh4r.r[Rn] );
540 MEM_READ_LONG(sh4r.r[Rn], tmp);
541 tmpl = SIGNEXT32(tmp);
542 MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
543 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
546 CHECKRALIGN32( sh4r.r[Rm] );
547 CHECKRALIGN32( sh4r.r[Rn] );
548 MEM_READ_LONG(sh4r.r[Rn], tmp);
549 tmpl = SIGNEXT32(tmp);
550 MEM_READ_LONG(sh4r.r[Rm], tmp);
551 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
556 /* 48-bit Saturation. Yuch */
557 if( tmpl < (int64_t)0xFFFF800000000000LL )
558 tmpl = 0xFFFF800000000000LL;
559 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
560 tmpl = 0x00007FFFFFFFFFFFLL;
564 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
565 (sh4r.r[Rm] * sh4r.r[Rn]); :}
567 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
568 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
571 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
572 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
575 tmp = 0 - sh4r.r[Rm];
576 sh4r.r[Rn] = tmp - sh4r.t;
577 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
579 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
580 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
583 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
584 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
589 CHECKDEST( pc + 4 + sh4r.r[Rn] );
590 sh4r.in_delay_slot = 1;
591 sh4r.pc = sh4r.new_pc;
592 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
597 CHECKDEST( pc + 4 + sh4r.r[Rn] );
598 sh4r.in_delay_slot = 1;
599 sh4r.pr = sh4r.pc + 4;
600 sh4r.pc = sh4r.new_pc;
601 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
602 TRACE_CALL( pc, sh4r.new_pc );
608 CHECKDEST( sh4r.pc + disp + 4 )
610 sh4r.new_pc = sh4r.pc + 2;
617 CHECKDEST( sh4r.pc + disp + 4 )
619 sh4r.new_pc = sh4r.pc + 2;
626 CHECKDEST( sh4r.pc + disp + 4 )
627 sh4r.in_delay_slot = 1;
628 sh4r.pc = sh4r.new_pc;
629 sh4r.new_pc = pc + disp + 4;
630 sh4r.in_delay_slot = 1;
637 CHECKDEST( sh4r.pc + disp + 4 )
638 sh4r.in_delay_slot = 1;
639 sh4r.pc = sh4r.new_pc;
640 sh4r.new_pc = pc + disp + 4;
646 CHECKDEST( sh4r.pc + disp + 4 );
647 sh4r.in_delay_slot = 1;
648 sh4r.pc = sh4r.new_pc;
649 sh4r.new_pc = pc + 4 + disp;
653 CHECKDEST( sh4r.pc + disp + 4 );
655 sh4r.in_delay_slot = 1;
657 sh4r.pc = sh4r.new_pc;
658 sh4r.new_pc = pc + 4 + disp;
659 TRACE_CALL( pc, sh4r.new_pc );
665 sh4_raise_trap( imm );
670 CHECKDEST( sh4r.pr );
671 sh4r.in_delay_slot = 1;
672 sh4r.pc = sh4r.new_pc;
673 sh4r.new_pc = sh4r.pr;
674 TRACE_RETURN( pc, sh4r.new_pc );
678 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
679 sh4r.sh4_state = SH4_STATE_STANDBY;
681 sh4r.sh4_state = SH4_STATE_SLEEP;
683 return FALSE; /* Halt CPU */
687 CHECKDEST( sh4r.spc );
689 sh4r.in_delay_slot = 1;
690 sh4r.pc = sh4r.new_pc;
691 sh4r.new_pc = sh4r.spc;
692 sh4_write_sr( sh4r.ssr );
696 CHECKDEST( sh4r.r[Rn] );
698 sh4r.in_delay_slot = 1;
699 sh4r.pc = sh4r.new_pc;
700 sh4r.new_pc = sh4r.r[Rn];
704 CHECKDEST( sh4r.r[Rn] );
706 sh4r.in_delay_slot = 1;
707 sh4r.pc = sh4r.new_pc;
708 sh4r.new_pc = sh4r.r[Rn];
710 TRACE_CALL( pc, sh4r.new_pc );
713 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
715 CHECKWALIGN32( sh4r.r[Rn] );
716 MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
721 CHECKWALIGN32( sh4r.r[Rn] );
722 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
726 CHECKRALIGN32( sh4r.r[Rm] );
727 MEM_READ_LONG(sh4r.r[Rm], tmp);
728 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
729 (((uint64_t)tmp)<<32);
735 CHECKWALIGN32( sh4r.r[Rm] );
736 MEM_READ_LONG(sh4r.r[Rm], tmp);
741 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
742 (((uint64_t)sh4r.r[Rm])<<32);
747 sh4_write_sr( sh4r.r[Rm] );
751 sh4r.sgr = sh4r.r[Rm];
755 CHECKRALIGN32( sh4r.r[Rm] );
756 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
759 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
761 CHECKWALIGN32( sh4r.r[Rn] );
762 MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
766 CHECKWALIGN32( sh4r.r[Rn] );
767 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
771 CHECKRALIGN32( sh4r.r[Rm] );
772 MEM_READ_LONG(sh4r.r[Rm], tmp);
773 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
774 (uint64_t)((uint32_t)tmp);
778 CHECKRALIGN32( sh4r.r[Rm] );
779 MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
783 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
784 (uint64_t)((uint32_t)(sh4r.r[Rm]));
786 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
787 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
789 CHECKWALIGN32( sh4r.r[Rn] );
790 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
795 CHECKWALIGN32( sh4r.r[Rn] );
796 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
800 CHECKRALIGN32( sh4r.r[Rm] );
801 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
806 CHECKRALIGN32( sh4r.r[Rm] );
807 MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
810 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
813 sh4r.vbr = sh4r.r[Rm];
817 sh4r.r[Rn] = sh4r.sgr;
821 CHECKWALIGN32( sh4r.r[Rn] );
822 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
827 CHECKWALIGN32( sh4r.r[Rn] );
828 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
833 CHECKRALIGN32( sh4r.r[Rm] );
834 MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
839 sh4r.ssr = sh4r.r[Rm];
843 CHECKWALIGN32( sh4r.r[Rn] );
844 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
849 CHECKRALIGN32( sh4r.r[Rm] );
850 MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
855 sh4r.spc = sh4r.r[Rm];
857 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
859 CHECKWALIGN32( sh4r.r[Rn] );
860 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
864 CHECKRALIGN32( sh4r.r[Rm] );
865 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
868 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
869 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
871 CHECKWALIGN32( sh4r.r[Rn] );
872 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
876 CHECKRALIGN32( sh4r.r[Rm] );
877 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
879 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
882 sh4r.fpscr = sh4r.r[Rm];
883 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
885 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
888 CHECKWALIGN32( sh4r.r[Rn] );
889 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
894 CHECKRALIGN32( sh4r.r[Rm] );
895 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
900 sh4r.dbr = sh4r.r[Rm];
902 STC.L Rm_BANK, @-Rn {:
904 CHECKWALIGN32( sh4r.r[Rn] );
905 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
908 LDC.L @Rm+, Rn_BANK {:
910 CHECKRALIGN32( sh4r.r[Rm] );
911 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
916 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
920 sh4r.r[Rn] = sh4_read_sr();
924 sh4r.r[Rn] = sh4r.gbr;
928 sh4r.r[Rn] = sh4r.vbr;
932 sh4r.r[Rn] = sh4r.ssr;
936 sh4r.r[Rn] = sh4r.spc;
940 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
945 if( IS_FPU_DOUBLEPREC() ) {
953 if( IS_FPU_DOUBLEPREC() ) {
962 if( IS_FPU_DOUBLEPREC() ) {
971 if( IS_FPU_DOUBLEPREC() ) {
980 if( IS_FPU_DOUBLEPREC() ) {
981 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
983 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
989 if( IS_FPU_DOUBLEPREC() ) {
990 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
992 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
996 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
997 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
998 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
999 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
1000 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
1001 FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
1003 if( IS_FPU_DOUBLESIZE() )
1008 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
1009 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
1012 if( IS_FPU_DOUBLEPREC() ) {
1013 if( FRn&1 ) { // No, really...
1014 dtmp = (double)FPULi;
1015 FR(FRn) = *(((float *)&dtmp)+1);
1017 DRF(FRn>>1) = (double)FPULi;
1020 FR(FRn) = (float)FPULi;
1025 if( IS_FPU_DOUBLEPREC() ) {
1028 *(((float *)&dtmp)+1) = FR(FRm);
1032 if( dtmp >= MAX_INTF )
1034 else if( dtmp <= MIN_INTF )
1037 FPULi = (int32_t)dtmp;
1040 if( ftmp >= MAX_INTF )
1042 else if( ftmp <= MIN_INTF )
1045 FPULi = (int32_t)ftmp;
1050 if( IS_FPU_DOUBLEPREC() ) {
1058 if( IS_FPU_DOUBLEPREC() ) {
1059 DR(FRn) = fabs(DR(FRn));
1061 FR(FRn) = fabsf(FR(FRn));
1066 if( IS_FPU_DOUBLEPREC() ) {
1067 DR(FRn) = sqrt(DR(FRn));
1069 FR(FRn) = sqrtf(FR(FRn));
1074 if( IS_FPU_DOUBLEPREC() ) {
1082 if( IS_FPU_DOUBLEPREC() ) {
1088 FMAC FR0, FRm, FRn {:
1090 if( IS_FPU_DOUBLEPREC() ) {
1091 DR(FRn) += DR(FRm)*DR(0);
1093 FR(FRn) += FR(FRm)*FR(0);
1098 sh4r.fpscr ^= FPSCR_FR;
1099 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1101 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1104 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1105 DR(FRn) = (double)FPULf;
1110 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1111 FPULf = (float)DR(FRm);
1117 if( !IS_FPU_DOUBLEPREC() ) {
1118 FR(FRn) = 1.0/sqrtf(FR(FRn));
1123 if( !IS_FPU_DOUBLEPREC() ) {
1126 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1127 FR(tmp+1)*FR(tmp2+1) +
1128 FR(tmp+2)*FR(tmp2+2) +
1129 FR(tmp+3)*FR(tmp2+3);
1134 if( !IS_FPU_DOUBLEPREC() ) {
1135 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
1137 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1138 FR(FRn) = sinf(angle);
1139 FR((FRn)+1) = cosf(angle);
1145 if( !IS_FPU_DOUBLEPREC() ) {
1146 sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
1149 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
1150 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1151 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
1152 xf[9]*fv[2] + xf[13]*fv[3];
1153 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
1154 xf[8]*fv[2] + xf[12]*fv[3];
1155 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
1156 xf[11]*fv[2] + xf[15]*fv[3];
1157 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
1158 xf[10]*fv[2] + xf[14]*fv[3];
1166 sh4r.pc = sh4r.new_pc;
1168 sh4r.in_delay_slot = 0;
.