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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 939:6f2302afeb89
prev937:81b0c79d9788
next941:c67574ed4355
author nkeynes
date Sat Jan 03 03:30:26 2009 +0000 (13 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change MMU work-in-progress
* Move SDRAM out into separate sdram.c
* Move all page-table management into mmu.c
* Convert UTLB management to use the new page-tables
* Rip out all calls to mmu_vma_to_phys_* and replace with direct access
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include <setjmp.h>
    23 #include <assert.h>
    24 #include "lxdream.h"
    25 #include "dreamcast.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "eventq.h"
    29 #include "syscall.h"
    30 #include "sh4/intc.h"
    31 #include "sh4/sh4core.h"
    32 #include "sh4/sh4mmio.h"
    33 #include "sh4/sh4stat.h"
    34 #include "sh4/sh4trans.h"
    35 #include "sh4/xltcache.h"
    37 void sh4_init( void );
    38 void sh4_xlat_init( void );
    39 void sh4_reset( void );
    40 void sh4_start( void );
    41 void sh4_stop( void );
    42 void sh4_save_state( FILE *f );
    43 int sh4_load_state( FILE *f );
    45 uint32_t sh4_run_slice( uint32_t );
    46 uint32_t sh4_xlat_run_slice( uint32_t );
    48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    49         sh4_start, sh4_run_slice, sh4_stop,
    50         sh4_save_state, sh4_load_state };
    52 struct sh4_registers sh4r __attribute__((aligned(16)));
    53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    54 int sh4_breakpoint_count = 0;
    56 gboolean sh4_starting = FALSE;
    57 static gboolean sh4_use_translator = FALSE;
    58 static jmp_buf sh4_exit_jmp_buf;
    59 static gboolean sh4_running = FALSE;
    60 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
    62 void sh4_translate_set_enabled( gboolean use )
    63 {
    64     // No-op if the translator was not built
    65 #ifdef SH4_TRANSLATOR
    66     if( use ) {
    67         sh4_translate_init();
    68     }
    69     sh4_use_translator = use;
    70 #endif
    71 }
    73 gboolean sh4_translate_is_enabled()
    74 {
    75     return sh4_use_translator;
    76 }
    78 void sh4_init(void)
    79 {
    80     register_io_regions( mmio_list_sh4mmio );
    81     MMU_init();
    82     TMU_init();
    83     xlat_cache_init();
    84     sh4_reset();
    85 #ifdef ENABLE_SH4STATS
    86     sh4_stats_reset();
    87 #endif
    88 }
    90 void sh4_start(void)
    91 {
    92     sh4_starting = TRUE;
    93 }
    95 void sh4_reset(void)
    96 {
    97     if(	sh4_use_translator ) {
    98         xlat_flush_cache();
    99     }
   101     /* zero everything out, for the sake of having a consistent state. */
   102     memset( &sh4r, 0, sizeof(sh4r) );
   104     /* Resume running if we were halted */
   105     sh4r.sh4_state = SH4_STATE_RUNNING;
   107     sh4r.pc    = 0xA0000000;
   108     sh4r.new_pc= 0xA0000002;
   109     sh4r.vbr   = 0x00000000;
   110     sh4r.fpscr = 0x00040001;
   111     sh4_write_sr(0x700000F0);
   113     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   114     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   116     /* Peripheral modules */
   117     CPG_reset();
   118     INTC_reset();
   119     MMU_reset();
   120     PMM_reset();
   121     TMU_reset();
   122     SCIF_reset();
   124 #ifdef ENABLE_SH4STATS
   125     sh4_stats_reset();
   126 #endif
   127 }
   129 void sh4_stop(void)
   130 {
   131     if(	sh4_use_translator ) {
   132         /* If we were running with the translator, update new_pc and in_delay_slot */
   133         sh4r.new_pc = sh4r.pc+2;
   134         sh4r.in_delay_slot = FALSE;
   135     }
   137 }
   139 /**
   140  * Execute a timeslice using translated code only (ie translate/execute loop)
   141  */
   142 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   143 {
   144     sh4r.slice_cycle = 0;
   146     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   147         sh4_sleep_run_slice(nanosecs);
   148     }
   150     /* Setup for sudden vm exits */
   151     switch( setjmp(sh4_exit_jmp_buf) ) {
   152     case CORE_EXIT_BREAKPOINT:
   153         sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   154         /* fallthrough */
   155     case CORE_EXIT_HALT:
   156         if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   157             TMU_run_slice( sh4r.slice_cycle );
   158             SCIF_run_slice( sh4r.slice_cycle );
   159             PMM_run_slice( sh4r.slice_cycle );
   160             dreamcast_stop();
   161             return sh4r.slice_cycle;
   162         }
   163     case CORE_EXIT_SYSRESET:
   164         dreamcast_reset();
   165         break;
   166     case CORE_EXIT_SLEEP:
   167         sh4_sleep_run_slice(nanosecs);
   168         break;  
   169     case CORE_EXIT_FLUSH_ICACHE:
   170         xlat_flush_cache();
   171         break;
   172     }
   174     sh4_running = TRUE;
   176     /* Execute the core's real slice */
   177 #ifdef SH4_TRANSLATOR
   178     if( sh4_use_translator ) {
   179         sh4_translate_run_slice(nanosecs);
   180     } else {
   181         sh4_emulate_run_slice(nanosecs);
   182     }
   183 #else
   184     sh4_emulate_run_slice(nanosecs);
   185 #endif
   187     /* And finish off the peripherals afterwards */
   189     sh4_running = FALSE;
   190     sh4_starting = FALSE;
   191     sh4r.slice_cycle = nanosecs;
   192     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   193         TMU_run_slice( nanosecs );
   194         SCIF_run_slice( nanosecs );
   195         PMM_run_slice( sh4r.slice_cycle );
   196     }
   197     return nanosecs;   
   198 }
   200 void sh4_core_exit( int exit_code )
   201 {
   202     if( sh4_running ) {
   203 #ifdef SH4_TRANSLATOR
   204         if( sh4_use_translator ) {
   205             sh4_translate_exit_recover();
   206         }
   207 #endif
   208         // longjmp back into sh4_run_slice
   209         sh4_running = FALSE;
   210         longjmp(sh4_exit_jmp_buf, exit_code);
   211     }
   212 }
   214 void sh4_flush_icache()
   215 {
   216 #ifdef SH4_TRANSLATOR
   217     // FIXME: Special case needs to be generalized
   218     if( sh4_use_translator ) {
   219         if( sh4_translate_flush_cache() ) {
   220             longjmp(sh4_exit_jmp_buf, CORE_EXIT_CONTINUE);
   221         }
   222     }
   223 #endif
   224 }
   226 void sh4_save_state( FILE *f )
   227 {
   228     if(	sh4_use_translator ) {
   229         /* If we were running with the translator, update new_pc and in_delay_slot */
   230         sh4r.new_pc = sh4r.pc+2;
   231         sh4r.in_delay_slot = FALSE;
   232     }
   234     fwrite( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
   235     MMU_save_state( f );
   236     CCN_save_state( f );
   237     PMM_save_state( f );
   238     INTC_save_state( f );
   239     TMU_save_state( f );
   240     SCIF_save_state( f );
   241 }
   243 int sh4_load_state( FILE * f )
   244 {
   245     if(	sh4_use_translator ) {
   246         xlat_flush_cache();
   247     }
   248     fread( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
   249     sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
   250     MMU_load_state( f );
   251     CCN_load_state( f );
   252     PMM_load_state( f );
   253     INTC_load_state( f );
   254     TMU_load_state( f );
   255     return SCIF_load_state( f );
   256 }
   258 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   259 {
   260     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   261     sh4_breakpoints[sh4_breakpoint_count].type = type;
   262     if( sh4_use_translator ) {
   263         xlat_invalidate_word( pc );
   264     }
   265     sh4_breakpoint_count++;
   266 }
   268 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   269 {
   270     int i;
   272     for( i=0; i<sh4_breakpoint_count; i++ ) {
   273         if( sh4_breakpoints[i].address == pc && 
   274                 sh4_breakpoints[i].type == type ) {
   275             while( ++i < sh4_breakpoint_count ) {
   276                 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   277                 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   278             }
   279             if( sh4_use_translator ) {
   280                 xlat_invalidate_word( pc );
   281             }
   282             sh4_breakpoint_count--;
   283             return TRUE;
   284         }
   285     }
   286     return FALSE;
   287 }
   289 int sh4_get_breakpoint( uint32_t pc )
   290 {
   291     int i;
   292     for( i=0; i<sh4_breakpoint_count; i++ ) {
   293         if( sh4_breakpoints[i].address == pc )
   294             return sh4_breakpoints[i].type;
   295     }
   296     return 0;
   297 }
   299 void sh4_set_pc( int pc )
   300 {
   301     sh4r.pc = pc;
   302     sh4r.new_pc = pc+2;
   303 }
   306 /******************************* Support methods ***************************/
   308 static void sh4_switch_banks( )
   309 {
   310     uint32_t tmp[8];
   312     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   313     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   314     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   315 }
   317 void FASTCALL sh4_switch_fr_banks()
   318 {
   319     int i;
   320     for( i=0; i<16; i++ ) {
   321         float tmp = sh4r.fr[0][i];
   322         sh4r.fr[0][i] = sh4r.fr[1][i];
   323         sh4r.fr[1][i] = tmp;
   324     }
   325 }
   327 void FASTCALL sh4_write_sr( uint32_t newval )
   328 {
   329     int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
   330     int newbank = (newval&SR_MDRB) == SR_MDRB;
   331     if( oldbank != newbank )
   332         sh4_switch_banks();
   333     sh4r.sr = newval & SR_MASK;
   334     sh4r.t = (newval&SR_T) ? 1 : 0;
   335     sh4r.s = (newval&SR_S) ? 1 : 0;
   336     sh4r.m = (newval&SR_M) ? 1 : 0;
   337     sh4r.q = (newval&SR_Q) ? 1 : 0;
   338     sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
   339     intc_mask_changed();
   340 }
   342 void FASTCALL sh4_write_fpscr( uint32_t newval )
   343 {
   344     if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
   345         sh4_switch_fr_banks();
   346     }
   347     sh4r.fpscr = newval & FPSCR_MASK;
   348     sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
   349 }
   351 uint32_t FASTCALL sh4_read_sr( void )
   352 {
   353     /* synchronize sh4r.sr with the various bitflags */
   354     sh4r.sr &= SR_MQSTMASK;
   355     if( sh4r.t ) sh4r.sr |= SR_T;
   356     if( sh4r.s ) sh4r.sr |= SR_S;
   357     if( sh4r.m ) sh4r.sr |= SR_M;
   358     if( sh4r.q ) sh4r.sr |= SR_Q;
   359     return sh4r.sr;
   360 }
   364 #define RAISE( x, v ) do{			\
   365     if( sh4r.vbr == 0 ) { \
   366         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   367         sh4_core_exit(CORE_EXIT_HALT); return FALSE;	\
   368     } else { \
   369         sh4r.spc = sh4r.pc;	\
   370         sh4r.ssr = sh4_read_sr(); \
   371         sh4r.sgr = sh4r.r[15]; \
   372         MMIO_WRITE(MMU,EXPEVT,x); \
   373         sh4r.pc = sh4r.vbr + v; \
   374         sh4r.new_pc = sh4r.pc + 2; \
   375         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   376         if( sh4r.in_delay_slot ) { \
   377             sh4r.in_delay_slot = 0; \
   378             sh4r.spc -= 2; \
   379         } \
   380     } \
   381     return TRUE; } while(0)
   383 /**
   384  * Raise a general CPU exception for the specified exception code.
   385  * (NOT for TRAPA or TLB exceptions)
   386  */
   387 gboolean FASTCALL sh4_raise_exception( int code )
   388 {
   389     RAISE( code, EXV_EXCEPTION );
   390 }
   392 /**
   393  * Raise a CPU reset exception with the specified exception code.
   394  */
   395 gboolean FASTCALL sh4_raise_reset( int code )
   396 {
   397     // FIXME: reset modules as per "manual reset"
   398     sh4_reset();
   399     MMIO_WRITE(MMU,EXPEVT,code);
   400     sh4r.vbr = 0;
   401     sh4r.pc = 0xA0000000;
   402     sh4r.new_pc = sh4r.pc + 2;
   403     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   404                   &(~SR_FD) );
   405     return TRUE;
   406 }
   408 gboolean FASTCALL sh4_raise_trap( int trap )
   409 {
   410     MMIO_WRITE( MMU, TRA, trap<<2 );
   411     RAISE( EXC_TRAP, EXV_EXCEPTION );
   412 }
   414 gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
   415     if( sh4r.in_delay_slot ) {
   416         return sh4_raise_exception(slot_code);
   417     } else {
   418         return sh4_raise_exception(normal_code);
   419     }
   420 }
   422 gboolean FASTCALL sh4_raise_tlb_exception( int code )
   423 {
   424     RAISE( code, EXV_TLBMISS );
   425 }
   427 void FASTCALL sh4_accept_interrupt( void )
   428 {
   429     uint32_t code = intc_accept_interrupt();
   430     sh4r.ssr = sh4_read_sr();
   431     sh4r.spc = sh4r.pc;
   432     sh4r.sgr = sh4r.r[15];
   433     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   434     MMIO_WRITE( MMU, INTEVT, code );
   435     sh4r.pc = sh4r.vbr + 0x600;
   436     sh4r.new_pc = sh4r.pc + 2;
   437     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   438 }
   440 void FASTCALL signsat48( void )
   441 {
   442     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   443         sh4r.mac = 0xFFFF800000000000LL;
   444     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   445         sh4r.mac = 0x00007FFFFFFFFFFFLL;
   446 }
   448 void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
   449 {
   450     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   451     *fr++ = cosf(angle);
   452     *fr = sinf(angle);
   453 }
   455 /**
   456  * Enter sleep mode (eg by executing a SLEEP instruction).
   457  * Sets sh4_state appropriately and ensures any stopping peripheral modules
   458  * are up to date.
   459  */
   460 void FASTCALL sh4_sleep(void)
   461 {
   462     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   463         sh4r.sh4_state = SH4_STATE_STANDBY;
   464         /* Bring all running peripheral modules up to date, and then halt them. */
   465         TMU_run_slice( sh4r.slice_cycle );
   466         SCIF_run_slice( sh4r.slice_cycle );
   467         PMM_run_slice( sh4r.slice_cycle );
   468     } else {
   469         if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
   470             sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
   471             /* Halt DMAC but other peripherals still running */
   473         } else {
   474             sh4r.sh4_state = SH4_STATE_SLEEP;
   475         }
   476     }
   477     sh4_core_exit( CORE_EXIT_SLEEP );
   478 }
   480 /**
   481  * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
   482  * and restarts any peripheral devices that were stopped.
   483  */
   484 void sh4_wakeup(void)
   485 {
   486     switch( sh4r.sh4_state ) {
   487     case SH4_STATE_STANDBY:
   488         break;
   489     case SH4_STATE_DEEP_SLEEP:
   490         break;
   491     case SH4_STATE_SLEEP:
   492         break;
   493     }
   494     sh4r.sh4_state = SH4_STATE_RUNNING;
   495 }
   497 /**
   498  * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
   499  * Returns when either the SH4 wakes up (interrupt received) or the end of
   500  * the slice is reached. Updates sh4.slice_cycle with the exit time and
   501  * returns the same value.
   502  */
   503 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
   504 {
   505     int sleep_state = sh4r.sh4_state;
   506     assert( sleep_state != SH4_STATE_RUNNING );
   508     while( sh4r.event_pending < nanosecs ) {
   509         sh4r.slice_cycle = sh4r.event_pending;
   510         if( sh4r.event_types & PENDING_EVENT ) {
   511             event_execute();
   512         }
   513         if( sh4r.event_types & PENDING_IRQ ) {
   514             sh4_wakeup();
   515             return sh4r.slice_cycle;
   516         }
   517     }
   518     sh4r.slice_cycle = nanosecs;
   519     return sh4r.slice_cycle;
   520 }
   523 /**
   524  * Compute the matrix tranform of fv given the matrix xf.
   525  * Both fv and xf are word-swapped as per the sh4r.fr banks
   526  */
   527 void FASTCALL sh4_ftrv( float *target )
   528 {
   529     float fv[4] = { target[1], target[0], target[3], target[2] };
   530     target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
   531     sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
   532     target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
   533     sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
   534     target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
   535     sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
   536     target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
   537     sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
   538 }
   540 gboolean sh4_has_page( sh4vma_t vma )
   541 {
   542     sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
   543     return addr != MMU_VMA_ERROR && mem_has_page(addr);
   544 }
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