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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 916:6fbba9e71516
prev890:a9896953e9a1
next921:6c0e9a8f5618
author nkeynes
date Fri Nov 07 07:39:52 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Fix incorrect calculation of width and size (darn missing parentheses)
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     1 /**
     2  * $Id$
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include <assert.h>
    21 #include "dream.h"
    22 #include "eventq.h"
    23 #include "display.h"
    24 #include "mem.h"
    25 #include "asic.h"
    26 #include "clock.h"
    27 #include "pvr2/pvr2.h"
    28 #include "pvr2/pvr2mmio.h"
    29 #include "pvr2/scene.h"
    30 #include "sh4/sh4.h"
    31 #define MMIO_IMPL
    32 #include "pvr2/pvr2mmio.h"
    34 unsigned char *video_base;
    36 #define MAX_RENDER_BUFFERS 4
    38 #define HPOS_PER_FRAME 0
    39 #define HPOS_PER_LINECOUNT 1
    41 static void pvr2_init( void );
    42 static void pvr2_reset( void );
    43 static uint32_t pvr2_run_slice( uint32_t );
    44 static void pvr2_save_state( FILE *f );
    45 static int pvr2_load_state( FILE *f );
    46 static void pvr2_update_raster_posn( uint32_t nanosecs );
    47 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
    48 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
    49 static render_buffer_t pvr2_next_render_buffer( );
    50 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
    51 uint32_t pvr2_get_sync_status();
    53 void pvr2_display_frame( void );
    55 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
    56 static int render_colour_formats[8] = {
    57         COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
    58         COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
    61 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    62         pvr2_run_slice, NULL,
    63         pvr2_save_state, pvr2_load_state };
    66 display_driver_t display_driver = NULL;
    68 struct pvr2_state {
    69     uint32_t frame_count;
    70     uint32_t line_count;
    71     uint32_t line_remainder;
    72     uint32_t cycles_run; /* Cycles already executed prior to main time slice */
    73     uint32_t irq_hpos_line;
    74     uint32_t irq_hpos_line_count;
    75     uint32_t irq_hpos_mode;
    76     uint32_t irq_hpos_time_ns; /* Time within the line */
    77     uint32_t irq_vpos1;
    78     uint32_t irq_vpos2;
    79     uint32_t odd_even_field; /* 1 = odd, 0 = even */
    80     int32_t palette_changed; /* TRUE if palette has changed since last render */
    81     /* timing */
    82     uint32_t dot_clock;
    83     uint32_t total_lines;
    84     uint32_t line_size;
    85     uint32_t line_time_ns;
    86     uint32_t vsync_lines;
    87     uint32_t hsync_width_ns;
    88     uint32_t front_porch_ns;
    89     uint32_t back_porch_ns;
    90     uint32_t retrace_start_line;
    91     uint32_t retrace_end_line;
    92     int32_t interlaced;
    93 } pvr2_state;
    95 static gchar *save_next_render_filename;
    96 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
    97 static uint32_t render_buffer_count = 0;
    98 static render_buffer_t displayed_render_buffer = NULL;
    99 static uint32_t displayed_border_colour = 0;
   101 /**
   102  * Event handler for the hpos callback
   103  */
   104 static void pvr2_hpos_callback( int eventid ) {
   105     asic_event( eventid );
   106     pvr2_update_raster_posn(sh4r.slice_cycle);
   107     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
   108         pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
   109         while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   110             pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   111         }
   112     }
   113     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
   114                                   pvr2_state.irq_hpos_time_ns );
   115 }
   117 /**
   118  * Event handler for the scanline callbacks. Fires the corresponding
   119  * ASIC event, and resets the timer for the next field.
   120  */
   121 static void pvr2_scanline_callback( int eventid ) 
   122 {
   123     asic_event( eventid );
   124     pvr2_update_raster_posn(sh4r.slice_cycle);
   125     if( eventid == EVENT_SCANLINE1 ) {
   126         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
   127     } else {
   128         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
   129     }
   130 }
   132 static void pvr2_gunpos_callback( int eventid ) 
   133 {
   134     pvr2_update_raster_posn(sh4r.slice_cycle);
   135     int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
   136     MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
   137     asic_event( EVENT_MAPLE_DMA );
   138 }
   140 static void pvr2_init( void )
   141 {
   142     int i;
   143     register_io_region( &mmio_region_PVR2 );
   144     register_io_region( &mmio_region_PVR2PAL );
   145     register_io_region( &mmio_region_PVR2TA );
   146     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
   147     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   148     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   149     register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
   150     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
   151     texcache_init();
   152     pvr2_reset();
   153     pvr2_ta_reset();
   154     save_next_render_filename = NULL;
   155     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
   156         render_buffers[i] = NULL;
   157     }
   158     render_buffer_count = 0;
   159     displayed_render_buffer = NULL;
   160     displayed_border_colour = 0;
   161 }
   163 static void pvr2_reset( void )
   164 {
   165     int i;
   166     pvr2_state.line_count = 0;
   167     pvr2_state.line_remainder = 0;
   168     pvr2_state.cycles_run = 0;
   169     pvr2_state.irq_vpos1 = 0;
   170     pvr2_state.irq_vpos2 = 0;
   171     pvr2_state.dot_clock = PVR2_DOT_CLOCK;
   172     pvr2_state.back_porch_ns = 4000;
   173     pvr2_state.palette_changed = FALSE;
   174     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
   175     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
   176     mmio_region_PVR2_write( YUV_ADDR, 0 );
   177     mmio_region_PVR2_write( YUV_CFG, 0 );
   179     pvr2_ta_init();
   180     texcache_flush();
   181     if( display_driver ) {
   182         display_driver->display_blank(0);
   183         for( i=0; i<render_buffer_count; i++ ) {
   184             display_driver->destroy_render_buffer(render_buffers[i]);
   185             render_buffers[i] = NULL;
   186         }
   187         render_buffer_count = 0;
   188     }
   189 }
   191 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
   192 {
   193     struct frame_buffer fbuf;
   195     fbuf.width = buffer->width;
   196     fbuf.height = buffer->height;
   197     fbuf.rowstride = fbuf.width*3;
   198     fbuf.colour_format = COLFMT_BGR888;
   199     fbuf.inverted = buffer->inverted;
   200     fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
   202     display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
   203     write_png_to_stream( f, &fbuf );
   204     g_free( fbuf.data );
   206     fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   207     fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   208     fwrite( &buffer->address, sizeof(buffer->address), 1, f );
   209     fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
   210     int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
   211     fwrite( &flushed, sizeof(flushed), 1, f );
   213 }
   215 render_buffer_t pvr2_load_render_buffer( FILE *f, gboolean *status )
   216 {
   217     frame_buffer_t frame = read_png_from_stream( f );
   218     if( frame == NULL ) {
   219         *status = FALSE;
   220         return NULL;
   221     }
   222     *status = TRUE;
   224     render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
   225     if( buffer != NULL ) {
   226         int32_t flushed;
   227         fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   228         fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   229         fread( &buffer->address, sizeof(buffer->address), 1, f );
   230         fread( &buffer->scale, sizeof(buffer->scale), 1, f );
   231         fread( &flushed, sizeof(flushed), 1, f );
   232         buffer->flushed = (gboolean)flushed;
   233     } else {
   234         fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
   235                 sizeof(buffer->address)+sizeof(buffer->scale)+
   236                 sizeof(int32_t), SEEK_CUR );
   237     }
   238     return buffer;
   239 }
   244 void pvr2_save_render_buffers( FILE *f )
   245 {
   246     int i;
   247     uint32_t has_frontbuffer;
   248     fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
   249     if( displayed_render_buffer != NULL ) {
   250         has_frontbuffer = 1;
   251         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   252         pvr2_save_render_buffer( f, displayed_render_buffer );
   253     } else {
   254         has_frontbuffer = 0;
   255         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   256     }
   258     for( i=0; i<render_buffer_count; i++ ) {
   259         if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
   260             pvr2_save_render_buffer( f, render_buffers[i] );
   261         }
   262     }
   263 }
   265 gboolean pvr2_load_render_buffers( FILE *f )
   266 {
   267     uint32_t count, has_frontbuffer;
   268     gboolean loadok;
   269     int i;
   271     fread( &count, sizeof(count), 1, f );
   272     if( count > MAX_RENDER_BUFFERS ) {
   273         return FALSE;
   274     }
   275     fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   276     for( i=0; i<render_buffer_count; i++ ) {
   277         display_driver->destroy_render_buffer(render_buffers[i]);
   278         render_buffers[i] = NULL;
   279     }
   280     render_buffer_count = 0;
   282     if( has_frontbuffer ) {
   283         displayed_render_buffer = pvr2_load_render_buffer(f, &loadok);
   284         if( displayed_render_buffer != NULL )
   285             display_driver->display_render_buffer( displayed_render_buffer );
   286         else if( !loadok )
   287             return FALSE;
   288         count--;
   289     }
   291     for( i=0; i<count; i++ ) {
   292         pvr2_load_render_buffer( f, &loadok );
   293         if( !loadok )
   294         	return FALSE;
   295     }
   296     return TRUE;
   297 }
   300 static void pvr2_save_state( FILE *f )
   301 {
   302     pvr2_save_render_buffers( f );
   303     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   304     pvr2_ta_save_state( f );
   305     pvr2_yuv_save_state( f );
   306 }
   308 static int pvr2_load_state( FILE *f )
   309 {
   310     if( !pvr2_load_render_buffers(f) )
   311         return 1;
   312     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   313         return 1;
   314     if( pvr2_ta_load_state(f) ) {
   315         return 1;
   316     }
   317     return pvr2_yuv_load_state(f);
   318 }
   320 /**
   321  * Update the current raster position to the given number of nanoseconds,
   322  * relative to the last time slice. (ie the raster will be adjusted forward
   323  * by nanosecs - nanosecs_already_run_this_timeslice)
   324  */
   325 static void pvr2_update_raster_posn( uint32_t nanosecs )
   326 {
   327     uint32_t old_line_count = pvr2_state.line_count;
   328     if( pvr2_state.line_time_ns == 0 ) {
   329         return; /* do nothing */
   330     }
   331     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
   332     pvr2_state.cycles_run = nanosecs;
   333     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
   334         pvr2_state.line_count ++;
   335         pvr2_state.line_remainder -= pvr2_state.line_time_ns;
   336     }
   338     if( pvr2_state.line_count >= pvr2_state.total_lines ) {
   339         pvr2_state.line_count -= pvr2_state.total_lines;
   340         if( pvr2_state.interlaced ) {
   341             pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
   342         }
   343     }
   344     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
   345             (old_line_count < pvr2_state.retrace_end_line ||
   346                     old_line_count > pvr2_state.line_count) ) {
   347         pvr2_state.frame_count++;
   348         pvr2_display_frame();
   349     }
   350 }
   352 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   353 {
   354     pvr2_update_raster_posn( nanosecs );
   355     pvr2_state.cycles_run = 0;
   356     return nanosecs;
   357 }
   359 int pvr2_get_frame_count() 
   360 {
   361     return pvr2_state.frame_count;
   362 }
   364 void pvr2_redraw_display()
   365 {
   366     if( display_driver != NULL ) {
   367         if( displayed_render_buffer == NULL ) {
   368             display_driver->display_blank(displayed_border_colour);
   369         } else {
   370             display_driver->display_render_buffer(displayed_render_buffer);
   371         }
   372     }
   373 }
   375 gboolean pvr2_save_next_scene( const gchar *filename )
   376 {
   377     if( save_next_render_filename != NULL ) {
   378         g_free( save_next_render_filename );
   379     } 
   380     save_next_render_filename = g_strdup(filename);
   381     return TRUE;
   382 }
   386 /**
   387  * Display the next frame, copying the current contents of video ram to
   388  * the window. If the video configuration has changed, first recompute the
   389  * new frame size/depth.
   390  */
   391 void pvr2_display_frame( void )
   392 {
   393     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   394     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
   395     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   397     if( display_driver == NULL ) {
   398         return; /* can't really do anything much */
   399     } else if( !bEnabled ) {
   400         /* Output disabled == black */
   401         displayed_render_buffer = NULL;
   402         displayed_border_colour = 0;
   403         display_driver->display_blank( 0 ); 
   404     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
   405         /* Enabled but blanked - border colour */
   406         displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
   407         displayed_render_buffer = NULL;
   408         display_driver->display_blank( displayed_border_colour );
   409     } else {
   410         /* Real output - determine dimensions etc */
   411         struct frame_buffer fbuf;
   412         uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
   413         int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
   414         int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   416         fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
   417         fbuf.width = (vid_ppl << 2) / colour_formats[fbuf.colour_format].bpp;
   418         fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   419         fbuf.size = (vid_ppl << 2) * fbuf.height;
   420         fbuf.rowstride = (vid_ppl + vid_stride) << 2;
   422         /* Determine the field to display, and deinterlace if possible */
   423         if( pvr2_state.interlaced ) {
   424             if( vid_ppl == vid_stride ) { /* Magic deinterlace */
   425                 fbuf.height = fbuf.height << 1;
   426                 fbuf.rowstride = vid_ppl << 2;
   427                 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   428             } else { 
   429                 /* Just display the field as is, folks. This is slightly tricky -
   430                  * we pick the field based on which frame is about to come through,
   431                  * which may not be the same as the odd_even_field.
   432                  */
   433                 gboolean oddfield = pvr2_state.odd_even_field;
   434                 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
   435                     oddfield = !oddfield;
   436                 }
   437                 if( oddfield ) {
   438                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   439                 } else {
   440                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
   441                 }
   442             }
   443         } else {
   444             fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   445         }
   446         fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
   447         fbuf.inverted = FALSE;
   448         fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
   450         render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
   451         if( rbuf == NULL ) {
   452             rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
   453         }
   454         displayed_render_buffer = rbuf;
   455         if( rbuf != NULL ) {
   456             display_driver->display_render_buffer( rbuf );
   457         }
   458     }
   459 }
   461 /**
   462  * This has to handle every single register individually as they all get masked 
   463  * off differently (and its easier to do it at write time)
   464  */
   465 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   466 {
   467     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   468         MMIO_WRITE( PVR2, reg, val );
   469         return;
   470     }
   472     switch(reg) {
   473     case PVRID:
   474     case PVRVER:
   475     case GUNPOS: /* Read only registers */
   476         break;
   477     case PVRRESET:
   478         val &= 0x00000007; /* Do stuff? */
   479         MMIO_WRITE( PVR2, reg, val );
   480         break;
   481     case RENDER_START: /* Don't really care what value */
   482         if( save_next_render_filename != NULL ) {
   483             if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
   484                 INFO( "Saved scene to %s", save_next_render_filename);
   485             }
   486             g_free( save_next_render_filename );
   487             save_next_render_filename = NULL;
   488         }
   489         pvr2_scene_read();
   490         render_buffer_t buffer = pvr2_next_render_buffer();
   491         if( buffer != NULL ) {
   492             pvr2_scene_render( buffer );
   493             pvr2_finish_render_buffer( buffer );
   494             if( buffer->address < PVR2_RAM_BASE ) {
   495                 // Flush immediately - optimize this later. Otherwise this gets
   496                 // complicated very quickly trying to second-guess how it's
   497                 // going to be used as a texture.
   498                 pvr2_render_buffer_copy_to_sh4( buffer );
   499             }
   500         }
   501         asic_event( EVENT_PVR_RENDER_DONE );
   502         break;
   503     case RENDER_POLYBASE:
   504         MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   505         break;
   506     case RENDER_TSPCFG:
   507         MMIO_WRITE( PVR2, reg, val&0x00010101 );
   508         break;
   509     case DISP_BORDER:
   510         MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   511         break;
   512     case DISP_MODE:
   513         MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   514         break;
   515     case RENDER_MODE:
   516         MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   517         break;
   518     case RENDER_SIZE:
   519         MMIO_WRITE( PVR2, reg, val&0x000001FF );
   520         break;
   521     case DISP_ADDR1:
   522         val &= 0x00FFFFFC;
   523         MMIO_WRITE( PVR2, reg, val );
   524         pvr2_update_raster_posn(sh4r.slice_cycle);
   525         break;
   526     case DISP_ADDR2:
   527         MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   528         pvr2_update_raster_posn(sh4r.slice_cycle);
   529         break;
   530     case DISP_SIZE:
   531         MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   532         break;
   533     case RENDER_ADDR1:
   534     case RENDER_ADDR2:
   535         MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   536         break;
   537     case RENDER_HCLIP:
   538         MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   539         break;
   540     case RENDER_VCLIP:
   541         MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   542         break;
   543     case DISP_HPOSIRQ:
   544         MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   545         pvr2_state.irq_hpos_line = val & 0x03FF;
   546         pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
   547         pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
   548         switch( pvr2_state.irq_hpos_mode ) {
   549         case 3: /* Reserved - treat as 0 */
   550         case 0: /* Once per frame at specified line */
   551             pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
   552             break;
   553         case 2: /* Once per line - as per-line-count */
   554             pvr2_state.irq_hpos_line = 1;
   555             pvr2_state.irq_hpos_mode = 1;
   556         case 1: /* Once per N lines */
   557             pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
   558             pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
   559             pvr2_state.irq_hpos_line_count;
   560             while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   561                 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   562             }
   563             pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
   564         }
   565         pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
   566                                       pvr2_state.irq_hpos_time_ns );
   567         break;
   568         case DISP_VPOSIRQ:
   569             val = val & 0x03FF03FF;
   570             pvr2_state.irq_vpos1 = (val >> 16);
   571             pvr2_state.irq_vpos2 = val & 0x03FF;
   572             pvr2_update_raster_posn(sh4r.slice_cycle);
   573             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   574             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   575             MMIO_WRITE( PVR2, reg, val );
   576             break;
   577         case RENDER_NEARCLIP:
   578             MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   579             break;
   580         case RENDER_SHADOW:
   581             MMIO_WRITE( PVR2, reg, val&0x000001FF );
   582             break;
   583         case RENDER_OBJCFG:
   584             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   585             break;
   586         case RENDER_TSPCLIP:
   587             MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   588             break;
   589         case RENDER_FARCLIP:
   590             MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   591             break;
   592         case RENDER_BGPLANE:
   593             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   594             break;
   595         case RENDER_ISPCFG:
   596             MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   597             break;
   598         case VRAM_CFG1:
   599             MMIO_WRITE( PVR2, reg, val&0x000000FF );
   600             break;
   601         case VRAM_CFG2:
   602             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   603             break;
   604         case VRAM_CFG3:
   605             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   606             break;
   607         case RENDER_FOGTBLCOL:
   608         case RENDER_FOGVRTCOL:
   609             MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   610             break;
   611         case RENDER_FOGCOEFF:
   612             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   613             break;
   614         case RENDER_CLAMPHI:
   615         case RENDER_CLAMPLO:
   616             MMIO_WRITE( PVR2, reg, val );
   617             break;
   618         case RENDER_TEXSIZE:
   619             MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   620             break;
   621         case RENDER_PALETTE:
   622             MMIO_WRITE( PVR2, reg, val&0x00000003 );
   623             break;
   624         case RENDER_ALPHA_REF:
   625             MMIO_WRITE( PVR2, reg, val&0x000000FF );
   626             break;
   627             /********** CRTC registers *************/
   628         case DISP_HBORDER:
   629         case DISP_VBORDER:
   630             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   631             break;
   632         case DISP_TOTAL:
   633             val = val & 0x03FF03FF;
   634             MMIO_WRITE( PVR2, reg, val );
   635             pvr2_update_raster_posn(sh4r.slice_cycle);
   636             pvr2_state.total_lines = (val >> 16) + 1;
   637             pvr2_state.line_size = (val & 0x03FF) + 1;
   638             pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
   639             pvr2_state.retrace_end_line = 0x2A;
   640             pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
   641             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   642             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   643             pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
   644                                           pvr2_state.irq_hpos_time_ns );
   645             break;
   646         case DISP_SYNCCFG:
   647             MMIO_WRITE( PVR2, reg, val&0x000003FF );
   648             pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
   649             break;
   650         case DISP_SYNCTIME:
   651             pvr2_state.vsync_lines = (val >> 8) & 0x0F;
   652             pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
   653             MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   654             break;
   655         case DISP_CFG2:
   656             MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   657             break;
   658         case DISP_HPOS:
   659             val = val & 0x03FF;
   660             pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
   661             MMIO_WRITE( PVR2, reg, val );
   662             break;
   663         case DISP_VPOS:
   664             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   665             break;
   667             /*********** Tile accelerator registers ***********/
   668         case TA_POLYPOS:
   669         case TA_LISTPOS:
   670             /* Readonly registers */
   671             break;
   672         case TA_TILEBASE:
   673         case TA_LISTEND:
   674         case TA_LISTBASE:
   675             MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   676             break;
   677         case RENDER_TILEBASE:
   678         case TA_POLYBASE:
   679         case TA_POLYEND:
   680             MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   681             break;
   682         case TA_TILESIZE:
   683             MMIO_WRITE( PVR2, reg, val&0x000F003F );
   684             break;
   685         case TA_TILECFG:
   686             MMIO_WRITE( PVR2, reg, val&0x00133333 );
   687             break;
   688         case TA_INIT:
   689             if( val & 0x80000000 )
   690                 pvr2_ta_init();
   691             break;
   692         case TA_REINIT:
   693             break;
   694             /**************** Scaler registers? ****************/
   695         case RENDER_SCALER:
   696             MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   697             break;
   699         case YUV_ADDR:
   700             val = val & 0x00FFFFF8;
   701             MMIO_WRITE( PVR2, reg, val );
   702             pvr2_yuv_init( val );
   703             break;
   704         case YUV_CFG:
   705             MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   706             pvr2_yuv_set_config(val);
   707             break;
   709             /**************** Unknowns ***************/
   710         case PVRUNK1:
   711             MMIO_WRITE( PVR2, reg, val&0x000007FF );
   712             break;
   713         case PVRUNK2:
   714             MMIO_WRITE( PVR2, reg, val&0x00000007 );
   715             break;
   716         case PVRUNK3:
   717             MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   718             break;
   719         case PVRUNK5:
   720             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   721             break;
   722         case PVRUNK7:
   723             MMIO_WRITE( PVR2, reg, val&0x00000001 );
   724             break;
   725         case PVRUNK8:
   726             MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
   727             break;
   728     }
   729 }
   731 /**
   732  * Calculate the current read value of the syncstat register, using
   733  * the current SH4 clock time as an offset from the last timeslice.
   734  * The register reads (LSB to MSB) as:
   735  *     0..9  Current scan line
   736  *     10    Odd/even field (1 = odd, 0 = even)
   737  *     11    Display active (including border and overscan)
   738  *     12    Horizontal sync off
   739  *     13    Vertical sync off
   740  * Note this method is probably incorrect for anything other than straight
   741  * interlaced PAL/NTSC, and needs further testing. 
   742  */
   743 uint32_t pvr2_get_sync_status()
   744 {
   745     pvr2_update_raster_posn(sh4r.slice_cycle);
   746     uint32_t result = pvr2_state.line_count;
   748     if( pvr2_state.odd_even_field ) {
   749         result |= 0x0400;
   750     }
   751     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
   752         if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
   753             result |= 0x1000; /* !HSYNC */
   754         }
   755         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   756             if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
   757                 result |= 0x2800; /* Display active */
   758             } else {
   759                 result |= 0x2000; /* Front porch */
   760             }
   761         }
   762     } else {
   763         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   764             if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
   765                 result |= 0x3800; /* Display active */
   766             } else {
   767                 result |= 0x3000;
   768             }
   769         } else {
   770             result |= 0x1000; /* Back porch */
   771         }
   772     }
   773     return result;
   774 }
   776 /**
   777  * Schedule a "scanline" event. This actually goes off at
   778  * 2 * line in even fields and 2 * line + 1 in odd fields.
   779  * Otherwise this behaves as per pvr2_schedule_line_event().
   780  * The raster position should be updated before calling this
   781  * method.
   782  * @param eventid Event to fire at the specified time
   783  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
   784  *  displays). 
   785  * @param hpos_ns Nanoseconds into the line at which to fire.
   786  */
   787 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
   788 {
   789     uint32_t field = pvr2_state.odd_even_field;
   790     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
   791         field = !field;
   792     }
   793     if( hpos_ns > pvr2_state.line_time_ns ) {
   794         hpos_ns = pvr2_state.line_time_ns;
   795     }
   797     line <<= 1;
   798     if( field ) {
   799         line += 1;
   800     }
   802     if( line < pvr2_state.total_lines ) {
   803         uint32_t lines;
   804         uint32_t time;
   805         if( line <= pvr2_state.line_count ) {
   806             lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
   807         } else {
   808             lines = (line - pvr2_state.line_count);
   809         }
   810         if( lines <= minimum_lines ) {
   811             lines += pvr2_state.total_lines;
   812         }
   813         time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
   814         event_schedule( eventid, time );
   815     } else {
   816         event_cancel( eventid );
   817     }
   818 }
   820 void pvr2_queue_gun_event( int xpos, int ypos )
   821 {
   822     pvr2_update_raster_posn(sh4r.slice_cycle);
   823     pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,  
   824             (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns ); 
   825 }
   827 MMIO_REGION_READ_FN( PVR2, reg )
   828 {
   829     switch( reg ) {
   830     case DISP_SYNCSTAT:
   831         return pvr2_get_sync_status();
   832     default:
   833         return MMIO_READ( PVR2, reg );
   834     }
   835 }
   837 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
   838 {
   839     MMIO_WRITE( PVR2PAL, reg, val );
   840     pvr2_state.palette_changed = TRUE;
   841 }
   843 void pvr2_check_palette_changed()
   844 {
   845     if( pvr2_state.palette_changed ) {
   846         texcache_invalidate_palette();
   847         pvr2_state.palette_changed = FALSE;
   848     }
   849 }
   851 MMIO_REGION_READ_DEFFN( PVR2PAL );
   853 void pvr2_set_base_address( uint32_t base ) 
   854 {
   855     mmio_region_PVR2_write( DISP_ADDR1, base );
   856 }
   861 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   862 {
   863     return 0xFFFFFFFF;
   864 }
   866 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   867 {
   868     pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
   869 }
   871 render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
   872 {
   873     if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
   874         render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
   875         buffer->address = addr;
   876         return buffer;
   877     }
   878     return NULL;
   879 }
   881 void pvr2_destroy_render_buffer( render_buffer_t buffer )
   882 {
   883     if( !buffer->flushed )
   884         pvr2_render_buffer_copy_to_sh4( buffer );
   885      display_driver->destroy_render_buffer( buffer );
   886 }
   888 void pvr2_finish_render_buffer( render_buffer_t buffer )
   889 {
   890     display_driver->finish_render( buffer );
   891 }
   893 /**
   894  * Find the render buffer corresponding to the requested output frame
   895  * (does not consider texture renders). 
   896  * @return the render_buffer if found, or null if no such buffer.
   897  *
   898  * Note: Currently does not consider "partial matches", ie partial
   899  * frame overlap - it probably needs to do this.
   900  */
   901 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
   902 {
   903     int i;
   904     for( i=0; i<render_buffer_count; i++ ) {
   905         if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
   906             return render_buffers[i];
   907         }
   908     }
   909     return NULL;
   910 }
   912 /**
   913  * Allocate a render buffer with the requested parameters.
   914  * The order of preference is:
   915  *   1. An existing buffer with the same address. (not flushed unless the new
   916  * size is smaller than the old one).
   917  *   2. An existing buffer with the same size chosen by LRU order. Old buffer
   918  *       is flushed to vram.
   919  *   3. A new buffer if one can be created.
   920  *   4. The current display buff
   921  * Note: The current display field(s) will never be overwritten except as a last
   922  * resort.
   923  */
   924 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
   925 {
   926     int i;
   927     render_buffer_t result = NULL;
   929     /* Check existing buffers for an available buffer */
   930     for( i=0; i<render_buffer_count; i++ ) {
   931         if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
   932             /* needs to be the right dimensions */
   933             if( render_buffers[i]->address == render_addr ) {
   934                 if( displayed_render_buffer == render_buffers[i] ) {
   935                     /* Same address, but we can't use it because the
   936                      * display has it. Mark it as unaddressed for later.
   937                      */
   938                     render_buffers[i]->address = -1;
   939                 } else {
   940                     /* perfect */
   941                     result = render_buffers[i];
   942                     break;
   943                 }
   944             } else if( render_buffers[i]->address == -1 && result == NULL && 
   945                     displayed_render_buffer != render_buffers[i] ) {
   946                 result = render_buffers[i];
   947             }
   949         } else if( render_buffers[i]->address == render_addr ) {
   950             /* right address, wrong size - if it's larger, flush it, otherwise 
   951              * nuke it quietly */
   952             if( render_buffers[i]->width * render_buffers[i]->height >
   953             width*height ) {
   954                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
   955             }
   956             render_buffers[i]->address = -1;
   957         }
   958     }
   960     /* Nothing available - make one */
   961     if( result == NULL ) {
   962         if( render_buffer_count == MAX_RENDER_BUFFERS ) {
   963             /* maximum buffers reached - need to throw one away */
   964             uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   965             uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
   966             for( i=0; i<render_buffer_count; i++ ) {
   967                 if( render_buffers[i]->address != field1_addr &&
   968                         render_buffers[i]->address != field2_addr &&
   969                         render_buffers[i] != displayed_render_buffer ) {
   970                     /* Never throw away the current "front buffer(s)" */
   971                     result = render_buffers[i];
   972                     if( !result->flushed && result->address != -1 ) {
   973                         pvr2_render_buffer_copy_to_sh4( result );
   974                     }
   975                     if( result->width != width || result->height != height ) {
   976                         display_driver->destroy_render_buffer(render_buffers[i]);
   977                         result = display_driver->create_render_buffer(width,height,0);
   978                         render_buffers[i] = result;
   979                     }
   980                     break;
   981                 }
   982             }
   983         } else {
   984             result = display_driver->create_render_buffer(width,height,0);
   985             if( result != NULL ) { 
   986                 render_buffers[render_buffer_count++] = result;
   987             }
   988         }
   989     }
   991     if( result != NULL ) {
   992         result->address = render_addr;
   993     }
   994     return result;
   995 }
   997 /**
   998  * Allocate a render buffer based on the current rendering settings
   999  */
  1000 render_buffer_t pvr2_next_render_buffer()
  1002     render_buffer_t result = NULL;
  1003     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
  1004     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
  1005     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
  1006     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
  1008     int width = pvr2_scene_buffer_width();
  1009     int height = pvr2_scene_buffer_height();
  1010     int colour_format = render_colour_formats[render_mode&0x07];
  1012     if( render_addr & 0x01000000 ) { /* vram64 */
  1013         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
  1014     } else { /* vram32 */
  1015         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
  1017     result = pvr2_alloc_render_buffer( render_addr, width, height );
  1019     /* Setup the buffer */
  1020     if( result != NULL ) {
  1021         result->rowstride = render_stride;
  1022         result->colour_format = colour_format;
  1023         result->scale = render_scale;
  1024         result->size = width * height * colour_formats[colour_format].bpp;
  1025         result->flushed = FALSE;
  1026         result->inverted = TRUE; // render buffers are inverted normally
  1028     return result;
  1031 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
  1033     render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
  1034     if( result != NULL ) {
  1035         int bpp = colour_formats[frame->colour_format].bpp;
  1036         result->rowstride = frame->rowstride;
  1037         result->colour_format = frame->colour_format;
  1038         result->scale = 0x400;
  1039         result->size = frame->width * frame->height * bpp;
  1040         result->flushed = TRUE;
  1041         result->inverted = frame->inverted;
  1042         display_driver->load_frame_buffer( frame, result );
  1044     return result;
  1048 /**
  1049  * Invalidate any caching on the supplied address. Specifically, if it falls
  1050  * within any of the render buffers, flush the buffer back to PVR2 ram.
  1051  */
  1052 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
  1054     int i;
  1055     address = address & 0x1FFFFFFF;
  1056     for( i=0; i<render_buffer_count; i++ ) {
  1057         uint32_t bufaddr = render_buffers[i]->address;
  1058         if( bufaddr != -1 && bufaddr <= address && 
  1059                 (bufaddr + render_buffers[i]->size) > address ) {
  1060             if( !render_buffers[i]->flushed ) {
  1061                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
  1063             if( isWrite ) {
  1064                 render_buffers[i]->address = -1; /* Invalid */
  1066             return TRUE; /* should never have overlapping buffers */
  1069     return FALSE;
.