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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 416:714df603c869
prev409:549e00835448
next417:bd927df302a9
author nkeynes
date Wed Oct 03 12:19:03 2007 +0000 (15 years ago)
permissions -rw-r--r--
last change Remove INC %esi (and esi in general), replace with load immediates (faster)
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     1 /**
     2  * $Id: sh4x86.c,v 1.17 2007-10-03 12:19:03 nkeynes Exp $
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    22 #include <math.h>
    24 #ifndef NDEBUG
    25 #define DEBUG_JUMPS 1
    26 #endif
    28 #include "sh4/sh4core.h"
    29 #include "sh4/sh4trans.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/x86op.h"
    32 #include "clock.h"
    34 #define DEFAULT_BACKPATCH_SIZE 4096
    36 /** 
    37  * Struct to manage internal translation state. This state is not saved -
    38  * it is only valid between calls to sh4_translate_begin_block() and
    39  * sh4_translate_end_block()
    40  */
    41 struct sh4_x86_state {
    42     gboolean in_delay_slot;
    43     gboolean priv_checked; /* true if we've already checked the cpu mode. */
    44     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    45     gboolean branch_taken; /* true if we branched unconditionally */
    46     uint32_t block_start_pc;
    48     /* Allocated memory for the (block-wide) back-patch list */
    49     uint32_t **backpatch_list;
    50     uint32_t backpatch_posn;
    51     uint32_t backpatch_size;
    52 };
    54 #define EXIT_DATA_ADDR_READ 0
    55 #define EXIT_DATA_ADDR_WRITE 7
    56 #define EXIT_ILLEGAL 14
    57 #define EXIT_SLOT_ILLEGAL 21
    58 #define EXIT_FPU_DISABLED 28
    59 #define EXIT_SLOT_FPU_DISABLED 35
    61 static struct sh4_x86_state sh4_x86;
    63 static uint32_t max_int = 0x7FFFFFFF;
    64 static uint32_t min_int = 0x80000000;
    65 static uint32_t save_fcw; /* save value for fpu control word */
    66 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
    68 void sh4_x86_init()
    69 {
    70     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
    71     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
    72 }
    75 static void sh4_x86_add_backpatch( uint8_t *ptr )
    76 {
    77     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
    78 	sh4_x86.backpatch_size <<= 1;
    79 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
    80 	assert( sh4_x86.backpatch_list != NULL );
    81     }
    82     sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
    83 }
    85 static void sh4_x86_do_backpatch( uint8_t *reloc_base )
    86 {
    87     unsigned int i;
    88     for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
    89 	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
    90     }
    91 }
    93 /**
    94  * Emit an instruction to load an SH4 reg into a real register
    95  */
    96 static inline void load_reg( int x86reg, int sh4reg ) 
    97 {
    98     /* mov [bp+n], reg */
    99     OP(0x8B);
   100     OP(0x45 + (x86reg<<3));
   101     OP(REG_OFFSET(r[sh4reg]));
   102 }
   104 static inline void load_reg16s( int x86reg, int sh4reg )
   105 {
   106     OP(0x0F);
   107     OP(0xBF);
   108     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   109 }
   111 static inline void load_reg16u( int x86reg, int sh4reg )
   112 {
   113     OP(0x0F);
   114     OP(0xB7);
   115     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   117 }
   119 #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
   120 #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
   121 /**
   122  * Emit an instruction to load an immediate value into a register
   123  */
   124 static inline void load_imm32( int x86reg, uint32_t value ) {
   125     /* mov #value, reg */
   126     OP(0xB8 + x86reg);
   127     OP32(value);
   128 }
   130 /**
   131  * Emit an instruction to store an SH4 reg (RN)
   132  */
   133 void static inline store_reg( int x86reg, int sh4reg ) {
   134     /* mov reg, [bp+n] */
   135     OP(0x89);
   136     OP(0x45 + (x86reg<<3));
   137     OP(REG_OFFSET(r[sh4reg]));
   138 }
   140 #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
   142 /**
   143  * Load an FR register (single-precision floating point) into an integer x86
   144  * register (eg for register-to-register moves)
   145  */
   146 void static inline load_fr( int bankreg, int x86reg, int frm )
   147 {
   148     OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
   149 }
   151 /**
   152  * Store an FR register (single-precision floating point) into an integer x86
   153  * register (eg for register-to-register moves)
   154  */
   155 void static inline store_fr( int bankreg, int x86reg, int frn )
   156 {
   157     OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
   158 }
   161 /**
   162  * Load a pointer to the back fp back into the specified x86 register. The
   163  * bankreg must have been previously loaded with FPSCR.
   164  * NB: 12 bytes
   165  */
   166 static inline void load_xf_bank( int bankreg )
   167 {
   168     NOT_r32( bankreg );
   169     SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
   170     AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
   171     OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
   172 }
   174 /**
   175  * Update the fr_bank pointer based on the current fpscr value.
   176  */
   177 static inline void update_fr_bank( int fpscrreg )
   178 {
   179     SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
   180     AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
   181     OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
   182     store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
   183 }
   184 /**
   185  * Push FPUL (as a 32-bit float) onto the FPU stack
   186  */
   187 static inline void push_fpul( )
   188 {
   189     OP(0xD9); OP(0x45); OP(R_FPUL);
   190 }
   192 /**
   193  * Pop FPUL (as a 32-bit float) from the FPU stack
   194  */
   195 static inline void pop_fpul( )
   196 {
   197     OP(0xD9); OP(0x5D); OP(R_FPUL);
   198 }
   200 /**
   201  * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
   202  * with the location of the current fp bank.
   203  */
   204 static inline void push_fr( int bankreg, int frm ) 
   205 {
   206     OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
   207 }
   209 /**
   210  * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
   211  * with bankreg previously loaded with the location of the current fp bank.
   212  */
   213 static inline void pop_fr( int bankreg, int frm )
   214 {
   215     OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
   216 }
   218 /**
   219  * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
   220  * with the location of the current fp bank.
   221  */
   222 static inline void push_dr( int bankreg, int frm )
   223 {
   224     OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
   225 }
   227 static inline void pop_dr( int bankreg, int frm )
   228 {
   229     OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
   230 }
   232 /**
   233  * Note: clobbers EAX to make the indirect call - this isn't usually
   234  * a problem since the callee will usually clobber it anyway.
   235  */
   236 static inline void call_func0( void *ptr )
   237 {
   238     load_imm32(R_EAX, (uint32_t)ptr);
   239     CALL_r32(R_EAX);
   240 }
   242 static inline void call_func1( void *ptr, int arg1 )
   243 {
   244     PUSH_r32(arg1);
   245     call_func0(ptr);
   246     ADD_imm8s_r32( 4, R_ESP );
   247 }
   249 static inline void call_func2( void *ptr, int arg1, int arg2 )
   250 {
   251     PUSH_r32(arg2);
   252     PUSH_r32(arg1);
   253     call_func0(ptr);
   254     ADD_imm8s_r32( 8, R_ESP );
   255 }
   257 /**
   258  * Write a double (64-bit) value into memory, with the first word in arg2a, and
   259  * the second in arg2b
   260  * NB: 30 bytes
   261  */
   262 static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
   263 {
   264     ADD_imm8s_r32( 4, addr );
   265     PUSH_r32(arg2b);
   266     PUSH_r32(addr);
   267     ADD_imm8s_r32( -4, addr );
   268     PUSH_r32(arg2a);
   269     PUSH_r32(addr);
   270     call_func0(sh4_write_long);
   271     ADD_imm8s_r32( 8, R_ESP );
   272     call_func0(sh4_write_long);
   273     ADD_imm8s_r32( 8, R_ESP );
   274 }
   276 /**
   277  * Read a double (64-bit) value from memory, writing the first word into arg2a
   278  * and the second into arg2b. The addr must not be in EAX
   279  * NB: 27 bytes
   280  */
   281 static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
   282 {
   283     PUSH_r32(addr);
   284     call_func0(sh4_read_long);
   285     POP_r32(addr);
   286     PUSH_r32(R_EAX);
   287     ADD_imm8s_r32( 4, addr );
   288     PUSH_r32(addr);
   289     call_func0(sh4_read_long);
   290     ADD_imm8s_r32( 4, R_ESP );
   291     MOV_r32_r32( R_EAX, arg2b );
   292     POP_r32(arg2a);
   293 }
   295 /* Exception checks - Note that all exception checks will clobber EAX */
   296 #define precheck() load_imm32(R_EDX, (pc-sh4_x86.block_start_pc-(sh4_x86.in_delay_slot?2:0))>>1)
   298 #define check_priv( ) \
   299     if( !sh4_x86.priv_checked ) { \
   300 	sh4_x86.priv_checked = TRUE;\
   301 	precheck();\
   302 	load_spreg( R_EAX, R_SR );\
   303 	AND_imm32_r32( SR_MD, R_EAX );\
   304 	if( sh4_x86.in_delay_slot ) {\
   305 	    JE_exit( EXIT_SLOT_ILLEGAL );\
   306 	} else {\
   307 	    JE_exit( EXIT_ILLEGAL );\
   308 	}\
   309     }\
   312 static void check_priv_no_precheck()
   313 {
   314     if( !sh4_x86.priv_checked ) {
   315 	sh4_x86.priv_checked = TRUE;
   316 	load_spreg( R_EAX, R_SR );
   317 	AND_imm32_r32( SR_MD, R_EAX );
   318 	if( sh4_x86.in_delay_slot ) {
   319 	    JE_exit( EXIT_SLOT_ILLEGAL );
   320 	} else {
   321 	    JE_exit( EXIT_ILLEGAL );
   322 	}
   323     }
   324 }
   326 #define check_fpuen( ) \
   327     if( !sh4_x86.fpuen_checked ) {\
   328 	sh4_x86.fpuen_checked = TRUE;\
   329 	precheck();\
   330 	load_spreg( R_EAX, R_SR );\
   331 	AND_imm32_r32( SR_FD, R_EAX );\
   332 	if( sh4_x86.in_delay_slot ) {\
   333 	    JNE_exit(EXIT_SLOT_FPU_DISABLED);\
   334 	} else {\
   335 	    JNE_exit(EXIT_FPU_DISABLED);\
   336 	}\
   337     }
   339 static void check_fpuen_no_precheck()
   340 {
   341     if( !sh4_x86.fpuen_checked ) {
   342 	sh4_x86.fpuen_checked = TRUE;
   343 	load_spreg( R_EAX, R_SR );
   344 	AND_imm32_r32( SR_FD, R_EAX );
   345 	if( sh4_x86.in_delay_slot ) {
   346 	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
   347 	} else {
   348 	    JNE_exit(EXIT_FPU_DISABLED);
   349 	}
   350     }
   352 }
   354 static void check_ralign16( int x86reg )
   355 {
   356     TEST_imm32_r32( 0x00000001, x86reg );
   357     JNE_exit(EXIT_DATA_ADDR_READ);
   358 }
   360 static void check_walign16( int x86reg )
   361 {
   362     TEST_imm32_r32( 0x00000001, x86reg );
   363     JNE_exit(EXIT_DATA_ADDR_WRITE);
   364 }
   366 static void check_ralign32( int x86reg )
   367 {
   368     TEST_imm32_r32( 0x00000003, x86reg );
   369     JNE_exit(EXIT_DATA_ADDR_READ);
   370 }
   371 static void check_walign32( int x86reg )
   372 {
   373     TEST_imm32_r32( 0x00000003, x86reg );
   374     JNE_exit(EXIT_DATA_ADDR_WRITE);
   375 }
   377 #define UNDEF()
   378 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
   379 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
   380 #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
   381 #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
   382 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
   383 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
   384 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
   386 #define SLOTILLEGAL() precheck(); JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
   390 /**
   391  * Emit the 'start of block' assembly. Sets up the stack frame and save
   392  * SI/DI as required
   393  */
   394 void sh4_translate_begin_block( sh4addr_t pc ) 
   395 {
   396     PUSH_r32(R_EBP);
   397     /* mov &sh4r, ebp */
   398     load_imm32( R_EBP, (uint32_t)&sh4r );
   400     sh4_x86.in_delay_slot = FALSE;
   401     sh4_x86.priv_checked = FALSE;
   402     sh4_x86.fpuen_checked = FALSE;
   403     sh4_x86.branch_taken = FALSE;
   404     sh4_x86.backpatch_posn = 0;
   405     sh4_x86.block_start_pc = pc;
   406 }
   408 /**
   409  * Exit the block to an absolute PC
   410  * Bytes: 29
   411  */
   412 void exit_block( sh4addr_t pc, sh4addr_t endpc )
   413 {
   414     load_imm32( R_ECX, pc );                            // 5
   415     store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
   416     MOV_moff32_EAX( (uint32_t)xlat_get_lut_entry(pc) ); // 5
   417     AND_imm8s_r32( 0xFC, R_EAX ); // 3
   418     load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   419     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   420     POP_r32(R_EBP);
   421     RET();
   422 }
   424 /**
   425  * Exit the block with sh4r.pc already written
   426  * Bytes: 15
   427  */
   428 void exit_block_pcset( pc )
   429 {
   430     XOR_r32_r32( R_EAX, R_EAX );                       // 2
   431     load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   432     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
   433     POP_r32(R_EBP);
   434     RET();
   435 }
   437 /**
   438  * Write the block trailer (exception handling block)
   439  */
   440 void sh4_translate_end_block( sh4addr_t pc ) {
   441     if( sh4_x86.branch_taken == FALSE ) {
   442 	// Didn't exit unconditionally already, so write the termination here
   443 	exit_block( pc, pc );
   444     }
   445     if( sh4_x86.backpatch_posn != 0 ) {
   446 	uint8_t *end_ptr = xlat_output;
   447 	// Exception termination. Jump block for various exception codes:
   448 	PUSH_imm32( EXC_DATA_ADDR_READ );
   449 	JMP_rel8( 33, target1 );
   450 	PUSH_imm32( EXC_DATA_ADDR_WRITE );
   451 	JMP_rel8( 26, target2 );
   452 	PUSH_imm32( EXC_ILLEGAL );
   453 	JMP_rel8( 19, target3 );
   454 	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
   455 	JMP_rel8( 12, target4 );
   456 	PUSH_imm32( EXC_FPU_DISABLED ); 
   457 	JMP_rel8( 5, target5 );
   458 	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
   459 	// target
   460 	JMP_TARGET(target1);
   461 	JMP_TARGET(target2);
   462 	JMP_TARGET(target3);
   463 	JMP_TARGET(target4);
   464 	JMP_TARGET(target5);
   465 	load_spreg( R_ECX, REG_OFFSET(pc) );
   466 	ADD_r32_r32( R_EDX, R_ECX );
   467 	ADD_r32_r32( R_EDX, R_ECX );
   468 	store_spreg( R_ECX, REG_OFFSET(pc) );
   469 	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
   470 	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   471 	MUL_r32( R_EDX );
   472 	ADD_r32_r32( R_EAX, R_ECX );
   473 	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   475 	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
   476 	CALL_r32( R_EAX ); // 2
   477 	ADD_imm8s_r32( 4, R_ESP );
   478 	XOR_r32_r32( R_EAX, R_EAX );
   479 	POP_r32(R_EBP);
   480 	RET();
   482 	sh4_x86_do_backpatch( end_ptr );
   483     }
   485 }
   488 extern uint16_t *sh4_icache;
   489 extern uint32_t sh4_icache_addr;
   491 /**
   492  * Translate a single instruction. Delayed branches are handled specially
   493  * by translating both branch and delayed instruction as a single unit (as
   494  * 
   495  *
   496  * @return true if the instruction marks the end of a basic block
   497  * (eg a branch or 
   498  */
   499 uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
   500 {
   501     uint32_t ir;
   502     /* Read instruction */
   503     uint32_t pageaddr = pc >> 12;
   504     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   505 	ir = sh4_icache[(pc&0xFFF)>>1];
   506     } else {
   507 	sh4_icache = (uint16_t *)mem_get_page(pc);
   508 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   509 	    /* If someone's actually been so daft as to try to execute out of an IO
   510 	     * region, fallback on the full-blown memory read
   511 	     */
   512 	    sh4_icache = NULL;
   513 	    ir = sh4_read_word(pc);
   514 	} else {
   515 	    sh4_icache_addr = pageaddr;
   516 	    ir = sh4_icache[(pc&0xFFF)>>1];
   517 	}
   518     }
   520         switch( (ir&0xF000) >> 12 ) {
   521             case 0x0:
   522                 switch( ir&0xF ) {
   523                     case 0x2:
   524                         switch( (ir&0x80) >> 7 ) {
   525                             case 0x0:
   526                                 switch( (ir&0x70) >> 4 ) {
   527                                     case 0x0:
   528                                         { /* STC SR, Rn */
   529                                         uint32_t Rn = ((ir>>8)&0xF); 
   530                                         check_priv();
   531                                         call_func0(sh4_read_sr);
   532                                         store_reg( R_EAX, Rn );
   533                                         }
   534                                         break;
   535                                     case 0x1:
   536                                         { /* STC GBR, Rn */
   537                                         uint32_t Rn = ((ir>>8)&0xF); 
   538                                         load_spreg( R_EAX, R_GBR );
   539                                         store_reg( R_EAX, Rn );
   540                                         }
   541                                         break;
   542                                     case 0x2:
   543                                         { /* STC VBR, Rn */
   544                                         uint32_t Rn = ((ir>>8)&0xF); 
   545                                         check_priv();
   546                                         load_spreg( R_EAX, R_VBR );
   547                                         store_reg( R_EAX, Rn );
   548                                         }
   549                                         break;
   550                                     case 0x3:
   551                                         { /* STC SSR, Rn */
   552                                         uint32_t Rn = ((ir>>8)&0xF); 
   553                                         check_priv();
   554                                         load_spreg( R_EAX, R_SSR );
   555                                         store_reg( R_EAX, Rn );
   556                                         }
   557                                         break;
   558                                     case 0x4:
   559                                         { /* STC SPC, Rn */
   560                                         uint32_t Rn = ((ir>>8)&0xF); 
   561                                         check_priv();
   562                                         load_spreg( R_EAX, R_SPC );
   563                                         store_reg( R_EAX, Rn );
   564                                         }
   565                                         break;
   566                                     default:
   567                                         UNDEF();
   568                                         break;
   569                                 }
   570                                 break;
   571                             case 0x1:
   572                                 { /* STC Rm_BANK, Rn */
   573                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   574                                 check_priv();
   575                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
   576                                 store_reg( R_EAX, Rn );
   577                                 }
   578                                 break;
   579                         }
   580                         break;
   581                     case 0x3:
   582                         switch( (ir&0xF0) >> 4 ) {
   583                             case 0x0:
   584                                 { /* BSRF Rn */
   585                                 uint32_t Rn = ((ir>>8)&0xF); 
   586                                 if( sh4_x86.in_delay_slot ) {
   587                             	SLOTILLEGAL();
   588                                 } else {
   589                             	load_imm32( R_ECX, pc + 4 );
   590                             	store_spreg( R_ECX, R_PR );
   591                             	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
   592                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   593                             	sh4_x86.in_delay_slot = TRUE;
   594                             	sh4_x86_translate_instruction( pc + 2 );
   595                             	exit_block_pcset(pc+2);
   596                             	sh4_x86.branch_taken = TRUE;
   597                             	return 4;
   598                                 }
   599                                 }
   600                                 break;
   601                             case 0x2:
   602                                 { /* BRAF Rn */
   603                                 uint32_t Rn = ((ir>>8)&0xF); 
   604                                 if( sh4_x86.in_delay_slot ) {
   605                             	SLOTILLEGAL();
   606                                 } else {
   607                             	load_reg( R_EAX, Rn );
   608                             	ADD_imm32_r32( pc + 4, R_EAX );
   609                             	store_spreg( R_EAX, REG_OFFSET(pc) );
   610                             	sh4_x86.in_delay_slot = TRUE;
   611                             	sh4_x86_translate_instruction( pc + 2 );
   612                             	exit_block_pcset(pc+2);
   613                             	sh4_x86.branch_taken = TRUE;
   614                             	return 4;
   615                                 }
   616                                 }
   617                                 break;
   618                             case 0x8:
   619                                 { /* PREF @Rn */
   620                                 uint32_t Rn = ((ir>>8)&0xF); 
   621                                 load_reg( R_EAX, Rn );
   622                                 PUSH_r32( R_EAX );
   623                                 AND_imm32_r32( 0xFC000000, R_EAX );
   624                                 CMP_imm32_r32( 0xE0000000, R_EAX );
   625                                 JNE_rel8(7, end);
   626                                 call_func0( sh4_flush_store_queue );
   627                                 JMP_TARGET(end);
   628                                 ADD_imm8s_r32( 4, R_ESP );
   629                                 }
   630                                 break;
   631                             case 0x9:
   632                                 { /* OCBI @Rn */
   633                                 uint32_t Rn = ((ir>>8)&0xF); 
   634                                 }
   635                                 break;
   636                             case 0xA:
   637                                 { /* OCBP @Rn */
   638                                 uint32_t Rn = ((ir>>8)&0xF); 
   639                                 }
   640                                 break;
   641                             case 0xB:
   642                                 { /* OCBWB @Rn */
   643                                 uint32_t Rn = ((ir>>8)&0xF); 
   644                                 }
   645                                 break;
   646                             case 0xC:
   647                                 { /* MOVCA.L R0, @Rn */
   648                                 uint32_t Rn = ((ir>>8)&0xF); 
   649                                 load_reg( R_EAX, 0 );
   650                                 load_reg( R_ECX, Rn );
   651                                 precheck();
   652                                 check_walign32( R_ECX );
   653                                 MEM_WRITE_LONG( R_ECX, R_EAX );
   654                                 }
   655                                 break;
   656                             default:
   657                                 UNDEF();
   658                                 break;
   659                         }
   660                         break;
   661                     case 0x4:
   662                         { /* MOV.B Rm, @(R0, Rn) */
   663                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   664                         load_reg( R_EAX, 0 );
   665                         load_reg( R_ECX, Rn );
   666                         ADD_r32_r32( R_EAX, R_ECX );
   667                         load_reg( R_EAX, Rm );
   668                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   669                         }
   670                         break;
   671                     case 0x5:
   672                         { /* MOV.W Rm, @(R0, Rn) */
   673                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   674                         load_reg( R_EAX, 0 );
   675                         load_reg( R_ECX, Rn );
   676                         ADD_r32_r32( R_EAX, R_ECX );
   677                         precheck();
   678                         check_walign16( R_ECX );
   679                         load_reg( R_EAX, Rm );
   680                         MEM_WRITE_WORD( R_ECX, R_EAX );
   681                         }
   682                         break;
   683                     case 0x6:
   684                         { /* MOV.L Rm, @(R0, Rn) */
   685                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   686                         load_reg( R_EAX, 0 );
   687                         load_reg( R_ECX, Rn );
   688                         ADD_r32_r32( R_EAX, R_ECX );
   689                         precheck();
   690                         check_walign32( R_ECX );
   691                         load_reg( R_EAX, Rm );
   692                         MEM_WRITE_LONG( R_ECX, R_EAX );
   693                         }
   694                         break;
   695                     case 0x7:
   696                         { /* MUL.L Rm, Rn */
   697                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   698                         load_reg( R_EAX, Rm );
   699                         load_reg( R_ECX, Rn );
   700                         MUL_r32( R_ECX );
   701                         store_spreg( R_EAX, R_MACL );
   702                         }
   703                         break;
   704                     case 0x8:
   705                         switch( (ir&0xFF0) >> 4 ) {
   706                             case 0x0:
   707                                 { /* CLRT */
   708                                 CLC();
   709                                 SETC_t();
   710                                 }
   711                                 break;
   712                             case 0x1:
   713                                 { /* SETT */
   714                                 STC();
   715                                 SETC_t();
   716                                 }
   717                                 break;
   718                             case 0x2:
   719                                 { /* CLRMAC */
   720                                 XOR_r32_r32(R_EAX, R_EAX);
   721                                 store_spreg( R_EAX, R_MACL );
   722                                 store_spreg( R_EAX, R_MACH );
   723                                 }
   724                                 break;
   725                             case 0x3:
   726                                 { /* LDTLB */
   727                                 }
   728                                 break;
   729                             case 0x4:
   730                                 { /* CLRS */
   731                                 CLC();
   732                                 SETC_sh4r(R_S);
   733                                 }
   734                                 break;
   735                             case 0x5:
   736                                 { /* SETS */
   737                                 STC();
   738                                 SETC_sh4r(R_S);
   739                                 }
   740                                 break;
   741                             default:
   742                                 UNDEF();
   743                                 break;
   744                         }
   745                         break;
   746                     case 0x9:
   747                         switch( (ir&0xF0) >> 4 ) {
   748                             case 0x0:
   749                                 { /* NOP */
   750                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
   751                                 }
   752                                 break;
   753                             case 0x1:
   754                                 { /* DIV0U */
   755                                 XOR_r32_r32( R_EAX, R_EAX );
   756                                 store_spreg( R_EAX, R_Q );
   757                                 store_spreg( R_EAX, R_M );
   758                                 store_spreg( R_EAX, R_T );
   759                                 }
   760                                 break;
   761                             case 0x2:
   762                                 { /* MOVT Rn */
   763                                 uint32_t Rn = ((ir>>8)&0xF); 
   764                                 load_spreg( R_EAX, R_T );
   765                                 store_reg( R_EAX, Rn );
   766                                 }
   767                                 break;
   768                             default:
   769                                 UNDEF();
   770                                 break;
   771                         }
   772                         break;
   773                     case 0xA:
   774                         switch( (ir&0xF0) >> 4 ) {
   775                             case 0x0:
   776                                 { /* STS MACH, Rn */
   777                                 uint32_t Rn = ((ir>>8)&0xF); 
   778                                 load_spreg( R_EAX, R_MACH );
   779                                 store_reg( R_EAX, Rn );
   780                                 }
   781                                 break;
   782                             case 0x1:
   783                                 { /* STS MACL, Rn */
   784                                 uint32_t Rn = ((ir>>8)&0xF); 
   785                                 load_spreg( R_EAX, R_MACL );
   786                                 store_reg( R_EAX, Rn );
   787                                 }
   788                                 break;
   789                             case 0x2:
   790                                 { /* STS PR, Rn */
   791                                 uint32_t Rn = ((ir>>8)&0xF); 
   792                                 load_spreg( R_EAX, R_PR );
   793                                 store_reg( R_EAX, Rn );
   794                                 }
   795                                 break;
   796                             case 0x3:
   797                                 { /* STC SGR, Rn */
   798                                 uint32_t Rn = ((ir>>8)&0xF); 
   799                                 check_priv();
   800                                 load_spreg( R_EAX, R_SGR );
   801                                 store_reg( R_EAX, Rn );
   802                                 }
   803                                 break;
   804                             case 0x5:
   805                                 { /* STS FPUL, Rn */
   806                                 uint32_t Rn = ((ir>>8)&0xF); 
   807                                 load_spreg( R_EAX, R_FPUL );
   808                                 store_reg( R_EAX, Rn );
   809                                 }
   810                                 break;
   811                             case 0x6:
   812                                 { /* STS FPSCR, Rn */
   813                                 uint32_t Rn = ((ir>>8)&0xF); 
   814                                 load_spreg( R_EAX, R_FPSCR );
   815                                 store_reg( R_EAX, Rn );
   816                                 }
   817                                 break;
   818                             case 0xF:
   819                                 { /* STC DBR, Rn */
   820                                 uint32_t Rn = ((ir>>8)&0xF); 
   821                                 check_priv();
   822                                 load_spreg( R_EAX, R_DBR );
   823                                 store_reg( R_EAX, Rn );
   824                                 }
   825                                 break;
   826                             default:
   827                                 UNDEF();
   828                                 break;
   829                         }
   830                         break;
   831                     case 0xB:
   832                         switch( (ir&0xFF0) >> 4 ) {
   833                             case 0x0:
   834                                 { /* RTS */
   835                                 if( sh4_x86.in_delay_slot ) {
   836                             	SLOTILLEGAL();
   837                                 } else {
   838                             	load_spreg( R_ECX, R_PR );
   839                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   840                             	sh4_x86.in_delay_slot = TRUE;
   841                             	sh4_x86_translate_instruction(pc+2);
   842                             	exit_block_pcset(pc+2);
   843                             	sh4_x86.branch_taken = TRUE;
   844                             	return 4;
   845                                 }
   846                                 }
   847                                 break;
   848                             case 0x1:
   849                                 { /* SLEEP */
   850                                 check_priv();
   851                                 call_func0( sh4_sleep );
   852                                 sh4_x86.in_delay_slot = FALSE;
   853                                 return 2;
   854                                 }
   855                                 break;
   856                             case 0x2:
   857                                 { /* RTE */
   858                                 if( sh4_x86.in_delay_slot ) {
   859                             	SLOTILLEGAL();
   860                                 } else {
   861                             	check_priv();
   862                             	load_spreg( R_ECX, R_SPC );
   863                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   864                             	load_spreg( R_EAX, R_SSR );
   865                             	call_func1( sh4_write_sr, R_EAX );
   866                             	sh4_x86.in_delay_slot = TRUE;
   867                             	sh4_x86.priv_checked = FALSE;
   868                             	sh4_x86.fpuen_checked = FALSE;
   869                             	sh4_x86_translate_instruction(pc+2);
   870                             	exit_block_pcset(pc+2);
   871                             	sh4_x86.branch_taken = TRUE;
   872                             	return 4;
   873                                 }
   874                                 }
   875                                 break;
   876                             default:
   877                                 UNDEF();
   878                                 break;
   879                         }
   880                         break;
   881                     case 0xC:
   882                         { /* MOV.B @(R0, Rm), Rn */
   883                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   884                         load_reg( R_EAX, 0 );
   885                         load_reg( R_ECX, Rm );
   886                         ADD_r32_r32( R_EAX, R_ECX );
   887                         MEM_READ_BYTE( R_ECX, R_EAX );
   888                         store_reg( R_EAX, Rn );
   889                         }
   890                         break;
   891                     case 0xD:
   892                         { /* MOV.W @(R0, Rm), Rn */
   893                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   894                         load_reg( R_EAX, 0 );
   895                         load_reg( R_ECX, Rm );
   896                         ADD_r32_r32( R_EAX, R_ECX );
   897                         precheck();
   898                         check_ralign16( R_ECX );
   899                         MEM_READ_WORD( R_ECX, R_EAX );
   900                         store_reg( R_EAX, Rn );
   901                         }
   902                         break;
   903                     case 0xE:
   904                         { /* MOV.L @(R0, Rm), Rn */
   905                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   906                         load_reg( R_EAX, 0 );
   907                         load_reg( R_ECX, Rm );
   908                         ADD_r32_r32( R_EAX, R_ECX );
   909                         precheck();
   910                         check_ralign32( R_ECX );
   911                         MEM_READ_LONG( R_ECX, R_EAX );
   912                         store_reg( R_EAX, Rn );
   913                         }
   914                         break;
   915                     case 0xF:
   916                         { /* MAC.L @Rm+, @Rn+ */
   917                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   918                         load_reg( R_ECX, Rm );
   919                         precheck();
   920                         check_ralign32( R_ECX );
   921                         load_reg( R_ECX, Rn );
   922                         check_ralign32( R_ECX );
   923                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
   924                         MEM_READ_LONG( R_ECX, R_EAX );
   925                         PUSH_r32( R_EAX );
   926                         load_reg( R_ECX, Rm );
   927                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
   928                         MEM_READ_LONG( R_ECX, R_EAX );
   929                         POP_r32( R_ECX );
   930                         IMUL_r32( R_ECX );
   931                         ADD_r32_sh4r( R_EAX, R_MACL );
   932                         ADC_r32_sh4r( R_EDX, R_MACH );
   934                         load_spreg( R_ECX, R_S );
   935                         TEST_r32_r32(R_ECX, R_ECX);
   936                         JE_rel8( 7, nosat );
   937                         call_func0( signsat48 );
   938                         JMP_TARGET( nosat );
   939                         }
   940                         break;
   941                     default:
   942                         UNDEF();
   943                         break;
   944                 }
   945                 break;
   946             case 0x1:
   947                 { /* MOV.L Rm, @(disp, Rn) */
   948                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   949                 load_reg( R_ECX, Rn );
   950                 load_reg( R_EAX, Rm );
   951                 ADD_imm32_r32( disp, R_ECX );
   952                 precheck();
   953                 check_walign32( R_ECX );
   954                 MEM_WRITE_LONG( R_ECX, R_EAX );
   955                 }
   956                 break;
   957             case 0x2:
   958                 switch( ir&0xF ) {
   959                     case 0x0:
   960                         { /* MOV.B Rm, @Rn */
   961                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   962                         load_reg( R_EAX, Rm );
   963                         load_reg( R_ECX, Rn );
   964                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   965                         }
   966                         break;
   967                     case 0x1:
   968                         { /* MOV.W Rm, @Rn */
   969                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   970                         load_reg( R_ECX, Rn );
   971                         precheck();
   972                         check_walign16( R_ECX );
   973                         load_reg( R_EAX, Rm );
   974                         MEM_WRITE_WORD( R_ECX, R_EAX );
   975                         }
   976                         break;
   977                     case 0x2:
   978                         { /* MOV.L Rm, @Rn */
   979                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   980                         load_reg( R_EAX, Rm );
   981                         load_reg( R_ECX, Rn );
   982                         precheck();
   983                         check_walign32(R_ECX);
   984                         MEM_WRITE_LONG( R_ECX, R_EAX );
   985                         }
   986                         break;
   987                     case 0x4:
   988                         { /* MOV.B Rm, @-Rn */
   989                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   990                         load_reg( R_EAX, Rm );
   991                         load_reg( R_ECX, Rn );
   992                         ADD_imm8s_r32( -1, R_ECX );
   993                         store_reg( R_ECX, Rn );
   994                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   995                         }
   996                         break;
   997                     case 0x5:
   998                         { /* MOV.W Rm, @-Rn */
   999                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1000                         load_reg( R_ECX, Rn );
  1001                         precheck();
  1002                         check_walign16( R_ECX );
  1003                         load_reg( R_EAX, Rm );
  1004                         ADD_imm8s_r32( -2, R_ECX );
  1005                         store_reg( R_ECX, Rn );
  1006                         MEM_WRITE_WORD( R_ECX, R_EAX );
  1008                         break;
  1009                     case 0x6:
  1010                         { /* MOV.L Rm, @-Rn */
  1011                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1012                         load_reg( R_EAX, Rm );
  1013                         load_reg( R_ECX, Rn );
  1014                         precheck();
  1015                         check_walign32( R_ECX );
  1016                         ADD_imm8s_r32( -4, R_ECX );
  1017                         store_reg( R_ECX, Rn );
  1018                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1020                         break;
  1021                     case 0x7:
  1022                         { /* DIV0S Rm, Rn */
  1023                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1024                         load_reg( R_EAX, Rm );
  1025                         load_reg( R_ECX, Rn );
  1026                         SHR_imm8_r32( 31, R_EAX );
  1027                         SHR_imm8_r32( 31, R_ECX );
  1028                         store_spreg( R_EAX, R_M );
  1029                         store_spreg( R_ECX, R_Q );
  1030                         CMP_r32_r32( R_EAX, R_ECX );
  1031                         SETNE_t();
  1033                         break;
  1034                     case 0x8:
  1035                         { /* TST Rm, Rn */
  1036                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1037                         load_reg( R_EAX, Rm );
  1038                         load_reg( R_ECX, Rn );
  1039                         TEST_r32_r32( R_EAX, R_ECX );
  1040                         SETE_t();
  1042                         break;
  1043                     case 0x9:
  1044                         { /* AND Rm, Rn */
  1045                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1046                         load_reg( R_EAX, Rm );
  1047                         load_reg( R_ECX, Rn );
  1048                         AND_r32_r32( R_EAX, R_ECX );
  1049                         store_reg( R_ECX, Rn );
  1051                         break;
  1052                     case 0xA:
  1053                         { /* XOR Rm, Rn */
  1054                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1055                         load_reg( R_EAX, Rm );
  1056                         load_reg( R_ECX, Rn );
  1057                         XOR_r32_r32( R_EAX, R_ECX );
  1058                         store_reg( R_ECX, Rn );
  1060                         break;
  1061                     case 0xB:
  1062                         { /* OR Rm, Rn */
  1063                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1064                         load_reg( R_EAX, Rm );
  1065                         load_reg( R_ECX, Rn );
  1066                         OR_r32_r32( R_EAX, R_ECX );
  1067                         store_reg( R_ECX, Rn );
  1069                         break;
  1070                     case 0xC:
  1071                         { /* CMP/STR Rm, Rn */
  1072                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1073                         load_reg( R_EAX, Rm );
  1074                         load_reg( R_ECX, Rn );
  1075                         XOR_r32_r32( R_ECX, R_EAX );
  1076                         TEST_r8_r8( R_AL, R_AL );
  1077                         JE_rel8(13, target1);
  1078                         TEST_r8_r8( R_AH, R_AH ); // 2
  1079                         JE_rel8(9, target2);
  1080                         SHR_imm8_r32( 16, R_EAX ); // 3
  1081                         TEST_r8_r8( R_AL, R_AL ); // 2
  1082                         JE_rel8(2, target3);
  1083                         TEST_r8_r8( R_AH, R_AH ); // 2
  1084                         JMP_TARGET(target1);
  1085                         JMP_TARGET(target2);
  1086                         JMP_TARGET(target3);
  1087                         SETE_t();
  1089                         break;
  1090                     case 0xD:
  1091                         { /* XTRCT Rm, Rn */
  1092                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1093                         load_reg( R_EAX, Rm );
  1094                         load_reg( R_ECX, Rn );
  1095                         SHL_imm8_r32( 16, R_EAX );
  1096                         SHR_imm8_r32( 16, R_ECX );
  1097                         OR_r32_r32( R_EAX, R_ECX );
  1098                         store_reg( R_ECX, Rn );
  1100                         break;
  1101                     case 0xE:
  1102                         { /* MULU.W Rm, Rn */
  1103                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1104                         load_reg16u( R_EAX, Rm );
  1105                         load_reg16u( R_ECX, Rn );
  1106                         MUL_r32( R_ECX );
  1107                         store_spreg( R_EAX, R_MACL );
  1109                         break;
  1110                     case 0xF:
  1111                         { /* MULS.W Rm, Rn */
  1112                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1113                         load_reg16s( R_EAX, Rm );
  1114                         load_reg16s( R_ECX, Rn );
  1115                         MUL_r32( R_ECX );
  1116                         store_spreg( R_EAX, R_MACL );
  1118                         break;
  1119                     default:
  1120                         UNDEF();
  1121                         break;
  1123                 break;
  1124             case 0x3:
  1125                 switch( ir&0xF ) {
  1126                     case 0x0:
  1127                         { /* CMP/EQ Rm, Rn */
  1128                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1129                         load_reg( R_EAX, Rm );
  1130                         load_reg( R_ECX, Rn );
  1131                         CMP_r32_r32( R_EAX, R_ECX );
  1132                         SETE_t();
  1134                         break;
  1135                     case 0x2:
  1136                         { /* CMP/HS Rm, Rn */
  1137                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1138                         load_reg( R_EAX, Rm );
  1139                         load_reg( R_ECX, Rn );
  1140                         CMP_r32_r32( R_EAX, R_ECX );
  1141                         SETAE_t();
  1143                         break;
  1144                     case 0x3:
  1145                         { /* CMP/GE Rm, Rn */
  1146                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1147                         load_reg( R_EAX, Rm );
  1148                         load_reg( R_ECX, Rn );
  1149                         CMP_r32_r32( R_EAX, R_ECX );
  1150                         SETGE_t();
  1152                         break;
  1153                     case 0x4:
  1154                         { /* DIV1 Rm, Rn */
  1155                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1156                         load_spreg( R_ECX, R_M );
  1157                         load_reg( R_EAX, Rn );
  1158                         LDC_t();
  1159                         RCL1_r32( R_EAX );
  1160                         SETC_r8( R_DL ); // Q'
  1161                         CMP_sh4r_r32( R_Q, R_ECX );
  1162                         JE_rel8(5, mqequal);
  1163                         ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1164                         JMP_rel8(3, end);
  1165                         JMP_TARGET(mqequal);
  1166                         SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1167                         JMP_TARGET(end);
  1168                         store_reg( R_EAX, Rn ); // Done with Rn now
  1169                         SETC_r8(R_AL); // tmp1
  1170                         XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
  1171                         XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
  1172                         store_spreg( R_ECX, R_Q );
  1173                         XOR_imm8s_r32( 1, R_AL );   // T = !Q'
  1174                         MOVZX_r8_r32( R_AL, R_EAX );
  1175                         store_spreg( R_EAX, R_T );
  1177                         break;
  1178                     case 0x5:
  1179                         { /* DMULU.L Rm, Rn */
  1180                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1181                         load_reg( R_EAX, Rm );
  1182                         load_reg( R_ECX, Rn );
  1183                         MUL_r32(R_ECX);
  1184                         store_spreg( R_EDX, R_MACH );
  1185                         store_spreg( R_EAX, R_MACL );
  1187                         break;
  1188                     case 0x6:
  1189                         { /* CMP/HI Rm, Rn */
  1190                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1191                         load_reg( R_EAX, Rm );
  1192                         load_reg( R_ECX, Rn );
  1193                         CMP_r32_r32( R_EAX, R_ECX );
  1194                         SETA_t();
  1196                         break;
  1197                     case 0x7:
  1198                         { /* CMP/GT Rm, Rn */
  1199                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1200                         load_reg( R_EAX, Rm );
  1201                         load_reg( R_ECX, Rn );
  1202                         CMP_r32_r32( R_EAX, R_ECX );
  1203                         SETG_t();
  1205                         break;
  1206                     case 0x8:
  1207                         { /* SUB Rm, Rn */
  1208                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1209                         load_reg( R_EAX, Rm );
  1210                         load_reg( R_ECX, Rn );
  1211                         SUB_r32_r32( R_EAX, R_ECX );
  1212                         store_reg( R_ECX, Rn );
  1214                         break;
  1215                     case 0xA:
  1216                         { /* SUBC Rm, Rn */
  1217                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1218                         load_reg( R_EAX, Rm );
  1219                         load_reg( R_ECX, Rn );
  1220                         LDC_t();
  1221                         SBB_r32_r32( R_EAX, R_ECX );
  1222                         store_reg( R_ECX, Rn );
  1223                         SETC_t();
  1225                         break;
  1226                     case 0xB:
  1227                         { /* SUBV Rm, Rn */
  1228                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1229                         load_reg( R_EAX, Rm );
  1230                         load_reg( R_ECX, Rn );
  1231                         SUB_r32_r32( R_EAX, R_ECX );
  1232                         store_reg( R_ECX, Rn );
  1233                         SETO_t();
  1235                         break;
  1236                     case 0xC:
  1237                         { /* ADD Rm, Rn */
  1238                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1239                         load_reg( R_EAX, Rm );
  1240                         load_reg( R_ECX, Rn );
  1241                         ADD_r32_r32( R_EAX, R_ECX );
  1242                         store_reg( R_ECX, Rn );
  1244                         break;
  1245                     case 0xD:
  1246                         { /* DMULS.L Rm, Rn */
  1247                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1248                         load_reg( R_EAX, Rm );
  1249                         load_reg( R_ECX, Rn );
  1250                         IMUL_r32(R_ECX);
  1251                         store_spreg( R_EDX, R_MACH );
  1252                         store_spreg( R_EAX, R_MACL );
  1254                         break;
  1255                     case 0xE:
  1256                         { /* ADDC Rm, Rn */
  1257                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1258                         load_reg( R_EAX, Rm );
  1259                         load_reg( R_ECX, Rn );
  1260                         LDC_t();
  1261                         ADC_r32_r32( R_EAX, R_ECX );
  1262                         store_reg( R_ECX, Rn );
  1263                         SETC_t();
  1265                         break;
  1266                     case 0xF:
  1267                         { /* ADDV Rm, Rn */
  1268                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1269                         load_reg( R_EAX, Rm );
  1270                         load_reg( R_ECX, Rn );
  1271                         ADD_r32_r32( R_EAX, R_ECX );
  1272                         store_reg( R_ECX, Rn );
  1273                         SETO_t();
  1275                         break;
  1276                     default:
  1277                         UNDEF();
  1278                         break;
  1280                 break;
  1281             case 0x4:
  1282                 switch( ir&0xF ) {
  1283                     case 0x0:
  1284                         switch( (ir&0xF0) >> 4 ) {
  1285                             case 0x0:
  1286                                 { /* SHLL Rn */
  1287                                 uint32_t Rn = ((ir>>8)&0xF); 
  1288                                 load_reg( R_EAX, Rn );
  1289                                 SHL1_r32( R_EAX );
  1290                                 SETC_t();
  1291                                 store_reg( R_EAX, Rn );
  1293                                 break;
  1294                             case 0x1:
  1295                                 { /* DT Rn */
  1296                                 uint32_t Rn = ((ir>>8)&0xF); 
  1297                                 load_reg( R_EAX, Rn );
  1298                                 ADD_imm8s_r32( -1, R_EAX );
  1299                                 store_reg( R_EAX, Rn );
  1300                                 SETE_t();
  1302                                 break;
  1303                             case 0x2:
  1304                                 { /* SHAL Rn */
  1305                                 uint32_t Rn = ((ir>>8)&0xF); 
  1306                                 load_reg( R_EAX, Rn );
  1307                                 SHL1_r32( R_EAX );
  1308                                 SETC_t();
  1309                                 store_reg( R_EAX, Rn );
  1311                                 break;
  1312                             default:
  1313                                 UNDEF();
  1314                                 break;
  1316                         break;
  1317                     case 0x1:
  1318                         switch( (ir&0xF0) >> 4 ) {
  1319                             case 0x0:
  1320                                 { /* SHLR Rn */
  1321                                 uint32_t Rn = ((ir>>8)&0xF); 
  1322                                 load_reg( R_EAX, Rn );
  1323                                 SHR1_r32( R_EAX );
  1324                                 SETC_t();
  1325                                 store_reg( R_EAX, Rn );
  1327                                 break;
  1328                             case 0x1:
  1329                                 { /* CMP/PZ Rn */
  1330                                 uint32_t Rn = ((ir>>8)&0xF); 
  1331                                 load_reg( R_EAX, Rn );
  1332                                 CMP_imm8s_r32( 0, R_EAX );
  1333                                 SETGE_t();
  1335                                 break;
  1336                             case 0x2:
  1337                                 { /* SHAR Rn */
  1338                                 uint32_t Rn = ((ir>>8)&0xF); 
  1339                                 load_reg( R_EAX, Rn );
  1340                                 SAR1_r32( R_EAX );
  1341                                 SETC_t();
  1342                                 store_reg( R_EAX, Rn );
  1344                                 break;
  1345                             default:
  1346                                 UNDEF();
  1347                                 break;
  1349                         break;
  1350                     case 0x2:
  1351                         switch( (ir&0xF0) >> 4 ) {
  1352                             case 0x0:
  1353                                 { /* STS.L MACH, @-Rn */
  1354                                 uint32_t Rn = ((ir>>8)&0xF); 
  1355                                 load_reg( R_ECX, Rn );
  1356                                 precheck();
  1357                                 check_walign32( R_ECX );
  1358                                 ADD_imm8s_r32( -4, R_ECX );
  1359                                 store_reg( R_ECX, Rn );
  1360                                 load_spreg( R_EAX, R_MACH );
  1361                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1363                                 break;
  1364                             case 0x1:
  1365                                 { /* STS.L MACL, @-Rn */
  1366                                 uint32_t Rn = ((ir>>8)&0xF); 
  1367                                 load_reg( R_ECX, Rn );
  1368                                 precheck();
  1369                                 check_walign32( R_ECX );
  1370                                 ADD_imm8s_r32( -4, R_ECX );
  1371                                 store_reg( R_ECX, Rn );
  1372                                 load_spreg( R_EAX, R_MACL );
  1373                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1375                                 break;
  1376                             case 0x2:
  1377                                 { /* STS.L PR, @-Rn */
  1378                                 uint32_t Rn = ((ir>>8)&0xF); 
  1379                                 load_reg( R_ECX, Rn );
  1380                                 precheck();
  1381                                 check_walign32( R_ECX );
  1382                                 ADD_imm8s_r32( -4, R_ECX );
  1383                                 store_reg( R_ECX, Rn );
  1384                                 load_spreg( R_EAX, R_PR );
  1385                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1387                                 break;
  1388                             case 0x3:
  1389                                 { /* STC.L SGR, @-Rn */
  1390                                 uint32_t Rn = ((ir>>8)&0xF); 
  1391                                 precheck();
  1392                                 check_priv_no_precheck();
  1393                                 load_reg( R_ECX, Rn );
  1394                                 check_walign32( R_ECX );
  1395                                 ADD_imm8s_r32( -4, R_ECX );
  1396                                 store_reg( R_ECX, Rn );
  1397                                 load_spreg( R_EAX, R_SGR );
  1398                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1400                                 break;
  1401                             case 0x5:
  1402                                 { /* STS.L FPUL, @-Rn */
  1403                                 uint32_t Rn = ((ir>>8)&0xF); 
  1404                                 load_reg( R_ECX, Rn );
  1405                                 precheck();
  1406                                 check_walign32( R_ECX );
  1407                                 ADD_imm8s_r32( -4, R_ECX );
  1408                                 store_reg( R_ECX, Rn );
  1409                                 load_spreg( R_EAX, R_FPUL );
  1410                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1412                                 break;
  1413                             case 0x6:
  1414                                 { /* STS.L FPSCR, @-Rn */
  1415                                 uint32_t Rn = ((ir>>8)&0xF); 
  1416                                 load_reg( R_ECX, Rn );
  1417                                 precheck();
  1418                                 check_walign32( R_ECX );
  1419                                 ADD_imm8s_r32( -4, R_ECX );
  1420                                 store_reg( R_ECX, Rn );
  1421                                 load_spreg( R_EAX, R_FPSCR );
  1422                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1424                                 break;
  1425                             case 0xF:
  1426                                 { /* STC.L DBR, @-Rn */
  1427                                 uint32_t Rn = ((ir>>8)&0xF); 
  1428                                 precheck();
  1429                                 check_priv_no_precheck();
  1430                                 load_reg( R_ECX, Rn );
  1431                                 check_walign32( R_ECX );
  1432                                 ADD_imm8s_r32( -4, R_ECX );
  1433                                 store_reg( R_ECX, Rn );
  1434                                 load_spreg( R_EAX, R_DBR );
  1435                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1437                                 break;
  1438                             default:
  1439                                 UNDEF();
  1440                                 break;
  1442                         break;
  1443                     case 0x3:
  1444                         switch( (ir&0x80) >> 7 ) {
  1445                             case 0x0:
  1446                                 switch( (ir&0x70) >> 4 ) {
  1447                                     case 0x0:
  1448                                         { /* STC.L SR, @-Rn */
  1449                                         uint32_t Rn = ((ir>>8)&0xF); 
  1450                                         precheck();
  1451                                         check_priv_no_precheck();
  1452                                         call_func0( sh4_read_sr );
  1453                                         load_reg( R_ECX, Rn );
  1454                                         check_walign32( R_ECX );
  1455                                         ADD_imm8s_r32( -4, R_ECX );
  1456                                         store_reg( R_ECX, Rn );
  1457                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1459                                         break;
  1460                                     case 0x1:
  1461                                         { /* STC.L GBR, @-Rn */
  1462                                         uint32_t Rn = ((ir>>8)&0xF); 
  1463                                         load_reg( R_ECX, Rn );
  1464                                         precheck();
  1465                                         check_walign32( R_ECX );
  1466                                         ADD_imm8s_r32( -4, R_ECX );
  1467                                         store_reg( R_ECX, Rn );
  1468                                         load_spreg( R_EAX, R_GBR );
  1469                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1471                                         break;
  1472                                     case 0x2:
  1473                                         { /* STC.L VBR, @-Rn */
  1474                                         uint32_t Rn = ((ir>>8)&0xF); 
  1475                                         precheck();
  1476                                         check_priv_no_precheck();
  1477                                         load_reg( R_ECX, Rn );
  1478                                         check_walign32( R_ECX );
  1479                                         ADD_imm8s_r32( -4, R_ECX );
  1480                                         store_reg( R_ECX, Rn );
  1481                                         load_spreg( R_EAX, R_VBR );
  1482                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1484                                         break;
  1485                                     case 0x3:
  1486                                         { /* STC.L SSR, @-Rn */
  1487                                         uint32_t Rn = ((ir>>8)&0xF); 
  1488                                         precheck();
  1489                                         check_priv_no_precheck();
  1490                                         load_reg( R_ECX, Rn );
  1491                                         check_walign32( R_ECX );
  1492                                         ADD_imm8s_r32( -4, R_ECX );
  1493                                         store_reg( R_ECX, Rn );
  1494                                         load_spreg( R_EAX, R_SSR );
  1495                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1497                                         break;
  1498                                     case 0x4:
  1499                                         { /* STC.L SPC, @-Rn */
  1500                                         uint32_t Rn = ((ir>>8)&0xF); 
  1501                                         precheck();
  1502                                         check_priv_no_precheck();
  1503                                         load_reg( R_ECX, Rn );
  1504                                         check_walign32( R_ECX );
  1505                                         ADD_imm8s_r32( -4, R_ECX );
  1506                                         store_reg( R_ECX, Rn );
  1507                                         load_spreg( R_EAX, R_SPC );
  1508                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1510                                         break;
  1511                                     default:
  1512                                         UNDEF();
  1513                                         break;
  1515                                 break;
  1516                             case 0x1:
  1517                                 { /* STC.L Rm_BANK, @-Rn */
  1518                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1519                                 precheck();
  1520                                 check_priv_no_precheck();
  1521                                 load_reg( R_ECX, Rn );
  1522                                 check_walign32( R_ECX );
  1523                                 ADD_imm8s_r32( -4, R_ECX );
  1524                                 store_reg( R_ECX, Rn );
  1525                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
  1526                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1528                                 break;
  1530                         break;
  1531                     case 0x4:
  1532                         switch( (ir&0xF0) >> 4 ) {
  1533                             case 0x0:
  1534                                 { /* ROTL Rn */
  1535                                 uint32_t Rn = ((ir>>8)&0xF); 
  1536                                 load_reg( R_EAX, Rn );
  1537                                 ROL1_r32( R_EAX );
  1538                                 store_reg( R_EAX, Rn );
  1539                                 SETC_t();
  1541                                 break;
  1542                             case 0x2:
  1543                                 { /* ROTCL Rn */
  1544                                 uint32_t Rn = ((ir>>8)&0xF); 
  1545                                 load_reg( R_EAX, Rn );
  1546                                 LDC_t();
  1547                                 RCL1_r32( R_EAX );
  1548                                 store_reg( R_EAX, Rn );
  1549                                 SETC_t();
  1551                                 break;
  1552                             default:
  1553                                 UNDEF();
  1554                                 break;
  1556                         break;
  1557                     case 0x5:
  1558                         switch( (ir&0xF0) >> 4 ) {
  1559                             case 0x0:
  1560                                 { /* ROTR Rn */
  1561                                 uint32_t Rn = ((ir>>8)&0xF); 
  1562                                 load_reg( R_EAX, Rn );
  1563                                 ROR1_r32( R_EAX );
  1564                                 store_reg( R_EAX, Rn );
  1565                                 SETC_t();
  1567                                 break;
  1568                             case 0x1:
  1569                                 { /* CMP/PL Rn */
  1570                                 uint32_t Rn = ((ir>>8)&0xF); 
  1571                                 load_reg( R_EAX, Rn );
  1572                                 CMP_imm8s_r32( 0, R_EAX );
  1573                                 SETG_t();
  1575                                 break;
  1576                             case 0x2:
  1577                                 { /* ROTCR Rn */
  1578                                 uint32_t Rn = ((ir>>8)&0xF); 
  1579                                 load_reg( R_EAX, Rn );
  1580                                 LDC_t();
  1581                                 RCR1_r32( R_EAX );
  1582                                 store_reg( R_EAX, Rn );
  1583                                 SETC_t();
  1585                                 break;
  1586                             default:
  1587                                 UNDEF();
  1588                                 break;
  1590                         break;
  1591                     case 0x6:
  1592                         switch( (ir&0xF0) >> 4 ) {
  1593                             case 0x0:
  1594                                 { /* LDS.L @Rm+, MACH */
  1595                                 uint32_t Rm = ((ir>>8)&0xF); 
  1596                                 load_reg( R_EAX, Rm );
  1597                                 precheck();
  1598                                 check_ralign32( R_EAX );
  1599                                 MOV_r32_r32( R_EAX, R_ECX );
  1600                                 ADD_imm8s_r32( 4, R_EAX );
  1601                                 store_reg( R_EAX, Rm );
  1602                                 MEM_READ_LONG( R_ECX, R_EAX );
  1603                                 store_spreg( R_EAX, R_MACH );
  1605                                 break;
  1606                             case 0x1:
  1607                                 { /* LDS.L @Rm+, MACL */
  1608                                 uint32_t Rm = ((ir>>8)&0xF); 
  1609                                 load_reg( R_EAX, Rm );
  1610                                 precheck();
  1611                                 check_ralign32( R_EAX );
  1612                                 MOV_r32_r32( R_EAX, R_ECX );
  1613                                 ADD_imm8s_r32( 4, R_EAX );
  1614                                 store_reg( R_EAX, Rm );
  1615                                 MEM_READ_LONG( R_ECX, R_EAX );
  1616                                 store_spreg( R_EAX, R_MACL );
  1618                                 break;
  1619                             case 0x2:
  1620                                 { /* LDS.L @Rm+, PR */
  1621                                 uint32_t Rm = ((ir>>8)&0xF); 
  1622                                 load_reg( R_EAX, Rm );
  1623                                 precheck();
  1624                                 check_ralign32( R_EAX );
  1625                                 MOV_r32_r32( R_EAX, R_ECX );
  1626                                 ADD_imm8s_r32( 4, R_EAX );
  1627                                 store_reg( R_EAX, Rm );
  1628                                 MEM_READ_LONG( R_ECX, R_EAX );
  1629                                 store_spreg( R_EAX, R_PR );
  1631                                 break;
  1632                             case 0x3:
  1633                                 { /* LDC.L @Rm+, SGR */
  1634                                 uint32_t Rm = ((ir>>8)&0xF); 
  1635                                 precheck();
  1636                                 check_priv_no_precheck();
  1637                                 load_reg( R_EAX, Rm );
  1638                                 check_ralign32( R_EAX );
  1639                                 MOV_r32_r32( R_EAX, R_ECX );
  1640                                 ADD_imm8s_r32( 4, R_EAX );
  1641                                 store_reg( R_EAX, Rm );
  1642                                 MEM_READ_LONG( R_ECX, R_EAX );
  1643                                 store_spreg( R_EAX, R_SGR );
  1645                                 break;
  1646                             case 0x5:
  1647                                 { /* LDS.L @Rm+, FPUL */
  1648                                 uint32_t Rm = ((ir>>8)&0xF); 
  1649                                 load_reg( R_EAX, Rm );
  1650                                 precheck();
  1651                                 check_ralign32( R_EAX );
  1652                                 MOV_r32_r32( R_EAX, R_ECX );
  1653                                 ADD_imm8s_r32( 4, R_EAX );
  1654                                 store_reg( R_EAX, Rm );
  1655                                 MEM_READ_LONG( R_ECX, R_EAX );
  1656                                 store_spreg( R_EAX, R_FPUL );
  1658                                 break;
  1659                             case 0x6:
  1660                                 { /* LDS.L @Rm+, FPSCR */
  1661                                 uint32_t Rm = ((ir>>8)&0xF); 
  1662                                 load_reg( R_EAX, Rm );
  1663                                 precheck();
  1664                                 check_ralign32( R_EAX );
  1665                                 MOV_r32_r32( R_EAX, R_ECX );
  1666                                 ADD_imm8s_r32( 4, R_EAX );
  1667                                 store_reg( R_EAX, Rm );
  1668                                 MEM_READ_LONG( R_ECX, R_EAX );
  1669                                 store_spreg( R_EAX, R_FPSCR );
  1670                                 update_fr_bank( R_EAX );
  1672                                 break;
  1673                             case 0xF:
  1674                                 { /* LDC.L @Rm+, DBR */
  1675                                 uint32_t Rm = ((ir>>8)&0xF); 
  1676                                 precheck();
  1677                                 check_priv_no_precheck();
  1678                                 load_reg( R_EAX, Rm );
  1679                                 check_ralign32( R_EAX );
  1680                                 MOV_r32_r32( R_EAX, R_ECX );
  1681                                 ADD_imm8s_r32( 4, R_EAX );
  1682                                 store_reg( R_EAX, Rm );
  1683                                 MEM_READ_LONG( R_ECX, R_EAX );
  1684                                 store_spreg( R_EAX, R_DBR );
  1686                                 break;
  1687                             default:
  1688                                 UNDEF();
  1689                                 break;
  1691                         break;
  1692                     case 0x7:
  1693                         switch( (ir&0x80) >> 7 ) {
  1694                             case 0x0:
  1695                                 switch( (ir&0x70) >> 4 ) {
  1696                                     case 0x0:
  1697                                         { /* LDC.L @Rm+, SR */
  1698                                         uint32_t Rm = ((ir>>8)&0xF); 
  1699                                         if( sh4_x86.in_delay_slot ) {
  1700                                     	SLOTILLEGAL();
  1701                                         } else {
  1702                                     	precheck();
  1703                                     	check_priv_no_precheck();
  1704                                     	load_reg( R_EAX, Rm );
  1705                                     	check_ralign32( R_EAX );
  1706                                     	MOV_r32_r32( R_EAX, R_ECX );
  1707                                     	ADD_imm8s_r32( 4, R_EAX );
  1708                                     	store_reg( R_EAX, Rm );
  1709                                     	MEM_READ_LONG( R_ECX, R_EAX );
  1710                                     	call_func1( sh4_write_sr, R_EAX );
  1711                                     	sh4_x86.priv_checked = FALSE;
  1712                                     	sh4_x86.fpuen_checked = FALSE;
  1715                                         break;
  1716                                     case 0x1:
  1717                                         { /* LDC.L @Rm+, GBR */
  1718                                         uint32_t Rm = ((ir>>8)&0xF); 
  1719                                         load_reg( R_EAX, Rm );
  1720                                         precheck();
  1721                                         check_ralign32( R_EAX );
  1722                                         MOV_r32_r32( R_EAX, R_ECX );
  1723                                         ADD_imm8s_r32( 4, R_EAX );
  1724                                         store_reg( R_EAX, Rm );
  1725                                         MEM_READ_LONG( R_ECX, R_EAX );
  1726                                         store_spreg( R_EAX, R_GBR );
  1728                                         break;
  1729                                     case 0x2:
  1730                                         { /* LDC.L @Rm+, VBR */
  1731                                         uint32_t Rm = ((ir>>8)&0xF); 
  1732                                         precheck();
  1733                                         check_priv_no_precheck();
  1734                                         load_reg( R_EAX, Rm );
  1735                                         check_ralign32( R_EAX );
  1736                                         MOV_r32_r32( R_EAX, R_ECX );
  1737                                         ADD_imm8s_r32( 4, R_EAX );
  1738                                         store_reg( R_EAX, Rm );
  1739                                         MEM_READ_LONG( R_ECX, R_EAX );
  1740                                         store_spreg( R_EAX, R_VBR );
  1742                                         break;
  1743                                     case 0x3:
  1744                                         { /* LDC.L @Rm+, SSR */
  1745                                         uint32_t Rm = ((ir>>8)&0xF); 
  1746                                         precheck();
  1747                                         check_priv_no_precheck();
  1748                                         load_reg( R_EAX, Rm );
  1749                                         check_ralign32( R_EAX );
  1750                                         MOV_r32_r32( R_EAX, R_ECX );
  1751                                         ADD_imm8s_r32( 4, R_EAX );
  1752                                         store_reg( R_EAX, Rm );
  1753                                         MEM_READ_LONG( R_ECX, R_EAX );
  1754                                         store_spreg( R_EAX, R_SSR );
  1756                                         break;
  1757                                     case 0x4:
  1758                                         { /* LDC.L @Rm+, SPC */
  1759                                         uint32_t Rm = ((ir>>8)&0xF); 
  1760                                         precheck();
  1761                                         check_priv_no_precheck();
  1762                                         load_reg( R_EAX, Rm );
  1763                                         check_ralign32( R_EAX );
  1764                                         MOV_r32_r32( R_EAX, R_ECX );
  1765                                         ADD_imm8s_r32( 4, R_EAX );
  1766                                         store_reg( R_EAX, Rm );
  1767                                         MEM_READ_LONG( R_ECX, R_EAX );
  1768                                         store_spreg( R_EAX, R_SPC );
  1770                                         break;
  1771                                     default:
  1772                                         UNDEF();
  1773                                         break;
  1775                                 break;
  1776                             case 0x1:
  1777                                 { /* LDC.L @Rm+, Rn_BANK */
  1778                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1779                                 precheck();
  1780                                 check_priv_no_precheck();
  1781                                 load_reg( R_EAX, Rm );
  1782                                 check_ralign32( R_EAX );
  1783                                 MOV_r32_r32( R_EAX, R_ECX );
  1784                                 ADD_imm8s_r32( 4, R_EAX );
  1785                                 store_reg( R_EAX, Rm );
  1786                                 MEM_READ_LONG( R_ECX, R_EAX );
  1787                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  1789                                 break;
  1791                         break;
  1792                     case 0x8:
  1793                         switch( (ir&0xF0) >> 4 ) {
  1794                             case 0x0:
  1795                                 { /* SHLL2 Rn */
  1796                                 uint32_t Rn = ((ir>>8)&0xF); 
  1797                                 load_reg( R_EAX, Rn );
  1798                                 SHL_imm8_r32( 2, R_EAX );
  1799                                 store_reg( R_EAX, Rn );
  1801                                 break;
  1802                             case 0x1:
  1803                                 { /* SHLL8 Rn */
  1804                                 uint32_t Rn = ((ir>>8)&0xF); 
  1805                                 load_reg( R_EAX, Rn );
  1806                                 SHL_imm8_r32( 8, R_EAX );
  1807                                 store_reg( R_EAX, Rn );
  1809                                 break;
  1810                             case 0x2:
  1811                                 { /* SHLL16 Rn */
  1812                                 uint32_t Rn = ((ir>>8)&0xF); 
  1813                                 load_reg( R_EAX, Rn );
  1814                                 SHL_imm8_r32( 16, R_EAX );
  1815                                 store_reg( R_EAX, Rn );
  1817                                 break;
  1818                             default:
  1819                                 UNDEF();
  1820                                 break;
  1822                         break;
  1823                     case 0x9:
  1824                         switch( (ir&0xF0) >> 4 ) {
  1825                             case 0x0:
  1826                                 { /* SHLR2 Rn */
  1827                                 uint32_t Rn = ((ir>>8)&0xF); 
  1828                                 load_reg( R_EAX, Rn );
  1829                                 SHR_imm8_r32( 2, R_EAX );
  1830                                 store_reg( R_EAX, Rn );
  1832                                 break;
  1833                             case 0x1:
  1834                                 { /* SHLR8 Rn */
  1835                                 uint32_t Rn = ((ir>>8)&0xF); 
  1836                                 load_reg( R_EAX, Rn );
  1837                                 SHR_imm8_r32( 8, R_EAX );
  1838                                 store_reg( R_EAX, Rn );
  1840                                 break;
  1841                             case 0x2:
  1842                                 { /* SHLR16 Rn */
  1843                                 uint32_t Rn = ((ir>>8)&0xF); 
  1844                                 load_reg( R_EAX, Rn );
  1845                                 SHR_imm8_r32( 16, R_EAX );
  1846                                 store_reg( R_EAX, Rn );
  1848                                 break;
  1849                             default:
  1850                                 UNDEF();
  1851                                 break;
  1853                         break;
  1854                     case 0xA:
  1855                         switch( (ir&0xF0) >> 4 ) {
  1856                             case 0x0:
  1857                                 { /* LDS Rm, MACH */
  1858                                 uint32_t Rm = ((ir>>8)&0xF); 
  1859                                 load_reg( R_EAX, Rm );
  1860                                 store_spreg( R_EAX, R_MACH );
  1862                                 break;
  1863                             case 0x1:
  1864                                 { /* LDS Rm, MACL */
  1865                                 uint32_t Rm = ((ir>>8)&0xF); 
  1866                                 load_reg( R_EAX, Rm );
  1867                                 store_spreg( R_EAX, R_MACL );
  1869                                 break;
  1870                             case 0x2:
  1871                                 { /* LDS Rm, PR */
  1872                                 uint32_t Rm = ((ir>>8)&0xF); 
  1873                                 load_reg( R_EAX, Rm );
  1874                                 store_spreg( R_EAX, R_PR );
  1876                                 break;
  1877                             case 0x3:
  1878                                 { /* LDC Rm, SGR */
  1879                                 uint32_t Rm = ((ir>>8)&0xF); 
  1880                                 check_priv();
  1881                                 load_reg( R_EAX, Rm );
  1882                                 store_spreg( R_EAX, R_SGR );
  1884                                 break;
  1885                             case 0x5:
  1886                                 { /* LDS Rm, FPUL */
  1887                                 uint32_t Rm = ((ir>>8)&0xF); 
  1888                                 load_reg( R_EAX, Rm );
  1889                                 store_spreg( R_EAX, R_FPUL );
  1891                                 break;
  1892                             case 0x6:
  1893                                 { /* LDS Rm, FPSCR */
  1894                                 uint32_t Rm = ((ir>>8)&0xF); 
  1895                                 load_reg( R_EAX, Rm );
  1896                                 store_spreg( R_EAX, R_FPSCR );
  1897                                 update_fr_bank( R_EAX );
  1899                                 break;
  1900                             case 0xF:
  1901                                 { /* LDC Rm, DBR */
  1902                                 uint32_t Rm = ((ir>>8)&0xF); 
  1903                                 check_priv();
  1904                                 load_reg( R_EAX, Rm );
  1905                                 store_spreg( R_EAX, R_DBR );
  1907                                 break;
  1908                             default:
  1909                                 UNDEF();
  1910                                 break;
  1912                         break;
  1913                     case 0xB:
  1914                         switch( (ir&0xF0) >> 4 ) {
  1915                             case 0x0:
  1916                                 { /* JSR @Rn */
  1917                                 uint32_t Rn = ((ir>>8)&0xF); 
  1918                                 if( sh4_x86.in_delay_slot ) {
  1919                             	SLOTILLEGAL();
  1920                                 } else {
  1921                             	load_imm32( R_EAX, pc + 4 );
  1922                             	store_spreg( R_EAX, R_PR );
  1923                             	load_reg( R_ECX, Rn );
  1924                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1925                             	sh4_x86.in_delay_slot = TRUE;
  1926                             	sh4_x86_translate_instruction(pc+2);
  1927                             	exit_block_pcset(pc+2);
  1928                             	sh4_x86.branch_taken = TRUE;
  1929                             	return 4;
  1932                                 break;
  1933                             case 0x1:
  1934                                 { /* TAS.B @Rn */
  1935                                 uint32_t Rn = ((ir>>8)&0xF); 
  1936                                 load_reg( R_ECX, Rn );
  1937                                 MEM_READ_BYTE( R_ECX, R_EAX );
  1938                                 TEST_r8_r8( R_AL, R_AL );
  1939                                 SETE_t();
  1940                                 OR_imm8_r8( 0x80, R_AL );
  1941                                 load_reg( R_ECX, Rn );
  1942                                 MEM_WRITE_BYTE( R_ECX, R_EAX );
  1944                                 break;
  1945                             case 0x2:
  1946                                 { /* JMP @Rn */
  1947                                 uint32_t Rn = ((ir>>8)&0xF); 
  1948                                 if( sh4_x86.in_delay_slot ) {
  1949                             	SLOTILLEGAL();
  1950                                 } else {
  1951                             	load_reg( R_ECX, Rn );
  1952                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1953                             	sh4_x86.in_delay_slot = TRUE;
  1954                             	sh4_x86_translate_instruction(pc+2);
  1955                             	exit_block_pcset(pc+2);
  1956                             	sh4_x86.branch_taken = TRUE;
  1957                             	return 4;
  1960                                 break;
  1961                             default:
  1962                                 UNDEF();
  1963                                 break;
  1965                         break;
  1966                     case 0xC:
  1967                         { /* SHAD Rm, Rn */
  1968                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1969                         /* Annoyingly enough, not directly convertible */
  1970                         load_reg( R_EAX, Rn );
  1971                         load_reg( R_ECX, Rm );
  1972                         CMP_imm32_r32( 0, R_ECX );
  1973                         JGE_rel8(16, doshl);
  1975                         NEG_r32( R_ECX );      // 2
  1976                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1977                         JE_rel8( 4, emptysar);     // 2
  1978                         SAR_r32_CL( R_EAX );       // 2
  1979                         JMP_rel8(10, end);          // 2
  1981                         JMP_TARGET(emptysar);
  1982                         SAR_imm8_r32(31, R_EAX );  // 3
  1983                         JMP_rel8(5, end2);
  1985                         JMP_TARGET(doshl);
  1986                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1987                         SHL_r32_CL( R_EAX );       // 2
  1988                         JMP_TARGET(end);
  1989                         JMP_TARGET(end2);
  1990                         store_reg( R_EAX, Rn );
  1992                         break;
  1993                     case 0xD:
  1994                         { /* SHLD Rm, Rn */
  1995                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1996                         load_reg( R_EAX, Rn );
  1997                         load_reg( R_ECX, Rm );
  1998                         CMP_imm32_r32( 0, R_ECX );
  1999                         JGE_rel8(15, doshl);
  2001                         NEG_r32( R_ECX );      // 2
  2002                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2003                         JE_rel8( 4, emptyshr );
  2004                         SHR_r32_CL( R_EAX );       // 2
  2005                         JMP_rel8(9, end);          // 2
  2007                         JMP_TARGET(emptyshr);
  2008                         XOR_r32_r32( R_EAX, R_EAX );
  2009                         JMP_rel8(5, end2);
  2011                         JMP_TARGET(doshl);
  2012                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2013                         SHL_r32_CL( R_EAX );       // 2
  2014                         JMP_TARGET(end);
  2015                         JMP_TARGET(end2);
  2016                         store_reg( R_EAX, Rn );
  2018                         break;
  2019                     case 0xE:
  2020                         switch( (ir&0x80) >> 7 ) {
  2021                             case 0x0:
  2022                                 switch( (ir&0x70) >> 4 ) {
  2023                                     case 0x0:
  2024                                         { /* LDC Rm, SR */
  2025                                         uint32_t Rm = ((ir>>8)&0xF); 
  2026                                         if( sh4_x86.in_delay_slot ) {
  2027                                     	SLOTILLEGAL();
  2028                                         } else {
  2029                                     	check_priv();
  2030                                     	load_reg( R_EAX, Rm );
  2031                                     	call_func1( sh4_write_sr, R_EAX );
  2032                                     	sh4_x86.priv_checked = FALSE;
  2033                                     	sh4_x86.fpuen_checked = FALSE;
  2036                                         break;
  2037                                     case 0x1:
  2038                                         { /* LDC Rm, GBR */
  2039                                         uint32_t Rm = ((ir>>8)&0xF); 
  2040                                         load_reg( R_EAX, Rm );
  2041                                         store_spreg( R_EAX, R_GBR );
  2043                                         break;
  2044                                     case 0x2:
  2045                                         { /* LDC Rm, VBR */
  2046                                         uint32_t Rm = ((ir>>8)&0xF); 
  2047                                         check_priv();
  2048                                         load_reg( R_EAX, Rm );
  2049                                         store_spreg( R_EAX, R_VBR );
  2051                                         break;
  2052                                     case 0x3:
  2053                                         { /* LDC Rm, SSR */
  2054                                         uint32_t Rm = ((ir>>8)&0xF); 
  2055                                         check_priv();
  2056                                         load_reg( R_EAX, Rm );
  2057                                         store_spreg( R_EAX, R_SSR );
  2059                                         break;
  2060                                     case 0x4:
  2061                                         { /* LDC Rm, SPC */
  2062                                         uint32_t Rm = ((ir>>8)&0xF); 
  2063                                         check_priv();
  2064                                         load_reg( R_EAX, Rm );
  2065                                         store_spreg( R_EAX, R_SPC );
  2067                                         break;
  2068                                     default:
  2069                                         UNDEF();
  2070                                         break;
  2072                                 break;
  2073                             case 0x1:
  2074                                 { /* LDC Rm, Rn_BANK */
  2075                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  2076                                 check_priv();
  2077                                 load_reg( R_EAX, Rm );
  2078                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2080                                 break;
  2082                         break;
  2083                     case 0xF:
  2084                         { /* MAC.W @Rm+, @Rn+ */
  2085                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2086                         load_reg( R_ECX, Rm );
  2087                         precheck();
  2088                         check_ralign16( R_ECX );
  2089                         load_reg( R_ECX, Rn );
  2090                         check_ralign16( R_ECX );
  2091                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
  2092                         MEM_READ_WORD( R_ECX, R_EAX );
  2093                         PUSH_r32( R_EAX );
  2094                         load_reg( R_ECX, Rm );
  2095                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2096                         MEM_READ_WORD( R_ECX, R_EAX );
  2097                         POP_r32( R_ECX );
  2098                         IMUL_r32( R_ECX );
  2100                         load_spreg( R_ECX, R_S );
  2101                         TEST_r32_r32( R_ECX, R_ECX );
  2102                         JE_rel8( 47, nosat );
  2104                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2105                         JNO_rel8( 51, end );            // 2
  2106                         load_imm32( R_EDX, 1 );         // 5
  2107                         store_spreg( R_EDX, R_MACH );   // 6
  2108                         JS_rel8( 13, positive );        // 2
  2109                         load_imm32( R_EAX, 0x80000000 );// 5
  2110                         store_spreg( R_EAX, R_MACL );   // 6
  2111                         JMP_rel8( 25, end2 );           // 2
  2113                         JMP_TARGET(positive);
  2114                         load_imm32( R_EAX, 0x7FFFFFFF );// 5
  2115                         store_spreg( R_EAX, R_MACL );   // 6
  2116                         JMP_rel8( 12, end3);            // 2
  2118                         JMP_TARGET(nosat);
  2119                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2120                         ADC_r32_sh4r( R_EDX, R_MACH );  // 6
  2121                         JMP_TARGET(end);
  2122                         JMP_TARGET(end2);
  2123                         JMP_TARGET(end3);
  2125                         break;
  2127                 break;
  2128             case 0x5:
  2129                 { /* MOV.L @(disp, Rm), Rn */
  2130                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  2131                 load_reg( R_ECX, Rm );
  2132                 ADD_imm8s_r32( disp, R_ECX );
  2133                 precheck();
  2134                 check_ralign32( R_ECX );
  2135                 MEM_READ_LONG( R_ECX, R_EAX );
  2136                 store_reg( R_EAX, Rn );
  2138                 break;
  2139             case 0x6:
  2140                 switch( ir&0xF ) {
  2141                     case 0x0:
  2142                         { /* MOV.B @Rm, Rn */
  2143                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2144                         load_reg( R_ECX, Rm );
  2145                         MEM_READ_BYTE( R_ECX, R_EAX );
  2146                         store_reg( R_EAX, Rn );
  2148                         break;
  2149                     case 0x1:
  2150                         { /* MOV.W @Rm, Rn */
  2151                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2152                         load_reg( R_ECX, Rm );
  2153                         precheck();
  2154                         check_ralign16( R_ECX );
  2155                         MEM_READ_WORD( R_ECX, R_EAX );
  2156                         store_reg( R_EAX, Rn );
  2158                         break;
  2159                     case 0x2:
  2160                         { /* MOV.L @Rm, Rn */
  2161                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2162                         load_reg( R_ECX, Rm );
  2163                         precheck();
  2164                         check_ralign32( R_ECX );
  2165                         MEM_READ_LONG( R_ECX, R_EAX );
  2166                         store_reg( R_EAX, Rn );
  2168                         break;
  2169                     case 0x3:
  2170                         { /* MOV Rm, Rn */
  2171                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2172                         load_reg( R_EAX, Rm );
  2173                         store_reg( R_EAX, Rn );
  2175                         break;
  2176                     case 0x4:
  2177                         { /* MOV.B @Rm+, Rn */
  2178                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2179                         load_reg( R_ECX, Rm );
  2180                         MOV_r32_r32( R_ECX, R_EAX );
  2181                         ADD_imm8s_r32( 1, R_EAX );
  2182                         store_reg( R_EAX, Rm );
  2183                         MEM_READ_BYTE( R_ECX, R_EAX );
  2184                         store_reg( R_EAX, Rn );
  2186                         break;
  2187                     case 0x5:
  2188                         { /* MOV.W @Rm+, Rn */
  2189                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2190                         load_reg( R_EAX, Rm );
  2191                         precheck();
  2192                         check_ralign16( R_EAX );
  2193                         MOV_r32_r32( R_EAX, R_ECX );
  2194                         ADD_imm8s_r32( 2, R_EAX );
  2195                         store_reg( R_EAX, Rm );
  2196                         MEM_READ_WORD( R_ECX, R_EAX );
  2197                         store_reg( R_EAX, Rn );
  2199                         break;
  2200                     case 0x6:
  2201                         { /* MOV.L @Rm+, Rn */
  2202                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2203                         load_reg( R_EAX, Rm );
  2204                         precheck();
  2205                         check_ralign32( R_EAX );
  2206                         MOV_r32_r32( R_EAX, R_ECX );
  2207                         ADD_imm8s_r32( 4, R_EAX );
  2208                         store_reg( R_EAX, Rm );
  2209                         MEM_READ_LONG( R_ECX, R_EAX );
  2210                         store_reg( R_EAX, Rn );
  2212                         break;
  2213                     case 0x7:
  2214                         { /* NOT Rm, Rn */
  2215                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2216                         load_reg( R_EAX, Rm );
  2217                         NOT_r32( R_EAX );
  2218                         store_reg( R_EAX, Rn );
  2220                         break;
  2221                     case 0x8:
  2222                         { /* SWAP.B Rm, Rn */
  2223                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2224                         load_reg( R_EAX, Rm );
  2225                         XCHG_r8_r8( R_AL, R_AH );
  2226                         store_reg( R_EAX, Rn );
  2228                         break;
  2229                     case 0x9:
  2230                         { /* SWAP.W Rm, Rn */
  2231                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2232                         load_reg( R_EAX, Rm );
  2233                         MOV_r32_r32( R_EAX, R_ECX );
  2234                         SHL_imm8_r32( 16, R_ECX );
  2235                         SHR_imm8_r32( 16, R_EAX );
  2236                         OR_r32_r32( R_EAX, R_ECX );
  2237                         store_reg( R_ECX, Rn );
  2239                         break;
  2240                     case 0xA:
  2241                         { /* NEGC Rm, Rn */
  2242                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2243                         load_reg( R_EAX, Rm );
  2244                         XOR_r32_r32( R_ECX, R_ECX );
  2245                         LDC_t();
  2246                         SBB_r32_r32( R_EAX, R_ECX );
  2247                         store_reg( R_ECX, Rn );
  2248                         SETC_t();
  2250                         break;
  2251                     case 0xB:
  2252                         { /* NEG Rm, Rn */
  2253                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2254                         load_reg( R_EAX, Rm );
  2255                         NEG_r32( R_EAX );
  2256                         store_reg( R_EAX, Rn );
  2258                         break;
  2259                     case 0xC:
  2260                         { /* EXTU.B Rm, Rn */
  2261                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2262                         load_reg( R_EAX, Rm );
  2263                         MOVZX_r8_r32( R_EAX, R_EAX );
  2264                         store_reg( R_EAX, Rn );
  2266                         break;
  2267                     case 0xD:
  2268                         { /* EXTU.W Rm, Rn */
  2269                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2270                         load_reg( R_EAX, Rm );
  2271                         MOVZX_r16_r32( R_EAX, R_EAX );
  2272                         store_reg( R_EAX, Rn );
  2274                         break;
  2275                     case 0xE:
  2276                         { /* EXTS.B Rm, Rn */
  2277                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2278                         load_reg( R_EAX, Rm );
  2279                         MOVSX_r8_r32( R_EAX, R_EAX );
  2280                         store_reg( R_EAX, Rn );
  2282                         break;
  2283                     case 0xF:
  2284                         { /* EXTS.W Rm, Rn */
  2285                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2286                         load_reg( R_EAX, Rm );
  2287                         MOVSX_r16_r32( R_EAX, R_EAX );
  2288                         store_reg( R_EAX, Rn );
  2290                         break;
  2292                 break;
  2293             case 0x7:
  2294                 { /* ADD #imm, Rn */
  2295                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2296                 load_reg( R_EAX, Rn );
  2297                 ADD_imm8s_r32( imm, R_EAX );
  2298                 store_reg( R_EAX, Rn );
  2300                 break;
  2301             case 0x8:
  2302                 switch( (ir&0xF00) >> 8 ) {
  2303                     case 0x0:
  2304                         { /* MOV.B R0, @(disp, Rn) */
  2305                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2306                         load_reg( R_EAX, 0 );
  2307                         load_reg( R_ECX, Rn );
  2308                         ADD_imm32_r32( disp, R_ECX );
  2309                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2311                         break;
  2312                     case 0x1:
  2313                         { /* MOV.W R0, @(disp, Rn) */
  2314                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2315                         load_reg( R_ECX, Rn );
  2316                         load_reg( R_EAX, 0 );
  2317                         ADD_imm32_r32( disp, R_ECX );
  2318                         precheck();
  2319                         check_walign16( R_ECX );
  2320                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2322                         break;
  2323                     case 0x4:
  2324                         { /* MOV.B @(disp, Rm), R0 */
  2325                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2326                         load_reg( R_ECX, Rm );
  2327                         ADD_imm32_r32( disp, R_ECX );
  2328                         MEM_READ_BYTE( R_ECX, R_EAX );
  2329                         store_reg( R_EAX, 0 );
  2331                         break;
  2332                     case 0x5:
  2333                         { /* MOV.W @(disp, Rm), R0 */
  2334                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2335                         load_reg( R_ECX, Rm );
  2336                         ADD_imm32_r32( disp, R_ECX );
  2337                         precheck();
  2338                         check_ralign16( R_ECX );
  2339                         MEM_READ_WORD( R_ECX, R_EAX );
  2340                         store_reg( R_EAX, 0 );
  2342                         break;
  2343                     case 0x8:
  2344                         { /* CMP/EQ #imm, R0 */
  2345                         int32_t imm = SIGNEXT8(ir&0xFF); 
  2346                         load_reg( R_EAX, 0 );
  2347                         CMP_imm8s_r32(imm, R_EAX);
  2348                         SETE_t();
  2350                         break;
  2351                     case 0x9:
  2352                         { /* BT disp */
  2353                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2354                         if( sh4_x86.in_delay_slot ) {
  2355                     	SLOTILLEGAL();
  2356                         } else {
  2357                     	CMP_imm8s_sh4r( 0, R_T );
  2358                     	JE_rel8( 29, nottaken );
  2359                     	exit_block( disp + pc + 4, pc+2 );
  2360                     	JMP_TARGET(nottaken);
  2361                     	return 2;
  2364                         break;
  2365                     case 0xB:
  2366                         { /* BF disp */
  2367                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2368                         if( sh4_x86.in_delay_slot ) {
  2369                     	SLOTILLEGAL();
  2370                         } else {
  2371                     	CMP_imm8s_sh4r( 0, R_T );
  2372                     	JNE_rel8( 29, nottaken );
  2373                     	exit_block( disp + pc + 4, pc+2 );
  2374                     	JMP_TARGET(nottaken);
  2375                     	return 2;
  2378                         break;
  2379                     case 0xD:
  2380                         { /* BT/S disp */
  2381                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2382                         if( sh4_x86.in_delay_slot ) {
  2383                     	SLOTILLEGAL();
  2384                         } else {
  2385                     	sh4_x86.in_delay_slot = TRUE;
  2386                     	CMP_imm8s_sh4r( 0, R_T );
  2387                     	OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
  2388                     	sh4_x86_translate_instruction(pc+2);
  2389                     	exit_block( disp + pc + 4, pc+4 );
  2390                     	// not taken
  2391                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2392                     	sh4_x86_translate_instruction(pc+2);
  2393                     	return 4;
  2396                         break;
  2397                     case 0xF:
  2398                         { /* BF/S disp */
  2399                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2400                         if( sh4_x86.in_delay_slot ) {
  2401                     	SLOTILLEGAL();
  2402                         } else {
  2403                     	sh4_x86.in_delay_slot = TRUE;
  2404                     	CMP_imm8s_sh4r( 0, R_T );
  2405                     	OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
  2406                     	sh4_x86_translate_instruction(pc+2);
  2407                     	exit_block( disp + pc + 4, pc+4 );
  2408                     	// not taken
  2409                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2410                     	sh4_x86_translate_instruction(pc+2);
  2411                     	return 4;
  2414                         break;
  2415                     default:
  2416                         UNDEF();
  2417                         break;
  2419                 break;
  2420             case 0x9:
  2421                 { /* MOV.W @(disp, PC), Rn */
  2422                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  2423                 if( sh4_x86.in_delay_slot ) {
  2424             	SLOTILLEGAL();
  2425                 } else {
  2426             	load_imm32( R_ECX, pc + disp + 4 );
  2427             	MEM_READ_WORD( R_ECX, R_EAX );
  2428             	store_reg( R_EAX, Rn );
  2431                 break;
  2432             case 0xA:
  2433                 { /* BRA disp */
  2434                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2435                 if( sh4_x86.in_delay_slot ) {
  2436             	SLOTILLEGAL();
  2437                 } else {
  2438             	sh4_x86.in_delay_slot = TRUE;
  2439             	sh4_x86_translate_instruction( pc + 2 );
  2440             	exit_block( disp + pc + 4, pc+4 );
  2441             	sh4_x86.branch_taken = TRUE;
  2442             	return 4;
  2445                 break;
  2446             case 0xB:
  2447                 { /* BSR disp */
  2448                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2449                 if( sh4_x86.in_delay_slot ) {
  2450             	SLOTILLEGAL();
  2451                 } else {
  2452             	load_imm32( R_EAX, pc + 4 );
  2453             	store_spreg( R_EAX, R_PR );
  2454             	sh4_x86.in_delay_slot = TRUE;
  2455             	sh4_x86_translate_instruction( pc + 2 );
  2456             	exit_block( disp + pc + 4, pc+4 );
  2457             	sh4_x86.branch_taken = TRUE;
  2458             	return 4;
  2461                 break;
  2462             case 0xC:
  2463                 switch( (ir&0xF00) >> 8 ) {
  2464                     case 0x0:
  2465                         { /* MOV.B R0, @(disp, GBR) */
  2466                         uint32_t disp = (ir&0xFF); 
  2467                         load_reg( R_EAX, 0 );
  2468                         load_spreg( R_ECX, R_GBR );
  2469                         ADD_imm32_r32( disp, R_ECX );
  2470                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2472                         break;
  2473                     case 0x1:
  2474                         { /* MOV.W R0, @(disp, GBR) */
  2475                         uint32_t disp = (ir&0xFF)<<1; 
  2476                         load_spreg( R_ECX, R_GBR );
  2477                         load_reg( R_EAX, 0 );
  2478                         ADD_imm32_r32( disp, R_ECX );
  2479                         precheck();
  2480                         check_walign16( R_ECX );
  2481                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2483                         break;
  2484                     case 0x2:
  2485                         { /* MOV.L R0, @(disp, GBR) */
  2486                         uint32_t disp = (ir&0xFF)<<2; 
  2487                         load_spreg( R_ECX, R_GBR );
  2488                         load_reg( R_EAX, 0 );
  2489                         ADD_imm32_r32( disp, R_ECX );
  2490                         precheck();
  2491                         check_walign32( R_ECX );
  2492                         MEM_WRITE_LONG( R_ECX, R_EAX );
  2494                         break;
  2495                     case 0x3:
  2496                         { /* TRAPA #imm */
  2497                         uint32_t imm = (ir&0xFF); 
  2498                         if( sh4_x86.in_delay_slot ) {
  2499                     	SLOTILLEGAL();
  2500                         } else {
  2501                     	PUSH_imm32( imm );
  2502                     	call_func0( sh4_raise_trap );
  2503                     	ADD_imm8s_r32( 4, R_ESP );
  2504                     	exit_block_pcset(pc);
  2505                     	sh4_x86.branch_taken = TRUE;
  2506                     	return 2;
  2509                         break;
  2510                     case 0x4:
  2511                         { /* MOV.B @(disp, GBR), R0 */
  2512                         uint32_t disp = (ir&0xFF); 
  2513                         load_spreg( R_ECX, R_GBR );
  2514                         ADD_imm32_r32( disp, R_ECX );
  2515                         MEM_READ_BYTE( R_ECX, R_EAX );
  2516                         store_reg( R_EAX, 0 );
  2518                         break;
  2519                     case 0x5:
  2520                         { /* MOV.W @(disp, GBR), R0 */
  2521                         uint32_t disp = (ir&0xFF)<<1; 
  2522                         load_spreg( R_ECX, R_GBR );
  2523                         ADD_imm32_r32( disp, R_ECX );
  2524                         precheck();
  2525                         check_ralign16( R_ECX );
  2526                         MEM_READ_WORD( R_ECX, R_EAX );
  2527                         store_reg( R_EAX, 0 );
  2529                         break;
  2530                     case 0x6:
  2531                         { /* MOV.L @(disp, GBR), R0 */
  2532                         uint32_t disp = (ir&0xFF)<<2; 
  2533                         load_spreg( R_ECX, R_GBR );
  2534                         ADD_imm32_r32( disp, R_ECX );
  2535                         precheck();
  2536                         check_ralign32( R_ECX );
  2537                         MEM_READ_LONG( R_ECX, R_EAX );
  2538                         store_reg( R_EAX, 0 );
  2540                         break;
  2541                     case 0x7:
  2542                         { /* MOVA @(disp, PC), R0 */
  2543                         uint32_t disp = (ir&0xFF)<<2; 
  2544                         if( sh4_x86.in_delay_slot ) {
  2545                     	SLOTILLEGAL();
  2546                         } else {
  2547                     	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
  2548                     	store_reg( R_ECX, 0 );
  2551                         break;
  2552                     case 0x8:
  2553                         { /* TST #imm, R0 */
  2554                         uint32_t imm = (ir&0xFF); 
  2555                         load_reg( R_EAX, 0 );
  2556                         TEST_imm32_r32( imm, R_EAX );
  2557                         SETE_t();
  2559                         break;
  2560                     case 0x9:
  2561                         { /* AND #imm, R0 */
  2562                         uint32_t imm = (ir&0xFF); 
  2563                         load_reg( R_EAX, 0 );
  2564                         AND_imm32_r32(imm, R_EAX); 
  2565                         store_reg( R_EAX, 0 );
  2567                         break;
  2568                     case 0xA:
  2569                         { /* XOR #imm, R0 */
  2570                         uint32_t imm = (ir&0xFF); 
  2571                         load_reg( R_EAX, 0 );
  2572                         XOR_imm32_r32( imm, R_EAX );
  2573                         store_reg( R_EAX, 0 );
  2575                         break;
  2576                     case 0xB:
  2577                         { /* OR #imm, R0 */
  2578                         uint32_t imm = (ir&0xFF); 
  2579                         load_reg( R_EAX, 0 );
  2580                         OR_imm32_r32(imm, R_EAX);
  2581                         store_reg( R_EAX, 0 );
  2583                         break;
  2584                     case 0xC:
  2585                         { /* TST.B #imm, @(R0, GBR) */
  2586                         uint32_t imm = (ir&0xFF); 
  2587                         load_reg( R_EAX, 0);
  2588                         load_reg( R_ECX, R_GBR);
  2589                         ADD_r32_r32( R_EAX, R_ECX );
  2590                         MEM_READ_BYTE( R_ECX, R_EAX );
  2591                         TEST_imm8_r8( imm, R_AL );
  2592                         SETE_t();
  2594                         break;
  2595                     case 0xD:
  2596                         { /* AND.B #imm, @(R0, GBR) */
  2597                         uint32_t imm = (ir&0xFF); 
  2598                         load_reg( R_EAX, 0 );
  2599                         load_spreg( R_ECX, R_GBR );
  2600                         ADD_r32_r32( R_EAX, R_ECX );
  2601                         PUSH_r32(R_ECX);
  2602                         call_func0(sh4_read_byte);
  2603                         POP_r32(R_ECX);
  2604                         AND_imm32_r32(imm, R_EAX );
  2605                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2607                         break;
  2608                     case 0xE:
  2609                         { /* XOR.B #imm, @(R0, GBR) */
  2610                         uint32_t imm = (ir&0xFF); 
  2611                         load_reg( R_EAX, 0 );
  2612                         load_spreg( R_ECX, R_GBR );
  2613                         ADD_r32_r32( R_EAX, R_ECX );
  2614                         PUSH_r32(R_ECX);
  2615                         call_func0(sh4_read_byte);
  2616                         POP_r32(R_ECX);
  2617                         XOR_imm32_r32( imm, R_EAX );
  2618                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2620                         break;
  2621                     case 0xF:
  2622                         { /* OR.B #imm, @(R0, GBR) */
  2623                         uint32_t imm = (ir&0xFF); 
  2624                         load_reg( R_EAX, 0 );
  2625                         load_spreg( R_ECX, R_GBR );
  2626                         ADD_r32_r32( R_EAX, R_ECX );
  2627                         PUSH_r32(R_ECX);
  2628                         call_func0(sh4_read_byte);
  2629                         POP_r32(R_ECX);
  2630                         OR_imm32_r32(imm, R_EAX );
  2631                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2633                         break;
  2635                 break;
  2636             case 0xD:
  2637                 { /* MOV.L @(disp, PC), Rn */
  2638                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2639                 if( sh4_x86.in_delay_slot ) {
  2640             	SLOTILLEGAL();
  2641                 } else {
  2642             	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
  2643             	char *ptr = mem_get_region(target);
  2644             	if( ptr != NULL ) {
  2645             	    MOV_moff32_EAX( (uint32_t)ptr );
  2646             	} else {
  2647             	    load_imm32( R_ECX, target );
  2648             	    MEM_READ_LONG( R_ECX, R_EAX );
  2650             	store_reg( R_EAX, Rn );
  2653                 break;
  2654             case 0xE:
  2655                 { /* MOV #imm, Rn */
  2656                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2657                 load_imm32( R_EAX, imm );
  2658                 store_reg( R_EAX, Rn );
  2660                 break;
  2661             case 0xF:
  2662                 switch( ir&0xF ) {
  2663                     case 0x0:
  2664                         { /* FADD FRm, FRn */
  2665                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2666                         check_fpuen();
  2667                         load_spreg( R_ECX, R_FPSCR );
  2668                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2669                         load_fr_bank( R_EDX );
  2670                         JNE_rel8(13,doubleprec);
  2671                         push_fr(R_EDX, FRm);
  2672                         push_fr(R_EDX, FRn);
  2673                         FADDP_st(1);
  2674                         pop_fr(R_EDX, FRn);
  2675                         JMP_rel8(11,end);
  2676                         JMP_TARGET(doubleprec);
  2677                         push_dr(R_EDX, FRm);
  2678                         push_dr(R_EDX, FRn);
  2679                         FADDP_st(1);
  2680                         pop_dr(R_EDX, FRn);
  2681                         JMP_TARGET(end);
  2683                         break;
  2684                     case 0x1:
  2685                         { /* FSUB FRm, FRn */
  2686                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2687                         check_fpuen();
  2688                         load_spreg( R_ECX, R_FPSCR );
  2689                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2690                         load_fr_bank( R_EDX );
  2691                         JNE_rel8(13, doubleprec);
  2692                         push_fr(R_EDX, FRn);
  2693                         push_fr(R_EDX, FRm);
  2694                         FSUBP_st(1);
  2695                         pop_fr(R_EDX, FRn);
  2696                         JMP_rel8(11, end);
  2697                         JMP_TARGET(doubleprec);
  2698                         push_dr(R_EDX, FRn);
  2699                         push_dr(R_EDX, FRm);
  2700                         FSUBP_st(1);
  2701                         pop_dr(R_EDX, FRn);
  2702                         JMP_TARGET(end);
  2704                         break;
  2705                     case 0x2:
  2706                         { /* FMUL FRm, FRn */
  2707                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2708                         check_fpuen();
  2709                         load_spreg( R_ECX, R_FPSCR );
  2710                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2711                         load_fr_bank( R_EDX );
  2712                         JNE_rel8(13, doubleprec);
  2713                         push_fr(R_EDX, FRm);
  2714                         push_fr(R_EDX, FRn);
  2715                         FMULP_st(1);
  2716                         pop_fr(R_EDX, FRn);
  2717                         JMP_rel8(11, end);
  2718                         JMP_TARGET(doubleprec);
  2719                         push_dr(R_EDX, FRm);
  2720                         push_dr(R_EDX, FRn);
  2721                         FMULP_st(1);
  2722                         pop_dr(R_EDX, FRn);
  2723                         JMP_TARGET(end);
  2725                         break;
  2726                     case 0x3:
  2727                         { /* FDIV FRm, FRn */
  2728                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2729                         check_fpuen();
  2730                         load_spreg( R_ECX, R_FPSCR );
  2731                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2732                         load_fr_bank( R_EDX );
  2733                         JNE_rel8(13, doubleprec);
  2734                         push_fr(R_EDX, FRn);
  2735                         push_fr(R_EDX, FRm);
  2736                         FDIVP_st(1);
  2737                         pop_fr(R_EDX, FRn);
  2738                         JMP_rel8(11, end);
  2739                         JMP_TARGET(doubleprec);
  2740                         push_dr(R_EDX, FRn);
  2741                         push_dr(R_EDX, FRm);
  2742                         FDIVP_st(1);
  2743                         pop_dr(R_EDX, FRn);
  2744                         JMP_TARGET(end);
  2746                         break;
  2747                     case 0x4:
  2748                         { /* FCMP/EQ FRm, FRn */
  2749                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2750                         check_fpuen();
  2751                         load_spreg( R_ECX, R_FPSCR );
  2752                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2753                         load_fr_bank( R_EDX );
  2754                         JNE_rel8(8, doubleprec);
  2755                         push_fr(R_EDX, FRm);
  2756                         push_fr(R_EDX, FRn);
  2757                         JMP_rel8(6, end);
  2758                         JMP_TARGET(doubleprec);
  2759                         push_dr(R_EDX, FRm);
  2760                         push_dr(R_EDX, FRn);
  2761                         JMP_TARGET(end);
  2762                         FCOMIP_st(1);
  2763                         SETE_t();
  2764                         FPOP_st();
  2766                         break;
  2767                     case 0x5:
  2768                         { /* FCMP/GT FRm, FRn */
  2769                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2770                         check_fpuen();
  2771                         load_spreg( R_ECX, R_FPSCR );
  2772                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2773                         load_fr_bank( R_EDX );
  2774                         JNE_rel8(8, doubleprec);
  2775                         push_fr(R_EDX, FRm);
  2776                         push_fr(R_EDX, FRn);
  2777                         JMP_rel8(6, end);
  2778                         JMP_TARGET(doubleprec);
  2779                         push_dr(R_EDX, FRm);
  2780                         push_dr(R_EDX, FRn);
  2781                         JMP_TARGET(end);
  2782                         FCOMIP_st(1);
  2783                         SETA_t();
  2784                         FPOP_st();
  2786                         break;
  2787                     case 0x6:
  2788                         { /* FMOV @(R0, Rm), FRn */
  2789                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2790                         precheck();
  2791                         check_fpuen_no_precheck();
  2792                         load_reg( R_ECX, Rm );
  2793                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
  2794                         check_ralign32( R_ECX );
  2795                         load_spreg( R_EDX, R_FPSCR );
  2796                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2797                         JNE_rel8(19, doublesize);
  2798                         MEM_READ_LONG( R_ECX, R_EAX );
  2799                         load_fr_bank( R_EDX );
  2800                         store_fr( R_EDX, R_EAX, FRn );
  2801                         if( FRn&1 ) {
  2802                     	JMP_rel8(48, end);
  2803                     	JMP_TARGET(doublesize);
  2804                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2805                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2806                     	load_xf_bank( R_EDX );
  2807                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2808                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2809                     	JMP_TARGET(end);
  2810                         } else {
  2811                     	JMP_rel8(36, end);
  2812                     	JMP_TARGET(doublesize);
  2813                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2814                     	load_fr_bank( R_EDX );
  2815                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2816                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2817                     	JMP_TARGET(end);
  2820                         break;
  2821                     case 0x7:
  2822                         { /* FMOV FRm, @(R0, Rn) */
  2823                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2824                         precheck();
  2825                         check_fpuen_no_precheck();
  2826                         load_reg( R_ECX, Rn );
  2827                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
  2828                         check_walign32( R_ECX );
  2829                         load_spreg( R_EDX, R_FPSCR );
  2830                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2831                         JNE_rel8(20, doublesize);
  2832                         load_fr_bank( R_EDX );
  2833                         load_fr( R_EDX, R_EAX, FRm );
  2834                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2835                         if( FRm&1 ) {
  2836                     	JMP_rel8( 48, end );
  2837                     	JMP_TARGET(doublesize);
  2838                     	load_xf_bank( R_EDX );
  2839                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2840                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2841                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2842                     	JMP_TARGET(end);
  2843                         } else {
  2844                     	JMP_rel8( 39, end );
  2845                     	JMP_TARGET(doublesize);
  2846                     	load_fr_bank( R_EDX );
  2847                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2848                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2849                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2850                     	JMP_TARGET(end);
  2853                         break;
  2854                     case 0x8:
  2855                         { /* FMOV @Rm, FRn */
  2856                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2857                         precheck();
  2858                         check_fpuen_no_precheck();
  2859                         load_reg( R_ECX, Rm );
  2860                         check_ralign32( R_ECX );
  2861                         load_spreg( R_EDX, R_FPSCR );
  2862                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2863                         JNE_rel8(19, doublesize);
  2864                         MEM_READ_LONG( R_ECX, R_EAX );
  2865                         load_fr_bank( R_EDX );
  2866                         store_fr( R_EDX, R_EAX, FRn );
  2867                         if( FRn&1 ) {
  2868                     	JMP_rel8(48, end);
  2869                     	JMP_TARGET(doublesize);
  2870                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2871                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2872                     	load_xf_bank( R_EDX );
  2873                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2874                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2875                     	JMP_TARGET(end);
  2876                         } else {
  2877                     	JMP_rel8(36, end);
  2878                     	JMP_TARGET(doublesize);
  2879                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2880                     	load_fr_bank( R_EDX );
  2881                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2882                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2883                     	JMP_TARGET(end);
  2886                         break;
  2887                     case 0x9:
  2888                         { /* FMOV @Rm+, FRn */
  2889                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2890                         precheck();
  2891                         check_fpuen_no_precheck();
  2892                         load_reg( R_ECX, Rm );
  2893                         check_ralign32( R_ECX );
  2894                         MOV_r32_r32( R_ECX, R_EAX );
  2895                         load_spreg( R_EDX, R_FPSCR );
  2896                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2897                         JNE_rel8(25, doublesize);
  2898                         ADD_imm8s_r32( 4, R_EAX );
  2899                         store_reg( R_EAX, Rm );
  2900                         MEM_READ_LONG( R_ECX, R_EAX );
  2901                         load_fr_bank( R_EDX );
  2902                         store_fr( R_EDX, R_EAX, FRn );
  2903                         if( FRn&1 ) {
  2904                     	JMP_rel8(54, end);
  2905                     	JMP_TARGET(doublesize);
  2906                     	ADD_imm8s_r32( 8, R_EAX );
  2907                     	store_reg(R_EAX, Rm);
  2908                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2909                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2910                     	load_xf_bank( R_EDX );
  2911                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2912                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2913                     	JMP_TARGET(end);
  2914                         } else {
  2915                     	JMP_rel8(42, end);
  2916                     	ADD_imm8s_r32( 8, R_EAX );
  2917                     	store_reg(R_EAX, Rm);
  2918                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2919                     	load_fr_bank( R_EDX );
  2920                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2921                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2922                     	JMP_TARGET(end);
  2925                         break;
  2926                     case 0xA:
  2927                         { /* FMOV FRm, @Rn */
  2928                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2929                         precheck();
  2930                         check_fpuen_no_precheck();
  2931                         load_reg( R_ECX, Rn );
  2932                         check_walign32( R_ECX );
  2933                         load_spreg( R_EDX, R_FPSCR );
  2934                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2935                         JNE_rel8(20, doublesize);
  2936                         load_fr_bank( R_EDX );
  2937                         load_fr( R_EDX, R_EAX, FRm );
  2938                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2939                         if( FRm&1 ) {
  2940                     	JMP_rel8( 48, end );
  2941                     	JMP_TARGET(doublesize);
  2942                     	load_xf_bank( R_EDX );
  2943                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2944                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2945                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2946                     	JMP_TARGET(end);
  2947                         } else {
  2948                     	JMP_rel8( 39, end );
  2949                     	JMP_TARGET(doublesize);
  2950                     	load_fr_bank( R_EDX );
  2951                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2952                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2953                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2954                     	JMP_TARGET(end);
  2957                         break;
  2958                     case 0xB:
  2959                         { /* FMOV FRm, @-Rn */
  2960                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2961                         precheck();
  2962                         check_fpuen_no_precheck();
  2963                         load_reg( R_ECX, Rn );
  2964                         check_walign32( R_ECX );
  2965                         load_spreg( R_EDX, R_FPSCR );
  2966                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2967                         JNE_rel8(26, doublesize);
  2968                         load_fr_bank( R_EDX );
  2969                         load_fr( R_EDX, R_EAX, FRm );
  2970                         ADD_imm8s_r32(-4,R_ECX);
  2971                         store_reg( R_ECX, Rn );
  2972                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2973                         if( FRm&1 ) {
  2974                     	JMP_rel8( 54, end );
  2975                     	JMP_TARGET(doublesize);
  2976                     	load_xf_bank( R_EDX );
  2977                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2978                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2979                     	ADD_imm8s_r32(-8,R_ECX);
  2980                     	store_reg( R_ECX, Rn );
  2981                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2982                     	JMP_TARGET(end);
  2983                         } else {
  2984                     	JMP_rel8( 45, end );
  2985                     	JMP_TARGET(doublesize);
  2986                     	load_fr_bank( R_EDX );
  2987                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2988                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2989                     	ADD_imm8s_r32(-8,R_ECX);
  2990                     	store_reg( R_ECX, Rn );
  2991                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2992                     	JMP_TARGET(end);
  2995                         break;
  2996                     case 0xC:
  2997                         { /* FMOV FRm, FRn */
  2998                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2999                         /* As horrible as this looks, it's actually covering 5 separate cases:
  3000                          * 1. 32-bit fr-to-fr (PR=0)
  3001                          * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
  3002                          * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
  3003                          * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
  3004                          * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
  3005                          */
  3006                         check_fpuen();
  3007                         load_spreg( R_ECX, R_FPSCR );
  3008                         load_fr_bank( R_EDX );
  3009                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  3010                         JNE_rel8(8, doublesize);
  3011                         load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
  3012                         store_fr( R_EDX, R_EAX, FRn );
  3013                         if( FRm&1 ) {
  3014                     	JMP_rel8(24, end);
  3015                     	JMP_TARGET(doublesize);
  3016                     	load_xf_bank( R_ECX ); 
  3017                     	load_fr( R_ECX, R_EAX, FRm-1 );
  3018                     	if( FRn&1 ) {
  3019                     	    load_fr( R_ECX, R_EDX, FRm );
  3020                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  3021                     	    store_fr( R_ECX, R_EDX, FRn );
  3022                     	} else /* FRn&1 == 0 */ {
  3023                     	    load_fr( R_ECX, R_ECX, FRm );
  3024                     	    store_fr( R_EDX, R_EAX, FRn );
  3025                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  3027                     	JMP_TARGET(end);
  3028                         } else /* FRm&1 == 0 */ {
  3029                     	if( FRn&1 ) {
  3030                     	    JMP_rel8(24, end);
  3031                     	    load_xf_bank( R_ECX );
  3032                     	    load_fr( R_EDX, R_EAX, FRm );
  3033                     	    load_fr( R_EDX, R_EDX, FRm+1 );
  3034                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  3035                     	    store_fr( R_ECX, R_EDX, FRn );
  3036                     	    JMP_TARGET(end);
  3037                     	} else /* FRn&1 == 0 */ {
  3038                     	    JMP_rel8(12, end);
  3039                     	    load_fr( R_EDX, R_EAX, FRm );
  3040                     	    load_fr( R_EDX, R_ECX, FRm+1 );
  3041                     	    store_fr( R_EDX, R_EAX, FRn );
  3042                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  3043                     	    JMP_TARGET(end);
  3047                         break;
  3048                     case 0xD:
  3049                         switch( (ir&0xF0) >> 4 ) {
  3050                             case 0x0:
  3051                                 { /* FSTS FPUL, FRn */
  3052                                 uint32_t FRn = ((ir>>8)&0xF); 
  3053                                 check_fpuen();
  3054                                 load_fr_bank( R_ECX );
  3055                                 load_spreg( R_EAX, R_FPUL );
  3056                                 store_fr( R_ECX, R_EAX, FRn );
  3058                                 break;
  3059                             case 0x1:
  3060                                 { /* FLDS FRm, FPUL */
  3061                                 uint32_t FRm = ((ir>>8)&0xF); 
  3062                                 check_fpuen();
  3063                                 load_fr_bank( R_ECX );
  3064                                 load_fr( R_ECX, R_EAX, FRm );
  3065                                 store_spreg( R_EAX, R_FPUL );
  3067                                 break;
  3068                             case 0x2:
  3069                                 { /* FLOAT FPUL, FRn */
  3070                                 uint32_t FRn = ((ir>>8)&0xF); 
  3071                                 check_fpuen();
  3072                                 load_spreg( R_ECX, R_FPSCR );
  3073                                 load_spreg(R_EDX, REG_OFFSET(fr_bank));
  3074                                 FILD_sh4r(R_FPUL);
  3075                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3076                                 JNE_rel8(5, doubleprec);
  3077                                 pop_fr( R_EDX, FRn );
  3078                                 JMP_rel8(3, end);
  3079                                 JMP_TARGET(doubleprec);
  3080                                 pop_dr( R_EDX, FRn );
  3081                                 JMP_TARGET(end);
  3083                                 break;
  3084                             case 0x3:
  3085                                 { /* FTRC FRm, FPUL */
  3086                                 uint32_t FRm = ((ir>>8)&0xF); 
  3087                                 check_fpuen();
  3088                                 load_spreg( R_ECX, R_FPSCR );
  3089                                 load_fr_bank( R_EDX );
  3090                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3091                                 JNE_rel8(5, doubleprec);
  3092                                 push_fr( R_EDX, FRm );
  3093                                 JMP_rel8(3, doop);
  3094                                 JMP_TARGET(doubleprec);
  3095                                 push_dr( R_EDX, FRm );
  3096                                 JMP_TARGET( doop );
  3097                                 load_imm32( R_ECX, (uint32_t)&max_int );
  3098                                 FILD_r32ind( R_ECX );
  3099                                 FCOMIP_st(1);
  3100                                 JNA_rel8( 32, sat );
  3101                                 load_imm32( R_ECX, (uint32_t)&min_int );  // 5
  3102                                 FILD_r32ind( R_ECX );           // 2
  3103                                 FCOMIP_st(1);                   // 2
  3104                                 JAE_rel8( 21, sat2 );            // 2
  3105                                 load_imm32( R_EAX, (uint32_t)&save_fcw );
  3106                                 FNSTCW_r32ind( R_EAX );
  3107                                 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
  3108                                 FLDCW_r32ind( R_EDX );
  3109                                 FISTP_sh4r(R_FPUL);             // 3
  3110                                 FLDCW_r32ind( R_EAX );
  3111                                 JMP_rel8( 9, end );             // 2
  3113                                 JMP_TARGET(sat);
  3114                                 JMP_TARGET(sat2);
  3115                                 MOV_r32ind_r32( R_ECX, R_ECX ); // 2
  3116                                 store_spreg( R_ECX, R_FPUL );
  3117                                 FPOP_st();
  3118                                 JMP_TARGET(end);
  3120                                 break;
  3121                             case 0x4:
  3122                                 { /* FNEG FRn */
  3123                                 uint32_t FRn = ((ir>>8)&0xF); 
  3124                                 check_fpuen();
  3125                                 load_spreg( R_ECX, R_FPSCR );
  3126                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3127                                 load_fr_bank( R_EDX );
  3128                                 JNE_rel8(10, doubleprec);
  3129                                 push_fr(R_EDX, FRn);
  3130                                 FCHS_st0();
  3131                                 pop_fr(R_EDX, FRn);
  3132                                 JMP_rel8(8, end);
  3133                                 JMP_TARGET(doubleprec);
  3134                                 push_dr(R_EDX, FRn);
  3135                                 FCHS_st0();
  3136                                 pop_dr(R_EDX, FRn);
  3137                                 JMP_TARGET(end);
  3139                                 break;
  3140                             case 0x5:
  3141                                 { /* FABS FRn */
  3142                                 uint32_t FRn = ((ir>>8)&0xF); 
  3143                                 check_fpuen();
  3144                                 load_spreg( R_ECX, R_FPSCR );
  3145                                 load_fr_bank( R_EDX );
  3146                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3147                                 JNE_rel8(10, doubleprec);
  3148                                 push_fr(R_EDX, FRn); // 3
  3149                                 FABS_st0(); // 2
  3150                                 pop_fr( R_EDX, FRn); //3
  3151                                 JMP_rel8(8,end); // 2
  3152                                 JMP_TARGET(doubleprec);
  3153                                 push_dr(R_EDX, FRn);
  3154                                 FABS_st0();
  3155                                 pop_dr(R_EDX, FRn);
  3156                                 JMP_TARGET(end);
  3158                                 break;
  3159                             case 0x6:
  3160                                 { /* FSQRT FRn */
  3161                                 uint32_t FRn = ((ir>>8)&0xF); 
  3162                                 check_fpuen();
  3163                                 load_spreg( R_ECX, R_FPSCR );
  3164                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3165                                 load_fr_bank( R_EDX );
  3166                                 JNE_rel8(10, doubleprec);
  3167                                 push_fr(R_EDX, FRn);
  3168                                 FSQRT_st0();
  3169                                 pop_fr(R_EDX, FRn);
  3170                                 JMP_rel8(8, end);
  3171                                 JMP_TARGET(doubleprec);
  3172                                 push_dr(R_EDX, FRn);
  3173                                 FSQRT_st0();
  3174                                 pop_dr(R_EDX, FRn);
  3175                                 JMP_TARGET(end);
  3177                                 break;
  3178                             case 0x7:
  3179                                 { /* FSRRA FRn */
  3180                                 uint32_t FRn = ((ir>>8)&0xF); 
  3181                                 check_fpuen();
  3182                                 load_spreg( R_ECX, R_FPSCR );
  3183                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3184                                 load_fr_bank( R_EDX );
  3185                                 JNE_rel8(12, end); // PR=0 only
  3186                                 FLD1_st0();
  3187                                 push_fr(R_EDX, FRn);
  3188                                 FSQRT_st0();
  3189                                 FDIVP_st(1);
  3190                                 pop_fr(R_EDX, FRn);
  3191                                 JMP_TARGET(end);
  3193                                 break;
  3194                             case 0x8:
  3195                                 { /* FLDI0 FRn */
  3196                                 uint32_t FRn = ((ir>>8)&0xF); 
  3197                                 /* IFF PR=0 */
  3198                                   check_fpuen();
  3199                                   load_spreg( R_ECX, R_FPSCR );
  3200                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3201                                   JNE_rel8(8, end);
  3202                                   XOR_r32_r32( R_EAX, R_EAX );
  3203                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3204                                   store_fr( R_ECX, R_EAX, FRn );
  3205                                   JMP_TARGET(end);
  3207                                 break;
  3208                             case 0x9:
  3209                                 { /* FLDI1 FRn */
  3210                                 uint32_t FRn = ((ir>>8)&0xF); 
  3211                                 /* IFF PR=0 */
  3212                                   check_fpuen();
  3213                                   load_spreg( R_ECX, R_FPSCR );
  3214                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3215                                   JNE_rel8(11, end);
  3216                                   load_imm32(R_EAX, 0x3F800000);
  3217                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3218                                   store_fr( R_ECX, R_EAX, FRn );
  3219                                   JMP_TARGET(end);
  3221                                 break;
  3222                             case 0xA:
  3223                                 { /* FCNVSD FPUL, FRn */
  3224                                 uint32_t FRn = ((ir>>8)&0xF); 
  3225                                 check_fpuen();
  3226                                 load_spreg( R_ECX, R_FPSCR );
  3227                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3228                                 JE_rel8(9, end); // only when PR=1
  3229                                 load_fr_bank( R_ECX );
  3230                                 push_fpul();
  3231                                 pop_dr( R_ECX, FRn );
  3232                                 JMP_TARGET(end);
  3234                                 break;
  3235                             case 0xB:
  3236                                 { /* FCNVDS FRm, FPUL */
  3237                                 uint32_t FRm = ((ir>>8)&0xF); 
  3238                                 check_fpuen();
  3239                                 load_spreg( R_ECX, R_FPSCR );
  3240                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3241                                 JE_rel8(9, end); // only when PR=1
  3242                                 load_fr_bank( R_ECX );
  3243                                 push_dr( R_ECX, FRm );
  3244                                 pop_fpul();
  3245                                 JMP_TARGET(end);
  3247                                 break;
  3248                             case 0xE:
  3249                                 { /* FIPR FVm, FVn */
  3250                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  3251                                 check_fpuen();
  3252                                 load_spreg( R_ECX, R_FPSCR );
  3253                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3254                                 JNE_rel8(44, doubleprec);
  3256                                 load_fr_bank( R_ECX );
  3257                                 push_fr( R_ECX, FVm<<2 );
  3258                                 push_fr( R_ECX, FVn<<2 );
  3259                                 FMULP_st(1);
  3260                                 push_fr( R_ECX, (FVm<<2)+1);
  3261                                 push_fr( R_ECX, (FVn<<2)+1);
  3262                                 FMULP_st(1);
  3263                                 FADDP_st(1);
  3264                                 push_fr( R_ECX, (FVm<<2)+2);
  3265                                 push_fr( R_ECX, (FVn<<2)+2);
  3266                                 FMULP_st(1);
  3267                                 FADDP_st(1);
  3268                                 push_fr( R_ECX, (FVm<<2)+3);
  3269                                 push_fr( R_ECX, (FVn<<2)+3);
  3270                                 FMULP_st(1);
  3271                                 FADDP_st(1);
  3272                                 pop_fr( R_ECX, (FVn<<2)+3);
  3273                                 JMP_TARGET(doubleprec);
  3275                                 break;
  3276                             case 0xF:
  3277                                 switch( (ir&0x100) >> 8 ) {
  3278                                     case 0x0:
  3279                                         { /* FSCA FPUL, FRn */
  3280                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  3281                                         check_fpuen();
  3282                                         load_spreg( R_ECX, R_FPSCR );
  3283                                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3284                                         JNE_rel8( 21, doubleprec );
  3285                                         load_fr_bank( R_ECX );
  3286                                         ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
  3287                                         load_spreg( R_EDX, R_FPUL );
  3288                                         call_func2( sh4_fsca, R_EDX, R_ECX );
  3289                                         JMP_TARGET(doubleprec);
  3291                                         break;
  3292                                     case 0x1:
  3293                                         switch( (ir&0x200) >> 9 ) {
  3294                                             case 0x0:
  3295                                                 { /* FTRV XMTRX, FVn */
  3296                                                 uint32_t FVn = ((ir>>10)&0x3); 
  3297                                                 check_fpuen();
  3298                                                 load_spreg( R_ECX, R_FPSCR );
  3299                                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3300                                                 JNE_rel8( 30, doubleprec );
  3301                                                 load_fr_bank( R_EDX );                 // 3
  3302                                                 ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
  3303                                                 load_xf_bank( R_ECX );                 // 12
  3304                                                 call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
  3305                                                 JMP_TARGET(doubleprec);
  3307                                                 break;
  3308                                             case 0x1:
  3309                                                 switch( (ir&0xC00) >> 10 ) {
  3310                                                     case 0x0:
  3311                                                         { /* FSCHG */
  3312                                                         check_fpuen();
  3313                                                         load_spreg( R_ECX, R_FPSCR );
  3314                                                         XOR_imm32_r32( FPSCR_SZ, R_ECX );
  3315                                                         store_spreg( R_ECX, R_FPSCR );
  3317                                                         break;
  3318                                                     case 0x2:
  3319                                                         { /* FRCHG */
  3320                                                         check_fpuen();
  3321                                                         load_spreg( R_ECX, R_FPSCR );
  3322                                                         XOR_imm32_r32( FPSCR_FR, R_ECX );
  3323                                                         store_spreg( R_ECX, R_FPSCR );
  3324                                                         update_fr_bank( R_ECX );
  3326                                                         break;
  3327                                                     case 0x3:
  3328                                                         { /* UNDEF */
  3329                                                         if( sh4_x86.in_delay_slot ) {
  3330                                                     	SLOTILLEGAL();
  3331                                                         } else {
  3332                                                     	precheck();
  3333                                                     	JMP_exit(EXIT_ILLEGAL);
  3334                                                     	return 2;
  3337                                                         break;
  3338                                                     default:
  3339                                                         UNDEF();
  3340                                                         break;
  3342                                                 break;
  3344                                         break;
  3346                                 break;
  3347                             default:
  3348                                 UNDEF();
  3349                                 break;
  3351                         break;
  3352                     case 0xE:
  3353                         { /* FMAC FR0, FRm, FRn */
  3354                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3355                         check_fpuen();
  3356                         load_spreg( R_ECX, R_FPSCR );
  3357                         load_spreg( R_EDX, REG_OFFSET(fr_bank));
  3358                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3359                         JNE_rel8(18, doubleprec);
  3360                         push_fr( R_EDX, 0 );
  3361                         push_fr( R_EDX, FRm );
  3362                         FMULP_st(1);
  3363                         push_fr( R_EDX, FRn );
  3364                         FADDP_st(1);
  3365                         pop_fr( R_EDX, FRn );
  3366                         JMP_rel8(16, end);
  3367                         JMP_TARGET(doubleprec);
  3368                         push_dr( R_EDX, 0 );
  3369                         push_dr( R_EDX, FRm );
  3370                         FMULP_st(1);
  3371                         push_dr( R_EDX, FRn );
  3372                         FADDP_st(1);
  3373                         pop_dr( R_EDX, FRn );
  3374                         JMP_TARGET(end);
  3376                         break;
  3377                     default:
  3378                         UNDEF();
  3379                         break;
  3381                 break;
  3384     sh4_x86.in_delay_slot = FALSE;
  3385     return 0;
.