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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 85:71e239d20c5d
prev65:9f124c245fc6
next94:8d80d9c7cc7d
author nkeynes
date Sun Jan 22 22:38:51 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Fix colour mode definitions
Add PVR2 palette region
Fix ta end-of-command when it's not in the same buffer
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     1 /**
     2  * $Id: pvr2.c,v 1.13 2006-01-22 22:38:51 nkeynes Exp $
     3  *
     4  * PVR2 (Video) MMIO and supporting functions.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "video.h"
    22 #include "mem.h"
    23 #include "asic.h"
    24 #include "pvr2.h"
    25 #include "sh4/sh4core.h"
    26 #define MMIO_IMPL
    27 #include "pvr2.h"
    29 char *video_base;
    31 void pvr2_init( void );
    32 uint32_t pvr2_run_slice( uint32_t );
    33 void pvr2_next_frame( void );
    35 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, 
    36 					pvr2_run_slice, NULL,
    37 					NULL, NULL };
    39 void pvr2_init( void )
    40 {
    41     register_io_region( &mmio_region_PVR2 );
    42     register_io_region( &mmio_region_PVR2PAL );
    43     register_io_region( &mmio_region_PVR2TA );
    44     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    45 }
    47 uint32_t pvr2_time_counter = 0;
    48 uint32_t pvr2_time_per_frame = 20000000;
    50 uint32_t pvr2_run_slice( uint32_t nanosecs ) 
    51 {
    52     pvr2_time_counter += nanosecs;
    53     while( pvr2_time_counter >= pvr2_time_per_frame ) {
    54 	pvr2_next_frame();
    55 	pvr2_time_counter -= pvr2_time_per_frame;
    56     }
    57     return nanosecs;
    58 }
    60 uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
    61 int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
    62 char *frame_start; /* current video start address (in real memory) */
    64 /*
    65  * Display the next frame, copying the current contents of video ram to
    66  * the window. If the video configuration has changed, first recompute the
    67  * new frame size/depth.
    68  */
    69 void pvr2_next_frame( void )
    70 {
    71     if( bChanged ) {
    72         int dispsize = MMIO_READ( PVR2, DISPSIZE );
    73         int dispmode = MMIO_READ( PVR2, DISPMODE );
    74         int vidcfg = MMIO_READ( PVR2, VIDCFG );
    75         vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
    76         vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
    77         vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
    78         vid_col = (dispmode & DISPMODE_COL);
    79         frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
    80         interlaced = (vidcfg & VIDCFG_I ? 1 : 0);
    81         bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & VIDCFG_VO ) ? 1 : 0;
    82         vid_size = (vid_ppl * vid_lpf) << (interlaced ? 3 : 2);
    83         vid_hres = vid_ppl;
    84         vid_vres = vid_lpf;
    85         if( interlaced ) vid_vres <<= 1;
    86         switch( vid_col ) {
    87             case MODE_RGB15:
    88             case MODE_RGB16: vid_hres <<= 1; break;
    89             case MODE_RGB24: vid_hres *= 3; break;
    90             case MODE_RGB32: vid_hres <<= 2; break;
    91         }
    92         vid_hres >>= 2;
    93         video_update_size( vid_hres, vid_vres, vid_col );
    94         bChanged = 0;
    95     }
    96     if( bEnabled ) {
    97 	if( MMIO_READ( PVR2, VIDCFG2 ) & 0x08 ) {
    98 	    /* Blanked */
    99 	    uint32_t colour = MMIO_READ( PVR2, BORDERCOL );
   100 	    video_fill( colour );
   101 	} else {
   102 	    /* Assume bit depths match for now... */
   103 	    memcpy( video_data, frame_start, vid_size );
   104 	}
   105     } else {
   106         memset( video_data, 0, vid_size );
   107     }
   108     video_update_frame();
   109     asic_event( EVENT_SCANLINE1 );
   110     asic_event( EVENT_SCANLINE2 );
   111     asic_event( EVENT_RETRACE );
   112 }
   114 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   115 {
   116     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   117         MMIO_WRITE( PVR2, reg, val );
   118         /* I don't want to hear about these */
   119         return;
   120     }
   122     INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
   123           MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
   125     switch(reg) {
   126     case DISPSIZE: bChanged = 1;
   127     case DISPMODE: bChanged = 1;
   128     case DISPADDR1: bChanged = 1;
   129     case DISPADDR2: bChanged = 1;
   130     case VIDCFG: bChanged = 1;
   131 	break;
   132     case RENDSTART:
   133 	if( val == 0xFFFFFFFF )
   134 	    pvr2_render_scene();
   135 	break;
   136     }
   137     MMIO_WRITE( PVR2, reg, val );
   138 }
   140 MMIO_REGION_READ_FN( PVR2, reg )
   141 {
   142     switch( reg ) {
   143         case BEAMPOS:
   144             return sh4r.icount&0x20 ? 0x2000 : 1;
   145         default:
   146             return MMIO_READ( PVR2, reg );
   147     }
   148 }
   150 MMIO_REGION_DEFFNS( PVR2PAL )
   152 void pvr2_set_base_address( uint32_t base ) 
   153 {
   154     mmio_region_PVR2_write( DISPADDR1, base );
   155 }
   158 void pvr2_render_scene( void )
   159 {
   160     /* Actual rendering goes here :) */
   161     asic_event( EVENT_PVR_RENDER_DONE );
   162     DEBUG( "Rendered frame %d", video_frame_count );
   163 }
   165 /** Tile Accelerator */
   167 struct tacmd {
   168     uint32_t command;
   169     uint32_t param1;
   170     uint32_t param2;
   171     uint32_t texture;
   172     float alpha;
   173     float red;
   174     float green;
   175     float blue;
   176 };
   178 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   179 {
   180     return 0xFFFFFFFF;
   181 }
   183 char pvr2ta_remainder[8];
   185 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   186 {
   187     DEBUG( "Direct write to TA %08X", val );
   188 }
   190 unsigned int pvr2_last_poly_type = 0;
   192 void pvr2ta_write( char *buf, uint32_t length )
   193 {
   194     int i;
   195     struct tacmd *cmd_list = (struct tacmd *)buf;
   196     int count = length >> 5;
   197     for( i=0; i<count; i++ ){
   198 	unsigned int type = (cmd_list[i].command >> 24) & 0xFF;
   199 	DEBUG( "PVR2 cmd: %08X %08X %08X", cmd_list[i].command, cmd_list[i].param1, cmd_list[i].param2 );
   200 	if( type == 0 ) {
   201 	    /* End of list */
   202 	    switch( pvr2_last_poly_type ) {
   203 	    case 0x80: /* Opaque polys */
   204 		asic_event( EVENT_PVR_OPAQUE_DONE );
   205 		break;
   206 	    case 0x81: /* Opaque poly modifier */
   207 		asic_event( EVENT_PVR_OPAQUEMOD_DONE );
   208 		break;
   209 	    case 0x82: /* Transparent polys */
   210 		asic_event( EVENT_PVR_TRANS_DONE );
   211 		break;
   212 	    case 0x83: /* Transparent poly modifier */
   213 		asic_event( EVENT_PVR_TRANSMOD_DONE );
   214 		break;
   215 	    case 0x84: /* Punchthrough */
   216 		asic_event( EVENT_PVR_PUNCHOUT_DONE );
   217 		break;
   218 	    }
   219 	    pvr2_last_poly_type = 0;
   220 	} else if( type >= 0x80 && type <= 0x84 ) {
   221 	    pvr2_last_poly_type = type;
   222 	}
   223     }
   224 }
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