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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 587:739a3136f269
prev586:2a3ba82cf243
next617:476a717a54f3
author nkeynes
date Wed Jan 16 09:35:30 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix instruction side-effects in presence of exceptions
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <assert.h>
    22 #include <math.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "eventq.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/intc.h"
    33 #define SH4_CALLTRACE 1
    35 #define MAX_INT 0x7FFFFFFF
    36 #define MIN_INT 0x80000000
    37 #define MAX_INTF 2147483647.0
    38 #define MIN_INTF -2147483648.0
    40 /********************** SH4 Module Definition ****************************/
    42 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    43 {
    44     int i;
    45     sh4r.slice_cycle = 0;
    47     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
    48 	if( sh4r.event_pending < nanosecs ) {
    49 	    sh4r.sh4_state = SH4_STATE_RUNNING;
    50 	    sh4r.slice_cycle = sh4r.event_pending;
    51 	}
    52     }
    54     if( sh4_breakpoint_count == 0 ) {
    55 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    56 	    if( SH4_EVENT_PENDING() ) {
    57 		if( sh4r.event_types & PENDING_EVENT ) {
    58 		    event_execute();
    59 		}
    60 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    61 		if( sh4r.event_types & PENDING_IRQ ) {
    62 		    sh4_accept_interrupt();
    63 		}
    64 	    }
    65 	    if( !sh4_execute_instruction() ) {
    66 		break;
    67 	    }
    68 	}
    69     } else {
    70 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    71 	    if( SH4_EVENT_PENDING() ) {
    72 		if( sh4r.event_types & PENDING_EVENT ) {
    73 		    event_execute();
    74 		}
    75 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    76 		if( sh4r.event_types & PENDING_IRQ ) {
    77 		    sh4_accept_interrupt();
    78 		}
    79 	    }
    81 	    if( !sh4_execute_instruction() )
    82 		break;
    83 #ifdef ENABLE_DEBUG_MODE
    84 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    85 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    86 		    break;
    87 		}
    88 	    }
    89 	    if( i != sh4_breakpoint_count ) {
    90 		dreamcast_stop();
    91 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
    92 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
    93 		break;
    94 	    }
    95 #endif	
    96 	}
    97     }
    99     /* If we aborted early, but the cpu is still technically running,
   100      * we're doing a hard abort - cut the timeslice back to what we
   101      * actually executed
   102      */
   103     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   104 	nanosecs = sh4r.slice_cycle;
   105     }
   106     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   107 	TMU_run_slice( nanosecs );
   108 	SCIF_run_slice( nanosecs );
   109     }
   110     return nanosecs;
   111 }
   113 /********************** SH4 emulation core  ****************************/
   115 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   116 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   118 #if(SH4_CALLTRACE == 1)
   119 #define MAX_CALLSTACK 32
   120 static struct call_stack {
   121     sh4addr_t call_addr;
   122     sh4addr_t target_addr;
   123     sh4addr_t stack_pointer;
   124 } call_stack[MAX_CALLSTACK];
   126 static int call_stack_depth = 0;
   127 int sh4_call_trace_on = 0;
   129 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   130 {
   131     if( call_stack_depth < MAX_CALLSTACK ) {
   132 	call_stack[call_stack_depth].call_addr = source;
   133 	call_stack[call_stack_depth].target_addr = dest;
   134 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   135     }
   136     call_stack_depth++;
   137 }
   139 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   140 {
   141     if( call_stack_depth > 0 ) {
   142 	call_stack_depth--;
   143     }
   144 }
   146 void fprint_stack_trace( FILE *f )
   147 {
   148     int i = call_stack_depth -1;
   149     if( i >= MAX_CALLSTACK )
   150 	i = MAX_CALLSTACK - 1;
   151     for( ; i >= 0; i-- ) {
   152 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   153 		 (call_stack_depth - i), call_stack[i].call_addr,
   154 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   155     }
   156 }
   158 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   159 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   160 #else
   161 #define TRACE_CALL( dest, rts ) 
   162 #define TRACE_RETURN( source, dest )
   163 #endif
   165 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
   166 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
   167 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
   168 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
   169 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
   170 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
   172 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   174 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   175 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   177 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   178 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   179 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   180 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   181 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   183 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   184 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   185 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   187 static void sh4_write_float( uint32_t addr, int reg )
   188 {
   189     if( IS_FPU_DOUBLESIZE() ) {
   190 	if( reg & 1 ) {
   191 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   192 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   193 	} else {
   194 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   195 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   196 	}
   197     } else {
   198 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   199     }
   200 }
   202 static void sh4_read_float( uint32_t addr, int reg )
   203 {
   204     if( IS_FPU_DOUBLESIZE() ) {
   205 	if( reg & 1 ) {
   206 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   207 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   208 	} else {
   209 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   210 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   211 	}
   212     } else {
   213 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   214     }
   215 }
   217 gboolean sh4_execute_instruction( void )
   218 {
   219     uint32_t pc;
   220     unsigned short ir;
   221     uint32_t tmp;
   222     float ftmp;
   223     double dtmp;
   224     int64_t memtmp; // temporary holder for memory reads
   226 #define R0 sh4r.r[0]
   227     pc = sh4r.pc;
   228     if( pc > 0xFFFFFF00 ) {
   229 	/* SYSCALL Magic */
   230 	syscall_invoke( pc );
   231 	sh4r.in_delay_slot = 0;
   232 	pc = sh4r.pc = sh4r.pr;
   233 	sh4r.new_pc = sh4r.pc + 2;
   234     }
   235     CHECKRALIGN16(pc);
   237     /* Read instruction */
   238     if( !IS_IN_ICACHE(pc) ) {
   239 	if( !mmu_update_icache(pc) ) {
   240 	    // Fault - look for the fault handler
   241 	    if( !mmu_update_icache(sh4r.pc) ) {
   242 		// double fault - halt
   243 		ERROR( "Double fault - halting" );
   244 		dreamcast_stop();
   245 		return FALSE;
   246 	    }
   247 	}
   248 	pc = sh4r.pc;
   249     }
   250     assert( IS_IN_ICACHE(pc) );
   251     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   252 %%
   253 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   254 AND #imm, R0 {: R0 &= imm; :}
   255  AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
   256 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   257 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   258 OR #imm, R0  {: R0 |= imm; :}
   259  OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
   260 TAS.B @Rn {:
   261     MEM_READ_BYTE( sh4r.r[Rn], tmp );
   262     sh4r.t = ( tmp == 0 ? 1 : 0 );
   263     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   264 :}
   265 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   266 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   267  TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
   268 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   269 XOR #imm, R0 {: R0 ^= imm; :}
   270  XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
   271 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   273 ROTL Rn {:
   274     sh4r.t = sh4r.r[Rn] >> 31;
   275     sh4r.r[Rn] <<= 1;
   276     sh4r.r[Rn] |= sh4r.t;
   277 :}
   278 ROTR Rn {:
   279     sh4r.t = sh4r.r[Rn] & 0x00000001;
   280     sh4r.r[Rn] >>= 1;
   281     sh4r.r[Rn] |= (sh4r.t << 31);
   282 :}
   283 ROTCL Rn {:
   284     tmp = sh4r.r[Rn] >> 31;
   285     sh4r.r[Rn] <<= 1;
   286     sh4r.r[Rn] |= sh4r.t;
   287     sh4r.t = tmp;
   288 :}
   289 ROTCR Rn {:
   290     tmp = sh4r.r[Rn] & 0x00000001;
   291     sh4r.r[Rn] >>= 1;
   292     sh4r.r[Rn] |= (sh4r.t << 31 );
   293     sh4r.t = tmp;
   294 :}
   295 SHAD Rm, Rn {:
   296     tmp = sh4r.r[Rm];
   297     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   298     else if( (tmp & 0x1F) == 0 )  
   299         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   300     else 
   301 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   302 :}
   303 SHLD Rm, Rn {:
   304     tmp = sh4r.r[Rm];
   305     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   306     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   307     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   308 :}
   309 SHAL Rn {:
   310     sh4r.t = sh4r.r[Rn] >> 31;
   311     sh4r.r[Rn] <<= 1;
   312 :}
   313 SHAR Rn {:
   314     sh4r.t = sh4r.r[Rn] & 0x00000001;
   315     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   316 :}
   317 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   318 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   319 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   320 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   321 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   322 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   323 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   324 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   326 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   327 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   328 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   329 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   330 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   331 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   333 CLRT {: sh4r.t = 0; :}
   334 SETT {: sh4r.t = 1; :}
   335 CLRMAC {: sh4r.mac = 0; :}
   336 LDTLB {: MMU_ldtlb(); :}
   337 CLRS {: sh4r.s = 0; :}
   338 SETS {: sh4r.s = 1; :}
   339 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   340 NOP {: /* NOP */ :}
   342 PREF @Rn {:
   343      tmp = sh4r.r[Rn];
   344      if( (tmp & 0xFC000000) == 0xE0000000 ) {
   345 	 sh4_flush_store_queue(tmp);
   346      }
   347 :}
   348 OCBI @Rn {: :}
   349 OCBP @Rn {: :}
   350 OCBWB @Rn {: :}
   351 MOVCA.L R0, @Rn {:
   352     tmp = sh4r.r[Rn];
   353     CHECKWALIGN32(tmp);
   354     MEM_WRITE_LONG( tmp, R0 );
   355 :}
   356 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   357 MOV.W Rm, @(R0, Rn) {: 
   358     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   359     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   360 :}
   361 MOV.L Rm, @(R0, Rn) {:
   362     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   363     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   364 :}
   365 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
   366 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   367     MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   368 :}
   369 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   370     MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   371 :}
   372 MOV.L Rm, @(disp, Rn) {:
   373     tmp = sh4r.r[Rn] + disp;
   374     CHECKWALIGN32( tmp );
   375     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   376 :}
   377 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   378 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   379 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   380  MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
   381  MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
   382  MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
   383 MOV.L @(disp, Rm), Rn {:
   384     tmp = sh4r.r[Rm] + disp;
   385     CHECKRALIGN32( tmp );
   386     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   387 :}
   388 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
   389  MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
   390  MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
   391 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   392  MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
   393  MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
   394  MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
   395 MOV.L @(disp, PC), Rn {:
   396     CHECKSLOTILLEGAL();
   397     tmp = (pc&0xFFFFFFFC) + disp + 4;
   398     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   399 :}
   400 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   401 MOV.W R0, @(disp, GBR) {:
   402     tmp = sh4r.gbr + disp;
   403     CHECKWALIGN16( tmp );
   404     MEM_WRITE_WORD( tmp, R0 );
   405 :}
   406 MOV.L R0, @(disp, GBR) {:
   407     tmp = sh4r.gbr + disp;
   408     CHECKWALIGN32( tmp );
   409     MEM_WRITE_LONG( tmp, R0 );
   410 :}
   411  MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
   412 MOV.W @(disp, GBR), R0 {: 
   413     tmp = sh4r.gbr + disp;
   414     CHECKRALIGN16( tmp );
   415     MEM_READ_WORD( tmp, R0 );
   416 :}
   417 MOV.L @(disp, GBR), R0 {:
   418     tmp = sh4r.gbr + disp;
   419     CHECKRALIGN32( tmp );
   420     MEM_READ_LONG( tmp, R0 );
   421 :}
   422 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   423 MOV.W R0, @(disp, Rn) {: 
   424     tmp = sh4r.r[Rn] + disp;
   425     CHECKWALIGN16( tmp );
   426     MEM_WRITE_WORD( tmp, R0 );
   427 :}
   428  MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
   429 MOV.W @(disp, Rm), R0 {: 
   430     tmp = sh4r.r[Rm] + disp;
   431     CHECKRALIGN16( tmp );
   432     MEM_READ_WORD( tmp, R0 );
   433 :}
   434 MOV.W @(disp, PC), Rn {:
   435     CHECKSLOTILLEGAL();
   436     tmp = pc + 4 + disp;
   437     MEM_READ_WORD( tmp, sh4r.r[Rn] );
   438 :}
   439 MOVA @(disp, PC), R0 {:
   440     CHECKSLOTILLEGAL();
   441     R0 = (pc&0xFFFFFFFC) + disp + 4;
   442 :}
   443 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   445 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   446 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   447 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   448 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   449 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   450 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   451 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   452 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   453 CMP/STR Rm, Rn {: 
   454     /* set T = 1 if any byte in RM & RN is the same */
   455     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   456     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   457              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   458 :}
   460 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   461 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   462 ADDC Rm, Rn {:
   463     tmp = sh4r.r[Rn];
   464     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   465     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   466 :}
   467 ADDV Rm, Rn {:
   468     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   469     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   470     sh4r.r[Rn] = tmp;
   471 :}
   472 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   473 DIV0S Rm, Rn {: 
   474     sh4r.q = sh4r.r[Rn]>>31;
   475     sh4r.m = sh4r.r[Rm]>>31;
   476     sh4r.t = sh4r.q ^ sh4r.m;
   477 :}
   478 DIV1 Rm, Rn {:
   479     /* This is derived from the sh4 manual with some simplifications */
   480     uint32_t tmp0, tmp1, tmp2, dir;
   482     dir = sh4r.q ^ sh4r.m;
   483     sh4r.q = (sh4r.r[Rn] >> 31);
   484     tmp2 = sh4r.r[Rm];
   485     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   486     tmp0 = sh4r.r[Rn];
   487     if( dir ) {
   488          sh4r.r[Rn] += tmp2;
   489          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   490     } else {
   491          sh4r.r[Rn] -= tmp2;
   492          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   493     }
   494     sh4r.q ^= sh4r.m ^ tmp1;
   495     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   496 :}
   497 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   498 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   499 DT Rn {:
   500     sh4r.r[Rn] --;
   501     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   502 :}
   503 MAC.W @Rm+, @Rn+ {:
   504     int32_t stmp;
   505     if( Rm == Rn ) {
   506 	CHECKRALIGN16(sh4r.r[Rn]);
   507 	MEM_READ_WORD( sh4r.r[Rn], tmp );
   508 	stmp = SIGNEXT16(tmp);
   509 	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
   510 	stmp *= SIGNEXT16(tmp);
   511 	sh4r.r[Rn] += 4;
   512     } else {
   513 	CHECKRALIGN16( sh4r.r[Rn] );
   514 	CHECKRALIGN16( sh4r.r[Rm] );
   515 	MEM_READ_WORD(sh4r.r[Rn], tmp);
   516 	stmp = SIGNEXT16(tmp);
   517 	MEM_READ_WORD(sh4r.r[Rm], tmp);
   518 	stmp = stmp * SIGNEXT16(tmp);
   519 	sh4r.r[Rn] += 2;
   520 	sh4r.r[Rm] += 2;
   521     }
   522     if( sh4r.s ) {
   523 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   524 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   525 	    sh4r.mac = 0x000000017FFFFFFFLL;
   526 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   527 	    sh4r.mac = 0x0000000180000000LL;
   528 	} else {
   529 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   530 		((uint32_t)(sh4r.mac + stmp));
   531 	}
   532     } else {
   533 	sh4r.mac += SIGNEXT32(stmp);
   534     }
   535 :}
   536 MAC.L @Rm+, @Rn+ {:
   537     int64_t tmpl;
   538     if( Rm == Rn ) {
   539 	CHECKRALIGN32( sh4r.r[Rn] );
   540 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   541 	tmpl = SIGNEXT32(tmp);
   542 	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
   543 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   544 	sh4r.r[Rn] += 8;
   545     } else {
   546 	CHECKRALIGN32( sh4r.r[Rm] );
   547 	CHECKRALIGN32( sh4r.r[Rn] );
   548 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   549 	tmpl = SIGNEXT32(tmp);
   550 	MEM_READ_LONG(sh4r.r[Rm], tmp);
   551 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   552 	sh4r.r[Rn] += 4;
   553 	sh4r.r[Rm] += 4;
   554     }
   555     if( sh4r.s ) {
   556         /* 48-bit Saturation. Yuch */
   557         if( tmpl < (int64_t)0xFFFF800000000000LL )
   558             tmpl = 0xFFFF800000000000LL;
   559         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   560             tmpl = 0x00007FFFFFFFFFFFLL;
   561     }
   562     sh4r.mac = tmpl;
   563 :}
   564 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   565                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   566 MULU.W Rm, Rn {:
   567     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   568                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   569 :}
   570 MULS.W Rm, Rn {:
   571     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   572                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   573 :}
   574 NEGC Rm, Rn {:
   575     tmp = 0 - sh4r.r[Rm];
   576     sh4r.r[Rn] = tmp - sh4r.t;
   577     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   578 :}
   579 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   580 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   581 SUBC Rm, Rn {: 
   582     tmp = sh4r.r[Rn];
   583     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   584     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   585 :}
   587 BRAF Rn {:
   588      CHECKSLOTILLEGAL();
   589      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   590      sh4r.in_delay_slot = 1;
   591      sh4r.pc = sh4r.new_pc;
   592      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   593      return TRUE;
   594 :}
   595 BSRF Rn {:
   596      CHECKSLOTILLEGAL();
   597      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   598      sh4r.in_delay_slot = 1;
   599      sh4r.pr = sh4r.pc + 4;
   600      sh4r.pc = sh4r.new_pc;
   601      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   602      TRACE_CALL( pc, sh4r.new_pc );
   603      return TRUE;
   604 :}
   605 BT disp {:
   606     CHECKSLOTILLEGAL();
   607     if( sh4r.t ) {
   608         CHECKDEST( sh4r.pc + disp + 4 )
   609         sh4r.pc += disp + 4;
   610         sh4r.new_pc = sh4r.pc + 2;
   611         return TRUE;
   612     }
   613 :}
   614 BF disp {:
   615     CHECKSLOTILLEGAL();
   616     if( !sh4r.t ) {
   617         CHECKDEST( sh4r.pc + disp + 4 )
   618         sh4r.pc += disp + 4;
   619         sh4r.new_pc = sh4r.pc + 2;
   620         return TRUE;
   621     }
   622 :}
   623 BT/S disp {:
   624     CHECKSLOTILLEGAL();
   625     if( sh4r.t ) {
   626         CHECKDEST( sh4r.pc + disp + 4 )
   627         sh4r.in_delay_slot = 1;
   628         sh4r.pc = sh4r.new_pc;
   629         sh4r.new_pc = pc + disp + 4;
   630         sh4r.in_delay_slot = 1;
   631         return TRUE;
   632     }
   633 :}
   634 BF/S disp {:
   635     CHECKSLOTILLEGAL();
   636     if( !sh4r.t ) {
   637         CHECKDEST( sh4r.pc + disp + 4 )
   638         sh4r.in_delay_slot = 1;
   639         sh4r.pc = sh4r.new_pc;
   640         sh4r.new_pc = pc + disp + 4;
   641         return TRUE;
   642     }
   643 :}
   644 BRA disp {:
   645     CHECKSLOTILLEGAL();
   646     CHECKDEST( sh4r.pc + disp + 4 );
   647     sh4r.in_delay_slot = 1;
   648     sh4r.pc = sh4r.new_pc;
   649     sh4r.new_pc = pc + 4 + disp;
   650     return TRUE;
   651 :}
   652 BSR disp {:
   653     CHECKDEST( sh4r.pc + disp + 4 );
   654     CHECKSLOTILLEGAL();
   655     sh4r.in_delay_slot = 1;
   656     sh4r.pr = pc + 4;
   657     sh4r.pc = sh4r.new_pc;
   658     sh4r.new_pc = pc + 4 + disp;
   659     TRACE_CALL( pc, sh4r.new_pc );
   660     return TRUE;
   661 :}
   662 TRAPA #imm {:
   663     CHECKSLOTILLEGAL();
   664     sh4r.pc += 2;
   665     sh4_raise_trap( imm );
   666     return TRUE;
   667 :}
   668 RTS {: 
   669     CHECKSLOTILLEGAL();
   670     CHECKDEST( sh4r.pr );
   671     sh4r.in_delay_slot = 1;
   672     sh4r.pc = sh4r.new_pc;
   673     sh4r.new_pc = sh4r.pr;
   674     TRACE_RETURN( pc, sh4r.new_pc );
   675     return TRUE;
   676 :}
   677 SLEEP {:
   678     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   679 	sh4r.sh4_state = SH4_STATE_STANDBY;
   680     } else {
   681 	sh4r.sh4_state = SH4_STATE_SLEEP;
   682     }
   683     return FALSE; /* Halt CPU */
   684 :}
   685 RTE {:
   686     CHECKPRIV();
   687     CHECKDEST( sh4r.spc );
   688     CHECKSLOTILLEGAL();
   689     sh4r.in_delay_slot = 1;
   690     sh4r.pc = sh4r.new_pc;
   691     sh4r.new_pc = sh4r.spc;
   692     sh4_write_sr( sh4r.ssr );
   693     return TRUE;
   694 :}
   695 JMP @Rn {:
   696     CHECKDEST( sh4r.r[Rn] );
   697     CHECKSLOTILLEGAL();
   698     sh4r.in_delay_slot = 1;
   699     sh4r.pc = sh4r.new_pc;
   700     sh4r.new_pc = sh4r.r[Rn];
   701     return TRUE;
   702 :}
   703 JSR @Rn {:
   704     CHECKDEST( sh4r.r[Rn] );
   705     CHECKSLOTILLEGAL();
   706     sh4r.in_delay_slot = 1;
   707     sh4r.pc = sh4r.new_pc;
   708     sh4r.new_pc = sh4r.r[Rn];
   709     sh4r.pr = pc + 4;
   710     TRACE_CALL( pc, sh4r.new_pc );
   711     return TRUE;
   712 :}
   713 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   714 STS.L MACH, @-Rn {:
   715     CHECKWALIGN32( sh4r.r[Rn] );
   716     MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
   717     sh4r.r[Rn] -= 4;
   718 :}
   719 STC.L SR, @-Rn {:
   720     CHECKPRIV();
   721     CHECKWALIGN32( sh4r.r[Rn] );
   722     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
   723     sh4r.r[Rn] -= 4;
   724 :}
   725 LDS.L @Rm+, MACH {:
   726     CHECKRALIGN32( sh4r.r[Rm] );
   727     MEM_READ_LONG(sh4r.r[Rm], tmp);
   728     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   729 	(((uint64_t)tmp)<<32);
   730     sh4r.r[Rm] += 4;
   731 :}
   732 LDC.L @Rm+, SR {:
   733     CHECKSLOTILLEGAL();
   734     CHECKPRIV();
   735     CHECKWALIGN32( sh4r.r[Rm] );
   736     MEM_READ_LONG(sh4r.r[Rm], tmp);
   737     sh4_write_sr( tmp );
   738     sh4r.r[Rm] +=4;
   739 :}
   740 LDS Rm, MACH {:
   741     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   742                (((uint64_t)sh4r.r[Rm])<<32);
   743 :}
   744 LDC Rm, SR {:
   745     CHECKSLOTILLEGAL();
   746     CHECKPRIV();
   747     sh4_write_sr( sh4r.r[Rm] );
   748 :}
   749 LDC Rm, SGR {:
   750     CHECKPRIV();
   751     sh4r.sgr = sh4r.r[Rm];
   752 :}
   753 LDC.L @Rm+, SGR {:
   754     CHECKPRIV();
   755     CHECKRALIGN32( sh4r.r[Rm] );
   756     MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
   757     sh4r.r[Rm] +=4;
   758 :}
   759 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   760 STS.L MACL, @-Rn {:
   761     CHECKWALIGN32( sh4r.r[Rn] );
   762     MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
   763     sh4r.r[Rn] -= 4;
   764 :}
   765 STC.L GBR, @-Rn {:
   766     CHECKWALIGN32( sh4r.r[Rn] );
   767     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
   768     sh4r.r[Rn] -= 4;
   769 :}
   770 LDS.L @Rm+, MACL {:
   771     CHECKRALIGN32( sh4r.r[Rm] );
   772     MEM_READ_LONG(sh4r.r[Rm], tmp);
   773     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   774                (uint64_t)((uint32_t)tmp);
   775     sh4r.r[Rm] += 4;
   776 :}
   777 LDC.L @Rm+, GBR {:
   778     CHECKRALIGN32( sh4r.r[Rm] );
   779     MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
   780     sh4r.r[Rm] +=4;
   781 :}
   782 LDS Rm, MACL {:
   783     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   784                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   785 :}
   786 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   787 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   788 STS.L PR, @-Rn {:
   789     CHECKWALIGN32( sh4r.r[Rn] );
   790     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
   791     sh4r.r[Rn] -= 4;
   792 :}
   793 STC.L VBR, @-Rn {:
   794     CHECKPRIV();
   795     CHECKWALIGN32( sh4r.r[Rn] );
   796     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
   797     sh4r.r[Rn] -= 4;
   798 :}
   799 LDS.L @Rm+, PR {:
   800     CHECKRALIGN32( sh4r.r[Rm] );
   801     MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
   802     sh4r.r[Rm] += 4;
   803 :}
   804 LDC.L @Rm+, VBR {:
   805     CHECKPRIV();
   806     CHECKRALIGN32( sh4r.r[Rm] );
   807     MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
   808     sh4r.r[Rm] +=4;
   809 :}
   810 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   811 LDC Rm, VBR {:
   812     CHECKPRIV();
   813     sh4r.vbr = sh4r.r[Rm];
   814 :}
   815 STC SGR, Rn {:
   816     CHECKPRIV();
   817     sh4r.r[Rn] = sh4r.sgr;
   818 :}
   819 STC.L SGR, @-Rn {:
   820     CHECKPRIV();
   821     CHECKWALIGN32( sh4r.r[Rn] );
   822     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
   823     sh4r.r[Rn] -= 4;
   824 :}
   825 STC.L SSR, @-Rn {:
   826     CHECKPRIV();
   827     CHECKWALIGN32( sh4r.r[Rn] );
   828     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
   829     sh4r.r[Rn] -= 4;
   830 :}
   831 LDC.L @Rm+, SSR {:
   832     CHECKPRIV();
   833     CHECKRALIGN32( sh4r.r[Rm] );
   834     MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
   835     sh4r.r[Rm] +=4;
   836 :}
   837 LDC Rm, SSR {:
   838     CHECKPRIV();
   839     sh4r.ssr = sh4r.r[Rm];
   840 :}
   841 STC.L SPC, @-Rn {:
   842     CHECKPRIV();
   843     CHECKWALIGN32( sh4r.r[Rn] );
   844     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
   845     sh4r.r[Rn] -= 4;
   846 :}
   847 LDC.L @Rm+, SPC {:
   848     CHECKPRIV();
   849     CHECKRALIGN32( sh4r.r[Rm] );
   850     MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
   851     sh4r.r[Rm] +=4;
   852 :}
   853 LDC Rm, SPC {:
   854     CHECKPRIV();
   855     sh4r.spc = sh4r.r[Rm];
   856 :}
   857 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
   858 STS.L FPUL, @-Rn {:
   859     CHECKWALIGN32( sh4r.r[Rn] );
   860     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
   861     sh4r.r[Rn] -= 4;
   862 :}
   863 LDS.L @Rm+, FPUL {:
   864     CHECKRALIGN32( sh4r.r[Rm] );
   865     MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
   866     sh4r.r[Rm] +=4;
   867 :}
   868 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
   869 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
   870 STS.L FPSCR, @-Rn {:
   871     CHECKWALIGN32( sh4r.r[Rn] );
   872     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
   873     sh4r.r[Rn] -= 4;
   874 :}
   875 LDS.L @Rm+, FPSCR {:
   876     CHECKRALIGN32( sh4r.r[Rm] );
   877     MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
   878     sh4r.r[Rm] +=4;
   879     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
   880 :}
   881 LDS Rm, FPSCR {: 
   882     sh4r.fpscr = sh4r.r[Rm]; 
   883     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
   884 :}
   885 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
   886 STC.L DBR, @-Rn {:
   887     CHECKPRIV();
   888     CHECKWALIGN32( sh4r.r[Rn] );
   889     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
   890     sh4r.r[Rn] -= 4;
   891 :}
   892 LDC.L @Rm+, DBR {:
   893     CHECKPRIV();
   894     CHECKRALIGN32( sh4r.r[Rm] );
   895     MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
   896     sh4r.r[Rm] +=4;
   897 :}
   898 LDC Rm, DBR {:
   899     CHECKPRIV();
   900     sh4r.dbr = sh4r.r[Rm];
   901 :}
   902 STC.L Rm_BANK, @-Rn {:
   903     CHECKPRIV();
   904     CHECKWALIGN32( sh4r.r[Rn] );
   905     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
   906     sh4r.r[Rn] -= 4;
   907 :}
   908 LDC.L @Rm+, Rn_BANK {:
   909     CHECKPRIV();
   910     CHECKRALIGN32( sh4r.r[Rm] );
   911     MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
   912     sh4r.r[Rm] += 4;
   913 :}
   914 LDC Rm, Rn_BANK {:
   915     CHECKPRIV();
   916     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
   917 :}
   918 STC SR, Rn {: 
   919     CHECKPRIV();
   920     sh4r.r[Rn] = sh4_read_sr();
   921 :}
   922 STC GBR, Rn {:
   923     CHECKPRIV();
   924     sh4r.r[Rn] = sh4r.gbr;
   925 :}
   926 STC VBR, Rn {:
   927     CHECKPRIV();
   928     sh4r.r[Rn] = sh4r.vbr;
   929 :}
   930 STC SSR, Rn {:
   931     CHECKPRIV();
   932     sh4r.r[Rn] = sh4r.ssr;
   933 :}
   934 STC SPC, Rn {:
   935     CHECKPRIV();
   936     sh4r.r[Rn] = sh4r.spc;
   937 :}
   938 STC Rm_BANK, Rn {:
   939     CHECKPRIV();
   940     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   941 :}
   943 FADD FRm, FRn {:
   944     CHECKFPUEN();
   945     if( IS_FPU_DOUBLEPREC() ) {
   946 	DR(FRn) += DR(FRm);
   947     } else {
   948 	FR(FRn) += FR(FRm);
   949     }
   950 :}
   951 FSUB FRm, FRn {:
   952     CHECKFPUEN();
   953     if( IS_FPU_DOUBLEPREC() ) {
   954 	DR(FRn) -= DR(FRm);
   955     } else {
   956 	FR(FRn) -= FR(FRm);
   957     }
   958 :}
   960 FMUL FRm, FRn {:
   961     CHECKFPUEN();
   962     if( IS_FPU_DOUBLEPREC() ) {
   963 	DR(FRn) *= DR(FRm);
   964     } else {
   965 	FR(FRn) *= FR(FRm);
   966     }
   967 :}
   969 FDIV FRm, FRn {:
   970     CHECKFPUEN();
   971     if( IS_FPU_DOUBLEPREC() ) {
   972 	DR(FRn) /= DR(FRm);
   973     } else {
   974 	FR(FRn) /= FR(FRm);
   975     }
   976 :}
   978 FCMP/EQ FRm, FRn {:
   979     CHECKFPUEN();
   980     if( IS_FPU_DOUBLEPREC() ) {
   981 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
   982     } else {
   983 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
   984     }
   985 :}
   987 FCMP/GT FRm, FRn {:
   988     CHECKFPUEN();
   989     if( IS_FPU_DOUBLEPREC() ) {
   990 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
   991     } else {
   992 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
   993     }
   994 :}
   996 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
   997 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
   998 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
   999 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
  1000 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
  1001  FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
  1002 FMOV FRm, FRn {: 
  1003     if( IS_FPU_DOUBLESIZE() )
  1004 	DR(FRn) = DR(FRm);
  1005     else
  1006 	FR(FRn) = FR(FRm);
  1007 :}
  1008 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
  1009 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
  1010 FLOAT FPUL, FRn {: 
  1011     CHECKFPUEN();
  1012     if( IS_FPU_DOUBLEPREC() ) {
  1013 	if( FRn&1 ) { // No, really...
  1014 	    dtmp = (double)FPULi;
  1015 	    FR(FRn) = *(((float *)&dtmp)+1);
  1016 	} else {
  1017 	    DRF(FRn>>1) = (double)FPULi;
  1019     } else {
  1020 	FR(FRn) = (float)FPULi;
  1022 :}
  1023 FTRC FRm, FPUL {:
  1024     CHECKFPUEN();
  1025     if( IS_FPU_DOUBLEPREC() ) {
  1026 	if( FRm&1 ) {
  1027 	    dtmp = 0;
  1028 	    *(((float *)&dtmp)+1) = FR(FRm);
  1029 	} else {
  1030 	    dtmp = DRF(FRm>>1);
  1032         if( dtmp >= MAX_INTF )
  1033             FPULi = MAX_INT;
  1034         else if( dtmp <= MIN_INTF )
  1035             FPULi = MIN_INT;
  1036         else 
  1037             FPULi = (int32_t)dtmp;
  1038     } else {
  1039 	ftmp = FR(FRm);
  1040 	if( ftmp >= MAX_INTF )
  1041 	    FPULi = MAX_INT;
  1042 	else if( ftmp <= MIN_INTF )
  1043 	    FPULi = MIN_INT;
  1044 	else
  1045 	    FPULi = (int32_t)ftmp;
  1047 :}
  1048 FNEG FRn {:
  1049     CHECKFPUEN();
  1050     if( IS_FPU_DOUBLEPREC() ) {
  1051 	DR(FRn) = -DR(FRn);
  1052     } else {
  1053         FR(FRn) = -FR(FRn);
  1055 :}
  1056 FABS FRn {:
  1057     CHECKFPUEN();
  1058     if( IS_FPU_DOUBLEPREC() ) {
  1059 	DR(FRn) = fabs(DR(FRn));
  1060     } else {
  1061         FR(FRn) = fabsf(FR(FRn));
  1063 :}
  1064 FSQRT FRn {:
  1065     CHECKFPUEN();
  1066     if( IS_FPU_DOUBLEPREC() ) {
  1067 	DR(FRn) = sqrt(DR(FRn));
  1068     } else {
  1069         FR(FRn) = sqrtf(FR(FRn));
  1071 :}
  1072 FLDI0 FRn {:
  1073     CHECKFPUEN();
  1074     if( IS_FPU_DOUBLEPREC() ) {
  1075 	DR(FRn) = 0.0;
  1076     } else {
  1077         FR(FRn) = 0.0;
  1079 :}
  1080 FLDI1 FRn {:
  1081     CHECKFPUEN();
  1082     if( IS_FPU_DOUBLEPREC() ) {
  1083 	DR(FRn) = 1.0;
  1084     } else {
  1085         FR(FRn) = 1.0;
  1087 :}
  1088 FMAC FR0, FRm, FRn {:
  1089     CHECKFPUEN();
  1090     if( IS_FPU_DOUBLEPREC() ) {
  1091         DR(FRn) += DR(FRm)*DR(0);
  1092     } else {
  1093 	FR(FRn) += FR(FRm)*FR(0);
  1095 :}
  1096 FRCHG {: 
  1097     CHECKFPUEN(); 
  1098     sh4r.fpscr ^= FPSCR_FR; 
  1099     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1100 :}
  1101 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1102 FCNVSD FPUL, FRn {:
  1103     CHECKFPUEN();
  1104     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1105 	DR(FRn) = (double)FPULf;
  1107 :}
  1108 FCNVDS FRm, FPUL {:
  1109     CHECKFPUEN();
  1110     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1111 	FPULf = (float)DR(FRm);
  1113 :}
  1115 FSRRA FRn {:
  1116     CHECKFPUEN();
  1117     if( !IS_FPU_DOUBLEPREC() ) {
  1118 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1120 :}
  1121 FIPR FVm, FVn {:
  1122     CHECKFPUEN();
  1123     if( !IS_FPU_DOUBLEPREC() ) {
  1124         int tmp2 = FVn<<2;
  1125         tmp = FVm<<2;
  1126         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1127             FR(tmp+1)*FR(tmp2+1) +
  1128             FR(tmp+2)*FR(tmp2+2) +
  1129             FR(tmp+3)*FR(tmp2+3);
  1131 :}
  1132 FSCA FPUL, FRn {:
  1133     CHECKFPUEN();
  1134     if( !IS_FPU_DOUBLEPREC() ) {
  1135 	sh4_fsca( FPULi, &(DRF(FRn>>1)) );
  1136 	/*
  1137         float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  1138         FR(FRn) = sinf(angle);
  1139         FR((FRn)+1) = cosf(angle);
  1140 	*/
  1142 :}
  1143 FTRV XMTRX, FVn {:
  1144     CHECKFPUEN();
  1145     if( !IS_FPU_DOUBLEPREC() ) {
  1146 	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
  1147 	/*
  1148         tmp = FVn<<2;
  1149 	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
  1150         float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  1151         FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
  1152 	    xf[9]*fv[2] + xf[13]*fv[3];
  1153         FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
  1154 	    xf[8]*fv[2] + xf[12]*fv[3];
  1155         FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
  1156 	    xf[11]*fv[2] + xf[15]*fv[3];
  1157         FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
  1158 	    xf[10]*fv[2] + xf[14]*fv[3];
  1159 	*/
  1161 :}
  1162 UNDEF {:
  1163     UNDEF(ir);
  1164 :}
  1165 %%
  1166     sh4r.pc = sh4r.new_pc;
  1167     sh4r.new_pc += 2;
  1168     sh4r.in_delay_slot = 0;
  1169     return TRUE;
.