2 * $Id: aica.c,v 1.12 2006-01-12 11:30:19 nkeynes Exp $
4 * This is the core sound system (ie the bit which does the actual work)
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #define MODULE aica_module
22 #include "dreamcast.h"
30 MMIO_REGION_READ_DEFFN( AICA0 )
31 MMIO_REGION_READ_DEFFN( AICA1 )
32 MMIO_REGION_READ_DEFFN( AICA2 )
34 void aica_init( void );
35 void aica_reset( void );
36 void aica_start( void );
37 void aica_stop( void );
38 void aica_save_state( FILE *f );
39 int aica_load_state( FILE *f );
40 uint32_t aica_run_slice( uint32_t );
42 struct dreamcast_module aica_module = { "AICA", aica_init, aica_reset,
43 aica_start, aica_run_slice, aica_stop,
44 aica_save_state, aica_load_state };
47 * Initialize the AICA subsystem. Note requires that
49 void aica_init( void )
51 register_io_regions( mmio_list_spu );
56 audio_set_output( &esd_audio_driver, 44100, AUDIO_FMT_16BIT|AUDIO_FMT_STEREO );
59 void aica_reset( void )
62 aica_event(2); /* Pre-deliver a timer interrupt */
65 void aica_start( void )
71 * Keep track of what we've done so far this second, to try to keep the
72 * precision of samples/second.
75 uint32_t nanosecs_done = 0;
77 uint32_t aica_run_slice( uint32_t nanosecs )
79 /* Run arm instructions */
80 int reset = MMIO_READ( AICA2, AICA_RESET );
81 if( (reset & 1) == 0 ) { /* Running */
82 int num_samples = (nanosecs_done + nanosecs) / AICA_SAMPLE_RATE - samples_done;
83 num_samples = arm_run_slice( num_samples );
84 audio_mix_samples( num_samples );
86 samples_done += num_samples;
87 nanosecs_done += nanosecs;
89 if( nanosecs_done > 1000000000 ) {
90 samples_done -= AICA_SAMPLE_RATE;
91 nanosecs_done -= 1000000000;
96 void aica_stop( void )
101 void aica_save_state( FILE *f )
106 int aica_load_state( FILE *f )
108 return arm_load_state( f );
111 int aica_event_pending = 0;
112 int aica_clear_count = 0;
114 /* Note: This is probably not necessarily technically correct but it should
115 * work in the meantime.
118 void aica_event( int event )
120 if( aica_event_pending == 0 )
121 armr.int_pending |= CPSR_F;
122 aica_event_pending |= (1<<event);
124 int pending = MMIO_READ( AICA2, AICA_IRQ );
125 if( pending == 0 || event < pending )
126 MMIO_WRITE( AICA2, AICA_IRQ, event );
129 void aica_clear_event( )
132 if( aica_clear_count == 4 ) {
134 aica_clear_count = 0;
136 for( i=0; i<8; i++ ) {
137 if( aica_event_pending & (1<<i) ) {
138 aica_event_pending &= ~(1<<i);
143 if( aica_event_pending & (1<<i) ) {
144 MMIO_WRITE( AICA2, AICA_IRQ, i );
148 if( aica_event_pending == 0 )
149 armr.int_pending &= ~CPSR_F;
153 /** Channel register structure:
154 * 00 4 Channel config
155 * 04 4 Waveform address lo (16 bits)
156 * 08 4 Loop start address
157 * 0C 4 Loop end address
158 * 10 4 Volume envelope
160 * 18 4 Frequency (floating point)
173 /* Write to channels 0-31 */
174 void mmio_region_AICA0_write( uint32_t reg, uint32_t val )
176 MMIO_WRITE( AICA0, reg, val );
177 aica_write_channel( reg >> 7, reg % 128, val );
178 // DEBUG( "AICA0 Write %08X => %08X", val, reg );
181 /* Write to channels 32-64 */
182 void mmio_region_AICA1_write( uint32_t reg, uint32_t val )
184 MMIO_WRITE( AICA1, reg, val );
185 aica_write_channel( (reg >> 7) + 32, reg % 128, val );
186 // DEBUG( "AICA1 Write %08X => %08X", val, reg );
190 * AICA control registers
192 void mmio_region_AICA2_write( uint32_t reg, uint32_t val )
197 tmp = MMIO_READ( AICA2, AICA_RESET );
198 if( (tmp & 1) == 1 && (val & 1) == 0 ) {
199 /* ARM enabled - execute a core reset */
200 DEBUG( "ARM enabled" );
204 } else if( (tmp&1) == 0 && (val&1) == 1 ) {
205 DEBUG( "ARM disabled" );
207 MMIO_WRITE( AICA2, AICA_RESET, val );
213 MMIO_WRITE( AICA2, reg, val );
219 * Translate the channel frequency to a sample rate. The frequency is a
220 * 14-bit floating point number, where bits 0..9 is the mantissa,
221 * 11..14 is the signed exponent (-8 to +7). Bit 10 appears to
224 * @return sample rate in samples per second.
226 uint32_t aica_frequency_to_sample_rate( uint32_t freq )
228 uint32_t exponent = (freq & 0x3800) >> 11;
229 uint32_t mantissa = freq & 0x03FF;
230 if( freq & 0x4000 ) {
231 /* neg exponent - rate < 44100 */
232 exponent = 8 - exponent;
233 return (44100 >> exponent) +
234 ((44100 * mantissa) >> (10+exponent));
236 /* pos exponent - rate > 44100 */
237 return (44100 << exponent) +
238 ((44100 * mantissa) >> (10-exponent));
242 void aica_write_channel( int channelNo, uint32_t reg, uint32_t val )
245 audio_channel_t channel = audio_get_channel(channelNo);
247 case 0x00: /* Config + high address bits*/
248 channel->start = (channel->start & 0xFFFF) | ((val&0x1F) << 16);
250 channel->loop = TRUE;
252 channel->loop = FALSE;
253 switch( (val >> 7) & 0x03 ) {
255 channel->sample_format = AUDIO_FMT_16BIT;
258 channel->sample_format = AUDIO_FMT_8BIT;
262 channel->sample_format = AUDIO_FMT_ADPCM;
265 switch( (val >> 14) & 0x03 ) {
267 audio_stop_channel( channelNo );
270 audio_start_channel( channelNo );
277 case 0x04: /* Low 16 address bits */
278 channel->start = (channel->start & 0x001F0000) | val;
280 case 0x08: /* Loop start */
281 channel->loop_start = val;
286 case 0x10: /* Envelope register 1 */
288 case 0x14: /* Envelope register 2 */
290 case 0x18: /* Frequency */
291 channel->sample_rate = aica_frequency_to_sample_rate ( val );
295 case 0x24: /* Volume? /pan */
297 case 0x28: /* Volume */
298 channel->vol_left = channel->vol_right = val & 0xFF;
.