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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 945:787729653236
prev939:6f2302afeb89
next946:d41ee7994db7
author nkeynes
date Mon Jan 05 04:19:46 2009 +0000 (11 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Move address space decls to mmu.h
Finally remove sh4_read_long and friends
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <assert.h>
    22 #include <math.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "eventq.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/sh4stat.h"
    32 #include "sh4/mmu.h"
    34 #define SH4_CALLTRACE 1
    36 #define MAX_INT 0x7FFFFFFF
    37 #define MIN_INT 0x80000000
    38 #define MAX_INTF 2147483647.0
    39 #define MIN_INTF -2147483648.0
    41 /********************** SH4 Module Definition ****************************/
    43 uint32_t sh4_emulate_run_slice( uint32_t nanosecs ) 
    44 {
    45     int i;
    47     if( sh4_breakpoint_count == 0 ) {
    48 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    49 	    if( SH4_EVENT_PENDING() ) {
    50 		if( sh4r.event_types & PENDING_EVENT ) {
    51 		    event_execute();
    52 		}
    53 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    54 		if( sh4r.event_types & PENDING_IRQ ) {
    55 		    sh4_accept_interrupt();
    56 		}
    57 	    }
    58 	    if( !sh4_execute_instruction() ) {
    59 		break;
    60 	    }
    61 	}
    62     } else {
    63 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    64 	    if( SH4_EVENT_PENDING() ) {
    65 		if( sh4r.event_types & PENDING_EVENT ) {
    66 		    event_execute();
    67 		}
    68 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    69 		if( sh4r.event_types & PENDING_IRQ ) {
    70 		    sh4_accept_interrupt();
    71 		}
    72 	    }
    74 	    if( !sh4_execute_instruction() )
    75 		break;
    76 #ifdef ENABLE_DEBUG_MODE
    77 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    78 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    79 		    break;
    80 		}
    81 	    }
    82 	    if( i != sh4_breakpoint_count ) {
    83 	    	sh4_core_exit( CORE_EXIT_BREAKPOINT );
    84 	    }
    85 #endif	
    86 	}
    87     }
    89     /* If we aborted early, but the cpu is still technically running,
    90      * we're doing a hard abort - cut the timeslice back to what we
    91      * actually executed
    92      */
    93     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
    94 	nanosecs = sh4r.slice_cycle;
    95     }
    96     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
    97 	TMU_run_slice( nanosecs );
    98 	SCIF_run_slice( nanosecs );
    99     }
   100     return nanosecs;
   101 }
   103 /********************** SH4 emulation core  ****************************/
   105 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   106 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }while(0)
   108 #if(SH4_CALLTRACE == 1)
   109 #define MAX_CALLSTACK 32
   110 static struct call_stack {
   111     sh4addr_t call_addr;
   112     sh4addr_t target_addr;
   113     sh4addr_t stack_pointer;
   114 } call_stack[MAX_CALLSTACK];
   116 static int call_stack_depth = 0;
   117 int sh4_call_trace_on = 0;
   119 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   120 {
   121     if( call_stack_depth < MAX_CALLSTACK ) {
   122 	call_stack[call_stack_depth].call_addr = source;
   123 	call_stack[call_stack_depth].target_addr = dest;
   124 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   125     }
   126     call_stack_depth++;
   127 }
   129 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   130 {
   131     if( call_stack_depth > 0 ) {
   132 	call_stack_depth--;
   133     }
   134 }
   136 void fprint_stack_trace( FILE *f )
   137 {
   138     int i = call_stack_depth -1;
   139     if( i >= MAX_CALLSTACK )
   140 	i = MAX_CALLSTACK - 1;
   141     for( ; i >= 0; i-- ) {
   142 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   143 		 (call_stack_depth - i), call_stack[i].call_addr,
   144 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   145     }
   146 }
   148 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   149 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   150 #else
   151 #define TRACE_CALL( dest, rts ) 
   152 #define TRACE_RETURN( source, dest )
   153 #endif
   155 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   156 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   157 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   158 #define CHECKRALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   159 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   160 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   161 #define CHECKWALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   163 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   164 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }
   165 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   167 #define ADDRSPACE (IS_SH4_PRIVMODE() ? sh4_address_space : sh4_user_address_space)
   168 #define SQADDRSPACE (IS_SH4_PRIVMODE() ? storequeue_address_space : storequeue_user_address_space)
   170 #ifdef HAVE_FRAME_ADDRESS
   171 static FASTCALL __attribute__((noinline)) void *__first_arg(void *a, void *b) { return a; }
   172 #define INIT_EXCEPTIONS(label) goto *__first_arg(&&fnstart,&&label); fnstart:
   173 #define MEM_READ_BYTE( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_byte)((addr), &&except)
   174 #define MEM_READ_WORD( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_word)((addr), &&except)
   175 #define MEM_READ_LONG( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_long)((addr), &&except)
   176 #define MEM_WRITE_BYTE( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_byte)((addr), (val), &&except)
   177 #define MEM_WRITE_WORD( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_word)((addr), (val), &&except)
   178 #define MEM_WRITE_LONG( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_long)((addr), (val), &&except)
   179 #else
   180 #define INIT_EXCEPTIONS(label)
   181 #define MEM_READ_BYTE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte(addr)
   182 #define MEM_READ_WORD( addr, val ) val = ADDRSPACE[(addr)>>12]->read_word(addr)
   183 #define MEM_READ_LONG( addr, val ) val = ADDRSPACE[(addr)>>12]->read_long(addr)
   184 #define MEM_WRITE_BYTE( addr, val ) ADDRSPACE[(addr)>>12]->write_byte(addr, val)
   185 #define MEM_WRITE_WORD( addr, val ) ADDRSPACE[(addr)>>12]->write_word(addr, val)
   186 #define MEM_WRITE_LONG( addr, val ) ADDRSPACE[(addr)>>12]->write_long(addr, val)
   187 #endif
   193 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   195 #define MEM_FP_READ( addr, reg ) \
   196     if( IS_FPU_DOUBLESIZE() ) { \
   197 	CHECKRALIGN64(addr); \
   198         if( reg & 1 ) { \
   199             MEM_READ_LONG( addr, *((uint32_t *)&XF((reg) & 0x0E)) ); \
   200             MEM_READ_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
   201         } else { \
   202             MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   203             MEM_READ_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
   204 	} \
   205     } else { \
   206         CHECKRALIGN32(addr); \
   207         MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   208     }
   209 #define MEM_FP_WRITE( addr, reg ) \
   210     if( IS_FPU_DOUBLESIZE() ) { \
   211         CHECKWALIGN64(addr); \
   212         if( reg & 1 ) { \
   213 	    MEM_WRITE_LONG( addr, *((uint32_t *)&XF((reg)&0x0E)) ); \
   214 	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
   215         } else { \
   216 	    MEM_WRITE_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   217 	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
   218 	} \
   219     } else { \
   220     	CHECKWALIGN32(addr); \
   221         MEM_WRITE_LONG(addr, *((uint32_t *)&FR((reg))) ); \
   222     }
   224 gboolean sh4_execute_instruction( void )
   225 {
   226     uint32_t pc;
   227     unsigned short ir;
   228     uint32_t tmp;
   229     float ftmp;
   230     double dtmp;
   231     int64_t memtmp; // temporary holder for memory reads
   233     INIT_EXCEPTIONS(except)
   235 #define R0 sh4r.r[0]
   236     pc = sh4r.pc;
   237     if( pc > 0xFFFFFF00 ) {
   238 	/* SYSCALL Magic */
   239 	syscall_invoke( pc );
   240 	sh4r.in_delay_slot = 0;
   241 	pc = sh4r.pc = sh4r.pr;
   242 	sh4r.new_pc = sh4r.pc + 2;
   243         return TRUE;
   244     }
   245     CHECKRALIGN16(pc);
   247 #ifdef ENABLE_SH4STATS
   248     sh4_stats_add_by_pc(sh4r.pc);
   249 #endif
   251     /* Read instruction */
   252     if( !IS_IN_ICACHE(pc) ) {
   253 	if( !mmu_update_icache(pc) ) {
   254 	    // Fault - look for the fault handler
   255 	    if( !mmu_update_icache(sh4r.pc) ) {
   256 		// double fault - halt
   257 		ERROR( "Double fault - halting" );
   258 		sh4_core_exit(CORE_EXIT_HALT);
   259 		return FALSE;
   260 	    }
   261 	}
   262 	pc = sh4r.pc;
   263     }
   264     assert( IS_IN_ICACHE(pc) );
   265     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   266 %%
   267 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   268 AND #imm, R0 {: R0 &= imm; :}
   269  AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
   270 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   271 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   272 OR #imm, R0  {: R0 |= imm; :}
   273  OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
   274 TAS.B @Rn {:
   275     MEM_READ_BYTE( sh4r.r[Rn], tmp );
   276     sh4r.t = ( tmp == 0 ? 1 : 0 );
   277     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   278 :}
   279 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   280 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   281  TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
   282 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   283 XOR #imm, R0 {: R0 ^= imm; :}
   284  XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
   285 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   287 ROTL Rn {:
   288     sh4r.t = sh4r.r[Rn] >> 31;
   289     sh4r.r[Rn] <<= 1;
   290     sh4r.r[Rn] |= sh4r.t;
   291 :}
   292 ROTR Rn {:
   293     sh4r.t = sh4r.r[Rn] & 0x00000001;
   294     sh4r.r[Rn] >>= 1;
   295     sh4r.r[Rn] |= (sh4r.t << 31);
   296 :}
   297 ROTCL Rn {:
   298     tmp = sh4r.r[Rn] >> 31;
   299     sh4r.r[Rn] <<= 1;
   300     sh4r.r[Rn] |= sh4r.t;
   301     sh4r.t = tmp;
   302 :}
   303 ROTCR Rn {:
   304     tmp = sh4r.r[Rn] & 0x00000001;
   305     sh4r.r[Rn] >>= 1;
   306     sh4r.r[Rn] |= (sh4r.t << 31 );
   307     sh4r.t = tmp;
   308 :}
   309 SHAD Rm, Rn {:
   310     tmp = sh4r.r[Rm];
   311     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   312     else if( (tmp & 0x1F) == 0 )  
   313         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   314     else 
   315 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   316 :}
   317 SHLD Rm, Rn {:
   318     tmp = sh4r.r[Rm];
   319     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   320     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   321     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   322 :}
   323 SHAL Rn {:
   324     sh4r.t = sh4r.r[Rn] >> 31;
   325     sh4r.r[Rn] <<= 1;
   326 :}
   327 SHAR Rn {:
   328     sh4r.t = sh4r.r[Rn] & 0x00000001;
   329     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   330 :}
   331 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   332 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   333 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   334 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   335 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   336 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   337 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   338 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   340 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   341 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   342 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   343 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   344 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   345 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   347 CLRT {: sh4r.t = 0; :}
   348 SETT {: sh4r.t = 1; :}
   349 CLRMAC {: sh4r.mac = 0; :}
   350 LDTLB {: MMU_ldtlb(); :}
   351 CLRS {: sh4r.s = 0; :}
   352 SETS {: sh4r.s = 1; :}
   353 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   354 NOP {: /* NOP */ :}
   356 PREF @Rn {:
   357      tmp = sh4r.r[Rn];
   358      if( (tmp & 0xFC000000) == 0xE0000000 ) {
   359 	 sh4_flush_store_queue(tmp);
   360      }
   361 :}
   362 OCBI @Rn {: :}
   363 OCBP @Rn {: :}
   364 OCBWB @Rn {: :}
   365 MOVCA.L R0, @Rn {:
   366     tmp = sh4r.r[Rn];
   367     CHECKWALIGN32(tmp);
   368     MEM_WRITE_LONG( tmp, R0 );
   369 :}
   370 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   371 MOV.W Rm, @(R0, Rn) {: 
   372     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   373     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   374 :}
   375 MOV.L Rm, @(R0, Rn) {:
   376     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   377     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   378 :}
   379 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
   380 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   381     MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   382 :}
   383 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   384     MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   385 :}
   386 MOV.L Rm, @(disp, Rn) {:
   387     tmp = sh4r.r[Rn] + disp;
   388     CHECKWALIGN32( tmp );
   389     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   390 :}
   391 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   392 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   393 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   394  MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
   395  MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
   396  MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
   397 MOV.L @(disp, Rm), Rn {:
   398     tmp = sh4r.r[Rm] + disp;
   399     CHECKRALIGN32( tmp );
   400     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   401 :}
   402 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
   403  MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
   404  MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
   405 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   406  MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
   407  MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
   408  MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
   409 MOV.L @(disp, PC), Rn {:
   410     CHECKSLOTILLEGAL();
   411     tmp = (pc&0xFFFFFFFC) + disp + 4;
   412     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   413 :}
   414 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   415 MOV.W R0, @(disp, GBR) {:
   416     tmp = sh4r.gbr + disp;
   417     CHECKWALIGN16( tmp );
   418     MEM_WRITE_WORD( tmp, R0 );
   419 :}
   420 MOV.L R0, @(disp, GBR) {:
   421     tmp = sh4r.gbr + disp;
   422     CHECKWALIGN32( tmp );
   423     MEM_WRITE_LONG( tmp, R0 );
   424 :}
   425  MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
   426 MOV.W @(disp, GBR), R0 {: 
   427     tmp = sh4r.gbr + disp;
   428     CHECKRALIGN16( tmp );
   429     MEM_READ_WORD( tmp, R0 );
   430 :}
   431 MOV.L @(disp, GBR), R0 {:
   432     tmp = sh4r.gbr + disp;
   433     CHECKRALIGN32( tmp );
   434     MEM_READ_LONG( tmp, R0 );
   435 :}
   436 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   437 MOV.W R0, @(disp, Rn) {: 
   438     tmp = sh4r.r[Rn] + disp;
   439     CHECKWALIGN16( tmp );
   440     MEM_WRITE_WORD( tmp, R0 );
   441 :}
   442  MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
   443 MOV.W @(disp, Rm), R0 {: 
   444     tmp = sh4r.r[Rm] + disp;
   445     CHECKRALIGN16( tmp );
   446     MEM_READ_WORD( tmp, R0 );
   447 :}
   448 MOV.W @(disp, PC), Rn {:
   449     CHECKSLOTILLEGAL();
   450     tmp = pc + 4 + disp;
   451     MEM_READ_WORD( tmp, sh4r.r[Rn] );
   452 :}
   453 MOVA @(disp, PC), R0 {:
   454     CHECKSLOTILLEGAL();
   455     R0 = (pc&0xFFFFFFFC) + disp + 4;
   456 :}
   457 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   459 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
   460 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
   461 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
   462 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
   463 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
   464  FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
   465 FMOV FRm, FRn {: 
   466     if( IS_FPU_DOUBLESIZE() )
   467 	DR(FRn) = DR(FRm);
   468     else
   469 	FR(FRn) = FR(FRm);
   470 :}
   472 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   473 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   474 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   475 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   476 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   477 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   478 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   479 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   480 CMP/STR Rm, Rn {: 
   481     /* set T = 1 if any byte in RM & RN is the same */
   482     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   483     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   484              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   485 :}
   487 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   488 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   489 ADDC Rm, Rn {:
   490     tmp = sh4r.r[Rn];
   491     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   492     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   493 :}
   494 ADDV Rm, Rn {:
   495     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   496     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   497     sh4r.r[Rn] = tmp;
   498 :}
   499 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   500 DIV0S Rm, Rn {: 
   501     sh4r.q = sh4r.r[Rn]>>31;
   502     sh4r.m = sh4r.r[Rm]>>31;
   503     sh4r.t = sh4r.q ^ sh4r.m;
   504 :}
   505 DIV1 Rm, Rn {:
   506     /* This is derived from the sh4 manual with some simplifications */
   507     uint32_t tmp0, tmp1, tmp2, dir;
   509     dir = sh4r.q ^ sh4r.m;
   510     sh4r.q = (sh4r.r[Rn] >> 31);
   511     tmp2 = sh4r.r[Rm];
   512     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   513     tmp0 = sh4r.r[Rn];
   514     if( dir ) {
   515          sh4r.r[Rn] += tmp2;
   516          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   517     } else {
   518          sh4r.r[Rn] -= tmp2;
   519          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   520     }
   521     sh4r.q ^= sh4r.m ^ tmp1;
   522     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   523 :}
   524 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   525 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   526 DT Rn {:
   527     sh4r.r[Rn] --;
   528     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   529 :}
   530 MAC.W @Rm+, @Rn+ {:
   531     int32_t stmp;
   532     if( Rm == Rn ) {
   533 	CHECKRALIGN16(sh4r.r[Rn]);
   534 	MEM_READ_WORD( sh4r.r[Rn], tmp );
   535 	stmp = SIGNEXT16(tmp);
   536 	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
   537 	stmp *= SIGNEXT16(tmp);
   538 	sh4r.r[Rn] += 4;
   539     } else {
   540 	CHECKRALIGN16( sh4r.r[Rn] );
   541 	CHECKRALIGN16( sh4r.r[Rm] );
   542 	MEM_READ_WORD(sh4r.r[Rn], tmp);
   543 	stmp = SIGNEXT16(tmp);
   544 	MEM_READ_WORD(sh4r.r[Rm], tmp);
   545 	stmp = stmp * SIGNEXT16(tmp);
   546 	sh4r.r[Rn] += 2;
   547 	sh4r.r[Rm] += 2;
   548     }
   549     if( sh4r.s ) {
   550 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   551 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   552 	    sh4r.mac = 0x000000017FFFFFFFLL;
   553 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   554 	    sh4r.mac = 0x0000000180000000LL;
   555 	} else {
   556 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   557 		((uint32_t)(sh4r.mac + stmp));
   558 	}
   559     } else {
   560 	sh4r.mac += SIGNEXT32(stmp);
   561     }
   562 :}
   563 MAC.L @Rm+, @Rn+ {:
   564     int64_t tmpl;
   565     if( Rm == Rn ) {
   566 	CHECKRALIGN32( sh4r.r[Rn] );
   567 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   568 	tmpl = SIGNEXT32(tmp);
   569 	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
   570 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   571 	sh4r.r[Rn] += 8;
   572     } else {
   573 	CHECKRALIGN32( sh4r.r[Rm] );
   574 	CHECKRALIGN32( sh4r.r[Rn] );
   575 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   576 	tmpl = SIGNEXT32(tmp);
   577 	MEM_READ_LONG(sh4r.r[Rm], tmp);
   578 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   579 	sh4r.r[Rn] += 4;
   580 	sh4r.r[Rm] += 4;
   581     }
   582     if( sh4r.s ) {
   583         /* 48-bit Saturation. Yuch */
   584         if( tmpl < (int64_t)0xFFFF800000000000LL )
   585             tmpl = 0xFFFF800000000000LL;
   586         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   587             tmpl = 0x00007FFFFFFFFFFFLL;
   588     }
   589     sh4r.mac = tmpl;
   590 :}
   591 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   592                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   593 MULU.W Rm, Rn {:
   594     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   595                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   596 :}
   597 MULS.W Rm, Rn {:
   598     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   599                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   600 :}
   601 NEGC Rm, Rn {:
   602     tmp = 0 - sh4r.r[Rm];
   603     sh4r.r[Rn] = tmp - sh4r.t;
   604     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   605 :}
   606 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   607 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   608 SUBC Rm, Rn {: 
   609     tmp = sh4r.r[Rn];
   610     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   611     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   612 :}
   614 BRAF Rn {:
   615      CHECKSLOTILLEGAL();
   616      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   617      sh4r.in_delay_slot = 1;
   618      sh4r.pc = sh4r.new_pc;
   619      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   620      return TRUE;
   621 :}
   622 BSRF Rn {:
   623      CHECKSLOTILLEGAL();
   624      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   625      sh4r.in_delay_slot = 1;
   626      sh4r.pr = sh4r.pc + 4;
   627      sh4r.pc = sh4r.new_pc;
   628      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   629      TRACE_CALL( pc, sh4r.new_pc );
   630      return TRUE;
   631 :}
   632 BT disp {:
   633     CHECKSLOTILLEGAL();
   634     if( sh4r.t ) {
   635         CHECKDEST( sh4r.pc + disp + 4 )
   636         sh4r.pc += disp + 4;
   637         sh4r.new_pc = sh4r.pc + 2;
   638         return TRUE;
   639     }
   640 :}
   641 BF disp {:
   642     CHECKSLOTILLEGAL();
   643     if( !sh4r.t ) {
   644         CHECKDEST( sh4r.pc + disp + 4 )
   645         sh4r.pc += disp + 4;
   646         sh4r.new_pc = sh4r.pc + 2;
   647         return TRUE;
   648     }
   649 :}
   650 BT/S disp {:
   651     CHECKSLOTILLEGAL();
   652     if( sh4r.t ) {
   653         CHECKDEST( sh4r.pc + disp + 4 )
   654         sh4r.in_delay_slot = 1;
   655         sh4r.pc = sh4r.new_pc;
   656         sh4r.new_pc = pc + disp + 4;
   657         sh4r.in_delay_slot = 1;
   658         return TRUE;
   659     }
   660 :}
   661 BF/S disp {:
   662     CHECKSLOTILLEGAL();
   663     if( !sh4r.t ) {
   664         CHECKDEST( sh4r.pc + disp + 4 )
   665         sh4r.in_delay_slot = 1;
   666         sh4r.pc = sh4r.new_pc;
   667         sh4r.new_pc = pc + disp + 4;
   668         return TRUE;
   669     }
   670 :}
   671 BRA disp {:
   672     CHECKSLOTILLEGAL();
   673     CHECKDEST( sh4r.pc + disp + 4 );
   674     sh4r.in_delay_slot = 1;
   675     sh4r.pc = sh4r.new_pc;
   676     sh4r.new_pc = pc + 4 + disp;
   677     return TRUE;
   678 :}
   679 BSR disp {:
   680     CHECKDEST( sh4r.pc + disp + 4 );
   681     CHECKSLOTILLEGAL();
   682     sh4r.in_delay_slot = 1;
   683     sh4r.pr = pc + 4;
   684     sh4r.pc = sh4r.new_pc;
   685     sh4r.new_pc = pc + 4 + disp;
   686     TRACE_CALL( pc, sh4r.new_pc );
   687     return TRUE;
   688 :}
   689 TRAPA #imm {:
   690     CHECKSLOTILLEGAL();
   691     sh4r.pc += 2;
   692     sh4_raise_trap( imm );
   693     return TRUE;
   694 :}
   695 RTS {: 
   696     CHECKSLOTILLEGAL();
   697     CHECKDEST( sh4r.pr );
   698     sh4r.in_delay_slot = 1;
   699     sh4r.pc = sh4r.new_pc;
   700     sh4r.new_pc = sh4r.pr;
   701     TRACE_RETURN( pc, sh4r.new_pc );
   702     return TRUE;
   703 :}
   704 SLEEP {:
   705     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   706 	sh4r.sh4_state = SH4_STATE_STANDBY;
   707     } else {
   708 	sh4r.sh4_state = SH4_STATE_SLEEP;
   709     }
   710     return FALSE; /* Halt CPU */
   711 :}
   712 RTE {:
   713     CHECKPRIV();
   714     CHECKDEST( sh4r.spc );
   715     CHECKSLOTILLEGAL();
   716     sh4r.in_delay_slot = 1;
   717     sh4r.pc = sh4r.new_pc;
   718     sh4r.new_pc = sh4r.spc;
   719     sh4_write_sr( sh4r.ssr );
   720     return TRUE;
   721 :}
   722 JMP @Rn {:
   723     CHECKDEST( sh4r.r[Rn] );
   724     CHECKSLOTILLEGAL();
   725     sh4r.in_delay_slot = 1;
   726     sh4r.pc = sh4r.new_pc;
   727     sh4r.new_pc = sh4r.r[Rn];
   728     return TRUE;
   729 :}
   730 JSR @Rn {:
   731     CHECKDEST( sh4r.r[Rn] );
   732     CHECKSLOTILLEGAL();
   733     sh4r.in_delay_slot = 1;
   734     sh4r.pc = sh4r.new_pc;
   735     sh4r.new_pc = sh4r.r[Rn];
   736     sh4r.pr = pc + 4;
   737     TRACE_CALL( pc, sh4r.new_pc );
   738     return TRUE;
   739 :}
   740 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   741 STS.L MACH, @-Rn {:
   742     CHECKWALIGN32( sh4r.r[Rn] );
   743     MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
   744     sh4r.r[Rn] -= 4;
   745 :}
   746 STC.L SR, @-Rn {:
   747     CHECKPRIV();
   748     CHECKWALIGN32( sh4r.r[Rn] );
   749     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
   750     sh4r.r[Rn] -= 4;
   751 :}
   752 LDS.L @Rm+, MACH {:
   753     CHECKRALIGN32( sh4r.r[Rm] );
   754     MEM_READ_LONG(sh4r.r[Rm], tmp);
   755     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   756 	(((uint64_t)tmp)<<32);
   757     sh4r.r[Rm] += 4;
   758 :}
   759 LDC.L @Rm+, SR {:
   760     CHECKSLOTILLEGAL();
   761     CHECKPRIV();
   762     CHECKWALIGN32( sh4r.r[Rm] );
   763     MEM_READ_LONG(sh4r.r[Rm], tmp);
   764     sh4_write_sr( tmp );
   765     sh4r.r[Rm] +=4;
   766 :}
   767 LDS Rm, MACH {:
   768     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   769                (((uint64_t)sh4r.r[Rm])<<32);
   770 :}
   771 LDC Rm, SR {:
   772     CHECKSLOTILLEGAL();
   773     CHECKPRIV();
   774     sh4_write_sr( sh4r.r[Rm] );
   775 :}
   776 LDC Rm, SGR {:
   777     CHECKPRIV();
   778     sh4r.sgr = sh4r.r[Rm];
   779 :}
   780 LDC.L @Rm+, SGR {:
   781     CHECKPRIV();
   782     CHECKRALIGN32( sh4r.r[Rm] );
   783     MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
   784     sh4r.r[Rm] +=4;
   785 :}
   786 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   787 STS.L MACL, @-Rn {:
   788     CHECKWALIGN32( sh4r.r[Rn] );
   789     MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
   790     sh4r.r[Rn] -= 4;
   791 :}
   792 STC.L GBR, @-Rn {:
   793     CHECKWALIGN32( sh4r.r[Rn] );
   794     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
   795     sh4r.r[Rn] -= 4;
   796 :}
   797 LDS.L @Rm+, MACL {:
   798     CHECKRALIGN32( sh4r.r[Rm] );
   799     MEM_READ_LONG(sh4r.r[Rm], tmp);
   800     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   801                (uint64_t)((uint32_t)tmp);
   802     sh4r.r[Rm] += 4;
   803 :}
   804 LDC.L @Rm+, GBR {:
   805     CHECKRALIGN32( sh4r.r[Rm] );
   806     MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
   807     sh4r.r[Rm] +=4;
   808 :}
   809 LDS Rm, MACL {:
   810     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   811                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   812 :}
   813 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   814 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   815 STS.L PR, @-Rn {:
   816     CHECKWALIGN32( sh4r.r[Rn] );
   817     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
   818     sh4r.r[Rn] -= 4;
   819 :}
   820 STC.L VBR, @-Rn {:
   821     CHECKPRIV();
   822     CHECKWALIGN32( sh4r.r[Rn] );
   823     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
   824     sh4r.r[Rn] -= 4;
   825 :}
   826 LDS.L @Rm+, PR {:
   827     CHECKRALIGN32( sh4r.r[Rm] );
   828     MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
   829     sh4r.r[Rm] += 4;
   830 :}
   831 LDC.L @Rm+, VBR {:
   832     CHECKPRIV();
   833     CHECKRALIGN32( sh4r.r[Rm] );
   834     MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
   835     sh4r.r[Rm] +=4;
   836 :}
   837 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   838 LDC Rm, VBR {:
   839     CHECKPRIV();
   840     sh4r.vbr = sh4r.r[Rm];
   841 :}
   842 STC SGR, Rn {:
   843     CHECKPRIV();
   844     sh4r.r[Rn] = sh4r.sgr;
   845 :}
   846 STC.L SGR, @-Rn {:
   847     CHECKPRIV();
   848     CHECKWALIGN32( sh4r.r[Rn] );
   849     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
   850     sh4r.r[Rn] -= 4;
   851 :}
   852 STC.L SSR, @-Rn {:
   853     CHECKPRIV();
   854     CHECKWALIGN32( sh4r.r[Rn] );
   855     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
   856     sh4r.r[Rn] -= 4;
   857 :}
   858 LDC.L @Rm+, SSR {:
   859     CHECKPRIV();
   860     CHECKRALIGN32( sh4r.r[Rm] );
   861     MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
   862     sh4r.r[Rm] +=4;
   863 :}
   864 LDC Rm, SSR {:
   865     CHECKPRIV();
   866     sh4r.ssr = sh4r.r[Rm];
   867 :}
   868 STC.L SPC, @-Rn {:
   869     CHECKPRIV();
   870     CHECKWALIGN32( sh4r.r[Rn] );
   871     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
   872     sh4r.r[Rn] -= 4;
   873 :}
   874 LDC.L @Rm+, SPC {:
   875     CHECKPRIV();
   876     CHECKRALIGN32( sh4r.r[Rm] );
   877     MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
   878     sh4r.r[Rm] +=4;
   879 :}
   880 LDC Rm, SPC {:
   881     CHECKPRIV();
   882     sh4r.spc = sh4r.r[Rm];
   883 :}
   884 STS FPUL, Rn {: 
   885     CHECKFPUEN();
   886     sh4r.r[Rn] = FPULi; 
   887 :}
   888 STS.L FPUL, @-Rn {:
   889     CHECKFPUEN();
   890     CHECKWALIGN32( sh4r.r[Rn] );
   891     MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
   892     sh4r.r[Rn] -= 4;
   893 :}
   894 LDS.L @Rm+, FPUL {:
   895     CHECKFPUEN();
   896     CHECKRALIGN32( sh4r.r[Rm] );
   897     MEM_READ_LONG(sh4r.r[Rm], FPULi);
   898     sh4r.r[Rm] +=4;
   899 :}
   900 LDS Rm, FPUL {:
   901     CHECKFPUEN();
   902     FPULi = sh4r.r[Rm]; 
   903 :}
   904 STS FPSCR, Rn {: 
   905     CHECKFPUEN();
   906     sh4r.r[Rn] = sh4r.fpscr; 
   907 :}
   908 STS.L FPSCR, @-Rn {:
   909     CHECKFPUEN();
   910     CHECKWALIGN32( sh4r.r[Rn] );
   911     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
   912     sh4r.r[Rn] -= 4;
   913 :}
   914 LDS.L @Rm+, FPSCR {:
   915     CHECKFPUEN();
   916     CHECKRALIGN32( sh4r.r[Rm] );
   917     MEM_READ_LONG(sh4r.r[Rm], tmp);
   918     sh4r.r[Rm] +=4;
   919     sh4_write_fpscr( tmp );
   920 :}
   921 LDS Rm, FPSCR {: 
   922     CHECKFPUEN();
   923     sh4_write_fpscr( sh4r.r[Rm] );
   924 :}
   925 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
   926 STC.L DBR, @-Rn {:
   927     CHECKPRIV();
   928     CHECKWALIGN32( sh4r.r[Rn] );
   929     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
   930     sh4r.r[Rn] -= 4;
   931 :}
   932 LDC.L @Rm+, DBR {:
   933     CHECKPRIV();
   934     CHECKRALIGN32( sh4r.r[Rm] );
   935     MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
   936     sh4r.r[Rm] +=4;
   937 :}
   938 LDC Rm, DBR {:
   939     CHECKPRIV();
   940     sh4r.dbr = sh4r.r[Rm];
   941 :}
   942 STC.L Rm_BANK, @-Rn {:
   943     CHECKPRIV();
   944     CHECKWALIGN32( sh4r.r[Rn] );
   945     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
   946     sh4r.r[Rn] -= 4;
   947 :}
   948 LDC.L @Rm+, Rn_BANK {:
   949     CHECKPRIV();
   950     CHECKRALIGN32( sh4r.r[Rm] );
   951     MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
   952     sh4r.r[Rm] += 4;
   953 :}
   954 LDC Rm, Rn_BANK {:
   955     CHECKPRIV();
   956     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
   957 :}
   958 STC SR, Rn {: 
   959     CHECKPRIV();
   960     sh4r.r[Rn] = sh4_read_sr();
   961 :}
   962 STC GBR, Rn {:
   963     sh4r.r[Rn] = sh4r.gbr;
   964 :}
   965 STC VBR, Rn {:
   966     CHECKPRIV();
   967     sh4r.r[Rn] = sh4r.vbr;
   968 :}
   969 STC SSR, Rn {:
   970     CHECKPRIV();
   971     sh4r.r[Rn] = sh4r.ssr;
   972 :}
   973 STC SPC, Rn {:
   974     CHECKPRIV();
   975     sh4r.r[Rn] = sh4r.spc;
   976 :}
   977 STC Rm_BANK, Rn {:
   978     CHECKPRIV();
   979     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   980 :}
   982 FADD FRm, FRn {:
   983     CHECKFPUEN();
   984     if( IS_FPU_DOUBLEPREC() ) {
   985 	DR(FRn) += DR(FRm);
   986     } else {
   987 	FR(FRn) += FR(FRm);
   988     }
   989 :}
   990 FSUB FRm, FRn {:
   991     CHECKFPUEN();
   992     if( IS_FPU_DOUBLEPREC() ) {
   993 	DR(FRn) -= DR(FRm);
   994     } else {
   995 	FR(FRn) -= FR(FRm);
   996     }
   997 :}
   999 FMUL FRm, FRn {:
  1000     CHECKFPUEN();
  1001     if( IS_FPU_DOUBLEPREC() ) {
  1002 	DR(FRn) *= DR(FRm);
  1003     } else {
  1004 	FR(FRn) *= FR(FRm);
  1006 :}
  1008 FDIV FRm, FRn {:
  1009     CHECKFPUEN();
  1010     if( IS_FPU_DOUBLEPREC() ) {
  1011 	DR(FRn) /= DR(FRm);
  1012     } else {
  1013 	FR(FRn) /= FR(FRm);
  1015 :}
  1017 FCMP/EQ FRm, FRn {:
  1018     CHECKFPUEN();
  1019     if( IS_FPU_DOUBLEPREC() ) {
  1020 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1021     } else {
  1022 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1024 :}
  1026 FCMP/GT FRm, FRn {:
  1027     CHECKFPUEN();
  1028     if( IS_FPU_DOUBLEPREC() ) {
  1029 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1030     } else {
  1031 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1033 :}
  1035 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
  1036 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
  1037 FLOAT FPUL, FRn {: 
  1038     CHECKFPUEN();
  1039     if( IS_FPU_DOUBLEPREC() ) {
  1040 	if( FRn&1 ) { // No, really...
  1041 	    dtmp = (double)FPULi;
  1042 	    FR(FRn) = *(((float *)&dtmp)+1);
  1043 	} else {
  1044 	    DRF(FRn>>1) = (double)FPULi;
  1046     } else {
  1047 	FR(FRn) = (float)FPULi;
  1049 :}
  1050 FTRC FRm, FPUL {:
  1051     CHECKFPUEN();
  1052     if( IS_FPU_DOUBLEPREC() ) {
  1053 	if( FRm&1 ) {
  1054 	    dtmp = 0;
  1055 	    *(((float *)&dtmp)+1) = FR(FRm);
  1056 	} else {
  1057 	    dtmp = DRF(FRm>>1);
  1059         if( dtmp >= MAX_INTF )
  1060             FPULi = MAX_INT;
  1061         else if( dtmp <= MIN_INTF )
  1062             FPULi = MIN_INT;
  1063         else 
  1064             FPULi = (int32_t)dtmp;
  1065     } else {
  1066 	ftmp = FR(FRm);
  1067 	if( ftmp >= MAX_INTF )
  1068 	    FPULi = MAX_INT;
  1069 	else if( ftmp <= MIN_INTF )
  1070 	    FPULi = MIN_INT;
  1071 	else
  1072 	    FPULi = (int32_t)ftmp;
  1074 :}
  1075 FNEG FRn {:
  1076     CHECKFPUEN();
  1077     if( IS_FPU_DOUBLEPREC() ) {
  1078 	DR(FRn) = -DR(FRn);
  1079     } else {
  1080         FR(FRn) = -FR(FRn);
  1082 :}
  1083 FABS FRn {:
  1084     CHECKFPUEN();
  1085     if( IS_FPU_DOUBLEPREC() ) {
  1086 	DR(FRn) = fabs(DR(FRn));
  1087     } else {
  1088         FR(FRn) = fabsf(FR(FRn));
  1090 :}
  1091 FSQRT FRn {:
  1092     CHECKFPUEN();
  1093     if( IS_FPU_DOUBLEPREC() ) {
  1094 	DR(FRn) = sqrt(DR(FRn));
  1095     } else {
  1096         FR(FRn) = sqrtf(FR(FRn));
  1098 :}
  1099 FLDI0 FRn {:
  1100     CHECKFPUEN();
  1101     if( IS_FPU_DOUBLEPREC() ) {
  1102 	DR(FRn) = 0.0;
  1103     } else {
  1104         FR(FRn) = 0.0;
  1106 :}
  1107 FLDI1 FRn {:
  1108     CHECKFPUEN();
  1109     if( IS_FPU_DOUBLEPREC() ) {
  1110 	DR(FRn) = 1.0;
  1111     } else {
  1112         FR(FRn) = 1.0;
  1114 :}
  1115 FMAC FR0, FRm, FRn {:
  1116     CHECKFPUEN();
  1117     if( IS_FPU_DOUBLEPREC() ) {
  1118         DR(FRn) += DR(FRm)*DR(0);
  1119     } else {
  1120 	FR(FRn) += FR(FRm)*FR(0);
  1122 :}
  1123 FRCHG {: 
  1124     CHECKFPUEN(); 
  1125     sh4r.fpscr ^= FPSCR_FR; 
  1126     sh4_switch_fr_banks();
  1127 :}
  1128 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1129 FCNVSD FPUL, FRn {:
  1130     CHECKFPUEN();
  1131     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1132 	DR(FRn) = (double)FPULf;
  1134 :}
  1135 FCNVDS FRm, FPUL {:
  1136     CHECKFPUEN();
  1137     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1138 	FPULf = (float)DR(FRm);
  1140 :}
  1142 FSRRA FRn {:
  1143     CHECKFPUEN();
  1144     if( !IS_FPU_DOUBLEPREC() ) {
  1145 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1147 :}
  1148 FIPR FVm, FVn {:
  1149     CHECKFPUEN();
  1150     if( !IS_FPU_DOUBLEPREC() ) {
  1151         int tmp2 = FVn<<2;
  1152         tmp = FVm<<2;
  1153         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1154             FR(tmp+1)*FR(tmp2+1) +
  1155             FR(tmp+2)*FR(tmp2+2) +
  1156             FR(tmp+3)*FR(tmp2+3);
  1158 :}
  1159 FSCA FPUL, FRn {:
  1160     CHECKFPUEN();
  1161     if( !IS_FPU_DOUBLEPREC() ) {
  1162 	sh4_fsca( FPULi, (float *)&(DRF(FRn>>1)) );
  1163 	/*
  1164         float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  1165         FR(FRn) = sinf(angle);
  1166         FR((FRn)+1) = cosf(angle);
  1167 	*/
  1169 :}
  1170 FTRV XMTRX, FVn {:
  1171     CHECKFPUEN();
  1172     if( !IS_FPU_DOUBLEPREC() ) {
  1173 	sh4_ftrv((float *)&(DRF(FVn<<1)) );
  1175 :}
  1176 UNDEF {:
  1177     UNDEF(ir);
  1178 :}
  1179 %%
  1180     sh4r.pc = sh4r.new_pc;
  1181     sh4r.new_pc += 2;
  1183 except:
  1184     sh4r.in_delay_slot = 0;
  1185     return TRUE;
.