lxdream 0.9.1| filename | src/sh4/sh4stat.in |
| changeset | 945:787729653236 |
| prev | 905:4c17ebd9ef5e |
| next | 1074:397d77b6e346 |
| author | nkeynes |
| date | Mon Jan 05 04:19:46 2009 +0000 (15 years ago) |
| branch | lxdream-mem |
| permissions | -rw-r--r-- |
| last change | Move address space decls to mmu.h Finally remove sh4_read_long and friends |
| view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * Support module for collecting instruction stats
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #include "dream.h"
20 #include "sh4/sh4stat.h"
21 #include "sh4/sh4core.h"
22 #include "sh4/mmu.h"
24 static uint64_t sh4_stats[SH4_INSTRUCTION_COUNT+1];
25 static uint64_t sh4_stats_total;
26 static const char *sh4_stats_names[] = {
27 "???",
28 "ADD Rm, Rn",
29 "ADD #imm, Rn",
30 "ADDC Rm, Rn",
31 "ADDV Rm, Rn",
32 "AND Rm, Rn",
33 "AND #imm, R0",
34 "AND.B #imm, @(R0, GBR)",
35 "BF disp",
36 "BF/S disp",
37 "BRA disp",
38 "BRAF Rn",
39 "BSR disp",
40 "BSRF Rn",
41 "BT disp",
42 "BT/S disp",
43 "CLRMAC",
44 "CLRS",
45 "CLRT",
46 "CMP/EQ Rm, Rn",
47 "CMP/EQ #imm, R0",
48 "CMP/GE Rm, Rn",
49 "CMP/GT Rm, Rn",
50 "CMP/HI Rm, Rn",
51 "CMP/HS Rm, Rn",
52 "CMP/PL Rn",
53 "CMP/PZ Rn",
54 "CMP/STR Rm, Rn",
55 "DIV0S Rm, Rn",
56 "DIV0U",
57 "DIV1 Rm, Rn",
58 "DMULS.L Rm, Rn",
59 "DMULU.L Rm, Rn",
60 "DT Rn",
61 "EXTS.B Rm, Rn",
62 "EXTS.W Rm, Rn",
63 "EXTU.B Rm, Rn",
64 "EXTU.W Rm, Rn",
65 "FABS FRn",
66 "FADD FRm, FRn",
67 "FCMP/EQ FRm, FRn",
68 "FCMP/GT FRm, FRn",
69 "FCNVDS FRm, FPUL",
70 "FCNVSD FPUL, FRn",
71 "FDIV FRm, FRn",
72 "FIPR FVm, FVn",
73 "FLDS FRm, FPUL",
74 "FLDI0 FRn",
75 "FLDI1 FRn",
76 "FLOAT FPUL, FRn",
77 "FMAC FR0, FRm, FRn",
78 "FMOV FRm, FRn",
79 "FMOV FRm, @Rn",
80 "FMOV FRm, @-Rn",
81 "FMOV FRm, @(R0, Rn)",
82 "FMOV @Rm, FRn",
83 "FMOV @Rm+, FRn",
84 "FMOV @(R0, Rm), FRn",
85 "FMUL FRm, FRn",
86 "FNEG FRn",
87 "FRCHG",
88 "FSCA FPUL, FRn",
89 "FSCHG",
90 "FSQRT FRn",
91 "FSRRA FRn",
92 "FSTS FPUL, FRn",
93 "FSUB FRm, FRn",
94 "FTRC FRm, FPUL",
95 "FTRV XMTRX, FVn",
96 "JMP @Rn",
97 "JSR @Rn",
98 "LDC Rm, SR",
99 "LDC Rm, *",
100 "LDC.L @Rm+, SR",
101 "LDC.L @Rm+, *",
102 "LDS Rm, FPSCR",
103 "LDS Rm, *",
104 "LDS.L @Rm+, FPSCR",
105 "LDS.L @Rm+, *",
106 "LDTLB",
107 "MAC.L @Rm+, @Rn+",
108 "MAC.W @Rm+, @Rn+",
109 "MOV Rm, Rn",
110 "MOV #imm, Rn",
111 "MOV.B ...",
112 "MOV.L ...",
113 "MOV.L @(disp, PC)",
114 "MOV.W ...",
115 "MOVA @(disp, PC), R0",
116 "MOVCA.L R0, @Rn",
117 "MOVT Rn",
118 "MUL.L Rm, Rn",
119 "MULS.W Rm, Rn",
120 "MULU.W Rm, Rn",
121 "NEG Rm, Rn",
122 "NEGC Rm, Rn",
123 "NOP",
124 "NOT Rm, Rn",
125 "OCBI @Rn",
126 "OCBP @Rn",
127 "OCBWB @Rn",
128 "OR Rm, Rn",
129 "OR #imm, R0",
130 "OR.B #imm, @(R0, GBR)",
131 "PREF @Rn",
132 "ROTCL Rn",
133 "ROTCR Rn",
134 "ROTL Rn",
135 "ROTR Rn",
136 "RTE",
137 "RTS",
138 "SETS",
139 "SETT",
140 "SHAD Rm, Rn",
141 "SHAL Rn",
142 "SHAR Rn",
143 "SHLD Rm, Rn",
144 "SHLL* Rn",
145 "SHLR* Rn",
146 "SLEEP",
147 "STC SR, Rn",
148 "STC *, Rn",
149 "STC.L SR, @-Rn",
150 "STC.L *, @-Rn",
151 "STS FPSCR, Rn",
152 "STS *, Rn",
153 "STS.L FPSCR, @-Rn",
154 "STS.L *, @-Rn",
155 "SUB Rm, Rn",
156 "SUBC Rm, Rn",
157 "SUBV Rm, Rn",
158 "SWAP.B Rm, Rn",
159 "SWAP.W Rm, Rn",
160 "TAS.B @Rn",
161 "TRAPA #imm",
162 "TST Rm, Rn",
163 "TST #imm, R0",
164 "TST.B #imm, @(R0, GBR)",
165 "XOR Rm, Rn",
166 "XOR #imm, R0",
167 "XOR.B #imm, @(R0, GBR)",
168 "XTRCT Rm, Rn",
169 "UNDEF"
170 };
172 void sh4_stats_reset( void )
173 {
174 int i;
175 for( i=0; i<= I_UNDEF; i++ ) {
176 sh4_stats[i] = 0;
177 }
178 sh4_stats_total = 0;
179 }
181 void sh4_stats_print( FILE *out )
182 {
183 int i;
184 for( i=0; i<= I_UNDEF; i++ ) {
185 fprintf( out, "%-20s\t%d\t%.2f%%\n", sh4_stats_names[i], (uint32_t)sh4_stats[i], ((double)sh4_stats[i])*100.0/(double)sh4_stats_total );
186 }
187 fprintf( out, "Total: %lld\n", sh4_stats_total );
188 }
190 void FASTCALL sh4_stats_add( sh4_inst_id item )
191 {
192 sh4_stats[item]++;
193 sh4_stats_total++;
194 }
196 void sh4_stats_add_by_pc( uint32_t pc )
197 {
198 sh4addr_t addr = mmu_vma_to_phys_disasm(pc);
199 uint16_t ir = ext_address_space[addr>>12]->read_word(addr);
200 #define UNDEF(ir) sh4_stats[0]++
201 %%
202 ADD Rm, Rn {: sh4_stats[I_ADD]++; :}
203 ADD #imm, Rn {: sh4_stats[I_ADDI]++; :}
204 ADDC Rm, Rn {: sh4_stats[I_ADDC]++; :}
205 ADDV Rm, Rn {: sh4_stats[I_ADDV]++; :}
206 AND Rm, Rn {: sh4_stats[I_AND]++; :}
207 AND #imm, R0 {: sh4_stats[I_ANDI]++; :}
208 AND.B #imm, @(R0, GBR) {: sh4_stats[I_ANDB]++; :}
209 BF disp {: sh4_stats[I_BF]++; :}
210 BF/S disp {: sh4_stats[I_BFS]++; :}
211 BRA disp {: sh4_stats[I_BRA]++; :}
212 BRAF Rn {: sh4_stats[I_BRAF]++; :}
213 BSR disp {: sh4_stats[I_BSR]++; :}
214 BSRF Rn {: sh4_stats[I_BSRF]++; :}
215 BT disp {: sh4_stats[I_BT]++; :}
216 BT/S disp {: sh4_stats[I_BTS]++; :}
217 CLRMAC {: sh4_stats[I_CLRMAC]++; :}
218 CLRS {: sh4_stats[I_CLRS]++; :}
219 CLRT {: sh4_stats[I_CLRT]++; :}
220 CMP/EQ Rm, Rn {: sh4_stats[I_CMPEQ]++; :}
221 CMP/EQ #imm, R0 {: sh4_stats[I_CMPEQI]++; :}
222 CMP/GE Rm, Rn {: sh4_stats[I_CMPGE]++; :}
223 CMP/GT Rm, Rn {: sh4_stats[I_CMPGT]++; :}
224 CMP/HI Rm, Rn {: sh4_stats[I_CMPHI]++; :}
225 CMP/HS Rm, Rn {: sh4_stats[I_CMPHS]++; :}
226 CMP/PL Rn {: sh4_stats[I_CMPPL]++; :}
227 CMP/PZ Rn {: sh4_stats[I_CMPPZ]++; :}
228 CMP/STR Rm, Rn {: sh4_stats[I_CMPSTR]++; :}
229 DIV0S Rm, Rn {: sh4_stats[I_DIV0S]++; :}
230 DIV0U {: sh4_stats[I_DIV0U]++; :}
231 DIV1 Rm, Rn {: sh4_stats[I_DIV1]++; :}
232 DMULS.L Rm, Rn {: sh4_stats[I_DMULS]++; :}
233 DMULU.L Rm, Rn {: sh4_stats[I_DMULU]++; :}
234 DT Rn {: sh4_stats[I_DT]++; :}
235 EXTS.B Rm, Rn {: sh4_stats[I_EXTSB]++; :}
236 EXTS.W Rm, Rn {: sh4_stats[I_EXTSW]++; :}
237 EXTU.B Rm, Rn {: sh4_stats[I_EXTUB]++; :}
238 EXTU.W Rm, Rn {: sh4_stats[I_EXTUW]++; :}
239 FABS FRn {: sh4_stats[I_FABS]++; :}
240 FADD FRm, FRn {: sh4_stats[I_FADD]++; :}
241 FCMP/EQ FRm, FRn {: sh4_stats[I_FCMPEQ]++; :}
242 FCMP/GT FRm, FRn {: sh4_stats[I_FCMPGT]++; :}
243 FCNVDS FRm, FPUL {: sh4_stats[I_FCNVDS]++; :}
244 FCNVSD FPUL, FRn {: sh4_stats[I_FCNVSD]++; :}
245 FDIV FRm, FRn {: sh4_stats[I_FDIV]++; :}
246 FIPR FVm, FVn {: sh4_stats[I_FIPR]++; :}
247 FLDS FRm, FPUL {: sh4_stats[I_FLDS]++; :}
248 FLDI0 FRn {: sh4_stats[I_FLDI0]++; :}
249 FLDI1 FRn {: sh4_stats[I_FLDI1]++; :}
250 FLOAT FPUL, FRn {: sh4_stats[I_FLOAT]++; :}
251 FMAC FR0, FRm, FRn {: sh4_stats[I_FMAC]++; :}
252 FMOV FRm, FRn {: sh4_stats[I_FMOV1]++; :}
253 FMOV FRm, @Rn {: sh4_stats[I_FMOV2]++; :}
254 FMOV FRm, @-Rn {: sh4_stats[I_FMOV3]++; :}
255 FMOV FRm, @(R0, Rn) {: sh4_stats[I_FMOV4]++; :}
256 FMOV @Rm, FRn {: sh4_stats[I_FMOV5]++; :}
257 FMOV @Rm+, FRn {: sh4_stats[I_FMOV6]++; :}
258 FMOV @(R0, Rm), FRn {: sh4_stats[I_FMOV7]++; :}
259 FMUL FRm, FRn {: sh4_stats[I_FMUL]++; :}
260 FNEG FRn {: sh4_stats[I_FNEG]++; :}
261 FRCHG {: sh4_stats[I_FRCHG]++; :}
262 FSCA FPUL, FRn {: sh4_stats[I_FSCA]++; :}
263 FSCHG {: sh4_stats[I_FSCHG]++; :}
264 FSQRT FRn {: sh4_stats[I_FSQRT]++; :}
265 FSRRA FRn {: sh4_stats[I_FSRRA]++; :}
266 FSTS FPUL, FRn {: sh4_stats[I_FSTS]++; :}
267 FSUB FRm, FRn {: sh4_stats[I_FSUB]++; :}
268 FTRC FRm, FPUL {: sh4_stats[I_FTRC]++; :}
269 FTRV XMTRX, FVn {: sh4_stats[I_FTRV]++; :}
270 JMP @Rn {: sh4_stats[I_JMP]++; :}
271 JSR @Rn {: sh4_stats[I_JSR]++; :}
272 LDC Rm, GBR {: sh4_stats[I_LDC]++; :}
273 LDC Rm, SR {: sh4_stats[I_LDCSR]++; :}
274 LDC Rm, VBR {: sh4_stats[I_LDC]++; :}
275 LDC Rm, SSR {: sh4_stats[I_LDC]++; :}
276 LDC Rm, SGR {: sh4_stats[I_LDC]++; :}
277 LDC Rm, SPC {: sh4_stats[I_LDC]++; :}
278 LDC Rm, DBR {: sh4_stats[I_LDC]++; :}
279 LDC Rm, Rn_BANK {: sh4_stats[I_LDC]++; :}
280 LDC.L @Rm+, GBR {: sh4_stats[I_LDCM]++; :}
281 LDC.L @Rm+, SR {: sh4_stats[I_LDCSRM]++; :}
282 LDC.L @Rm+, VBR {: sh4_stats[I_LDCM]++; :}
283 LDC.L @Rm+, SSR {: sh4_stats[I_LDCM]++; :}
284 LDC.L @Rm+, SGR {: sh4_stats[I_LDCM]++; :}
285 LDC.L @Rm+, SPC {: sh4_stats[I_LDCM]++; :}
286 LDC.L @Rm+, DBR {: sh4_stats[I_LDCM]++; :}
287 LDC.L @Rm+, Rn_BANK {: sh4_stats[I_LDCM]++; :}
288 LDS Rm, FPSCR {: sh4_stats[I_LDSFPSCR]++; :}
289 LDS.L @Rm+, FPSCR {: sh4_stats[I_LDSFPSCRM]++; :}
290 LDS Rm, FPUL {: sh4_stats[I_LDS]++; :}
291 LDS.L @Rm+, FPUL {: sh4_stats[I_LDSM]++; :}
292 LDS Rm, MACH {: sh4_stats[I_LDS]++; :}
293 LDS.L @Rm+, MACH {: sh4_stats[I_LDSM]++; :}
294 LDS Rm, MACL {: sh4_stats[I_LDS]++; :}
295 LDS.L @Rm+, MACL {: sh4_stats[I_LDSM]++; :}
296 LDS Rm, PR {: sh4_stats[I_LDS]++; :}
297 LDS.L @Rm+, PR {: sh4_stats[I_LDSM]++; :}
298 LDTLB {: sh4_stats[I_LDTLB]++; :}
299 MAC.L @Rm+, @Rn+ {: sh4_stats[I_MACL]++; :}
300 MAC.W @Rm+, @Rn+ {: sh4_stats[I_MACW]++; :}
301 MOV Rm, Rn {: sh4_stats[I_MOV]++; :}
302 MOV #imm, Rn {: sh4_stats[I_MOVI]++; :}
303 MOV.B Rm, @Rn {: sh4_stats[I_MOVB]++; :}
304 MOV.B Rm, @-Rn {: sh4_stats[I_MOVB]++; :}
305 MOV.B Rm, @(R0, Rn) {: sh4_stats[I_MOVB]++; :}
306 MOV.B R0, @(disp, GBR) {: sh4_stats[I_MOVB]++; :}
307 MOV.B R0, @(disp, Rn) {: sh4_stats[I_MOVB]++; :}
308 MOV.B @Rm, Rn {: sh4_stats[I_MOVB]++; :}
309 MOV.B @Rm+, Rn {: sh4_stats[I_MOVB]++; :}
310 MOV.B @(R0, Rm), Rn {: sh4_stats[I_MOVB]++; :}
311 MOV.B @(disp, GBR), R0 {: sh4_stats[I_MOVB]++; :}
312 MOV.B @(disp, Rm), R0 {: sh4_stats[I_MOVB]++; :}
313 MOV.L Rm, @Rn {: sh4_stats[I_MOVL]++; :}
314 MOV.L Rm, @-Rn {: sh4_stats[I_MOVL]++; :}
315 MOV.L Rm, @(R0, Rn) {: sh4_stats[I_MOVL]++; :}
316 MOV.L R0, @(disp, GBR) {: sh4_stats[I_MOVL]++; :}
317 MOV.L Rm, @(disp, Rn) {: sh4_stats[I_MOVL]++; :}
318 MOV.L @Rm, Rn {: sh4_stats[I_MOVL]++; :}
319 MOV.L @Rm+, Rn {: sh4_stats[I_MOVL]++; :}
320 MOV.L @(R0, Rm), Rn {: sh4_stats[I_MOVL]++; :}
321 MOV.L @(disp, GBR), R0 {: sh4_stats[I_MOVL]++; :}
322 MOV.L @(disp, PC), Rn {: sh4_stats[I_MOVLPC]++; :}
323 MOV.L @(disp, Rm), Rn {: sh4_stats[I_MOVL]++; :}
324 MOV.W Rm, @Rn {: sh4_stats[I_MOVW]++; :}
325 MOV.W Rm, @-Rn {: sh4_stats[I_MOVW]++; :}
326 MOV.W Rm, @(R0, Rn) {: sh4_stats[I_MOVW]++; :}
327 MOV.W R0, @(disp, GBR) {: sh4_stats[I_MOVW]++; :}
328 MOV.W R0, @(disp, Rn) {: sh4_stats[I_MOVW]++; :}
329 MOV.W @Rm, Rn {: sh4_stats[I_MOVW]++; :}
330 MOV.W @Rm+, Rn {: sh4_stats[I_MOVW]++; :}
331 MOV.W @(R0, Rm), Rn {: sh4_stats[I_MOVW]++; :}
332 MOV.W @(disp, GBR), R0 {: sh4_stats[I_MOVW]++; :}
333 MOV.W @(disp, PC), Rn {: sh4_stats[I_MOVW]++; :}
334 MOV.W @(disp, Rm), R0 {: sh4_stats[I_MOVW]++; :}
335 MOVA @(disp, PC), R0 {: sh4_stats[I_MOVA]++; :}
336 MOVCA.L R0, @Rn {: sh4_stats[I_MOVCA]++; :}
337 MOVT Rn {: sh4_stats[I_MOVT]++; :}
338 MUL.L Rm, Rn {: sh4_stats[I_MULL]++; :}
339 MULS.W Rm, Rn {: sh4_stats[I_MULSW]++; :}
340 MULU.W Rm, Rn {: sh4_stats[I_MULUW]++; :}
341 NEG Rm, Rn {: sh4_stats[I_NEG]++; :}
342 NEGC Rm, Rn {: sh4_stats[I_NEGC]++; :}
343 NOP {: sh4_stats[I_NOP]++; :}
344 NOT Rm, Rn {: sh4_stats[I_NOT]++; :}
345 OCBI @Rn {: sh4_stats[I_OCBI]++; :}
346 OCBP @Rn {: sh4_stats[I_OCBP]++; :}
347 OCBWB @Rn {: sh4_stats[I_OCBWB]++; :}
348 OR Rm, Rn {: sh4_stats[I_OR]++; :}
349 OR #imm, R0 {: sh4_stats[I_ORI]++; :}
350 OR.B #imm, @(R0, GBR) {: sh4_stats[I_ORB]++; :}
351 PREF @Rn {: sh4_stats[I_PREF]++; :}
352 ROTCL Rn {: sh4_stats[I_ROTCL]++; :}
353 ROTCR Rn {: sh4_stats[I_ROTCR]++; :}
354 ROTL Rn {: sh4_stats[I_ROTL]++; :}
355 ROTR Rn {: sh4_stats[I_ROTR]++; :}
356 RTE {: sh4_stats[I_RTE]++; :}
357 RTS {: sh4_stats[I_RTS]++; :}
358 SETS {: sh4_stats[I_SETS]++; :}
359 SETT {: sh4_stats[I_SETT]++; :}
360 SHAD Rm, Rn {: sh4_stats[I_SHAD]++; :}
361 SHAL Rn {: sh4_stats[I_SHAL]++; :}
362 SHAR Rn {: sh4_stats[I_SHAR]++; :}
363 SHLD Rm, Rn {: sh4_stats[I_SHLD]++; :}
364 SHLL Rn {: sh4_stats[I_SHLL]++; :}
365 SHLL2 Rn {: sh4_stats[I_SHLL]++; :}
366 SHLL8 Rn {: sh4_stats[I_SHLL]++; :}
367 SHLL16 Rn {: sh4_stats[I_SHLL]++; :}
368 SHLR Rn {: sh4_stats[I_SHLR]++; :}
369 SHLR2 Rn {: sh4_stats[I_SHLR]++; :}
370 SHLR8 Rn {: sh4_stats[I_SHLR]++; :}
371 SHLR16 Rn {: sh4_stats[I_SHLR]++; :}
372 SLEEP {: sh4_stats[I_SLEEP]++; :}
373 STC SR, Rn {: sh4_stats[I_STCSR]++; :}
374 STC GBR, Rn {: sh4_stats[I_STC]++; :}
375 STC VBR, Rn {: sh4_stats[I_STC]++; :}
376 STC SSR, Rn {: sh4_stats[I_STC]++; :}
377 STC SPC, Rn {: sh4_stats[I_STC]++; :}
378 STC SGR, Rn {: sh4_stats[I_STC]++; :}
379 STC DBR, Rn {: sh4_stats[I_STC]++; :}
380 STC Rm_BANK, Rn {: sh4_stats[I_STC]++; :}
381 STC.L SR, @-Rn {: sh4_stats[I_STCSRM]++; :}
382 STC.L VBR, @-Rn {: sh4_stats[I_STCM]++; :}
383 STC.L SSR, @-Rn {: sh4_stats[I_STCM]++; :}
384 STC.L SPC, @-Rn {: sh4_stats[I_STCM]++; :}
385 STC.L SGR, @-Rn {: sh4_stats[I_STCM]++; :}
386 STC.L DBR, @-Rn {: sh4_stats[I_STCM]++; :}
387 STC.L Rm_BANK, @-Rn {: sh4_stats[I_STCM]++; :}
388 STC.L GBR, @-Rn {: sh4_stats[I_STCM]++; :}
389 STS FPSCR, Rn {: sh4_stats[I_STSFPSCR]++; :}
390 STS.L FPSCR, @-Rn {: sh4_stats[I_STSFPSCRM]++; :}
391 STS FPUL, Rn {: sh4_stats[I_STS]++; :}
392 STS.L FPUL, @-Rn {: sh4_stats[I_STSM]++; :}
393 STS MACH, Rn {: sh4_stats[I_STS]++; :}
394 STS.L MACH, @-Rn {: sh4_stats[I_STSM]++; :}
395 STS MACL, Rn {: sh4_stats[I_STS]++; :}
396 STS.L MACL, @-Rn {: sh4_stats[I_STSM]++; :}
397 STS PR, Rn {: sh4_stats[I_STS]++; :}
398 STS.L PR, @-Rn {: sh4_stats[I_STSM]++; :}
399 SUB Rm, Rn {: sh4_stats[I_SUB]++; :}
400 SUBC Rm, Rn {: sh4_stats[I_SUBC]++; :}
401 SUBV Rm, Rn {: sh4_stats[I_SUBV]++; :}
402 SWAP.B Rm, Rn {: sh4_stats[I_SWAPB]++; :}
403 SWAP.W Rm, Rn {: sh4_stats[I_SWAPW]++; :}
404 TAS.B @Rn {: sh4_stats[I_TASB]++; :}
405 TRAPA #imm {: sh4_stats[I_TRAPA]++; :}
406 TST Rm, Rn {: sh4_stats[I_TST]++; :}
407 TST #imm, R0 {: sh4_stats[I_TSTI]++; :}
408 TST.B #imm, @(R0, GBR) {: sh4_stats[I_TSTB]++; :}
409 XOR Rm, Rn {: sh4_stats[I_XOR]++; :}
410 XOR #imm, R0 {: sh4_stats[I_XORI]++; :}
411 XOR.B #imm, @(R0, GBR) {: sh4_stats[I_XORB]++; :}
412 XTRCT Rm, Rn {: sh4_stats[I_XTRCT]++; :}
413 UNDEF {: sh4_stats[I_UNDEF]++; :}
414 %%
416 sh4_stats_total++;
417 }
.