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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 214:7a6501b74fbc
prev197:f65ff8c8320d
next218:cbad5a3f8387
author nkeynes
date Fri Aug 18 12:43:04 2006 +0000 (13 years ago)
permissions -rw-r--r--
last change Ensure pvr2_ta_reset() is called on system reset
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     1 /**
     2  * $Id: pvr2.c,v 1.32 2006-08-18 12:43:04 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "display.h"
    22 #include "mem.h"
    23 #include "asic.h"
    24 #include "pvr2/pvr2.h"
    25 #include "sh4/sh4core.h"
    26 #define MMIO_IMPL
    27 #include "pvr2/pvr2mmio.h"
    29 char *video_base;
    31 static void pvr2_init( void );
    32 static void pvr2_reset( void );
    33 static uint32_t pvr2_run_slice( uint32_t );
    34 static void pvr2_save_state( FILE *f );
    35 static int pvr2_load_state( FILE *f );
    37 void pvr2_display_frame( void );
    39 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
    41 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    42 					pvr2_run_slice, NULL,
    43 					pvr2_save_state, pvr2_load_state };
    46 display_driver_t display_driver = NULL;
    48 struct video_timing {
    49     int fields_per_second;
    50     int total_lines;
    51     int retrace_lines;
    52     int line_time_ns;
    53 };
    55 struct video_timing pal_timing = { 50, 625, 65, 32000 };
    56 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    58 struct pvr2_state {
    59     uint32_t frame_count;
    60     uint32_t line_count;
    61     uint32_t line_remainder;
    62     uint32_t irq_vpos1;
    63     uint32_t irq_vpos2;
    64     gboolean retrace;
    65     struct video_timing timing;
    66 } pvr2_state;
    68 struct video_buffer video_buffer[2];
    69 int video_buffer_idx = 0;
    71 static void pvr2_init( void )
    72 {
    73     register_io_region( &mmio_region_PVR2 );
    74     register_io_region( &mmio_region_PVR2PAL );
    75     register_io_region( &mmio_region_PVR2TA );
    76     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    77     texcache_init();
    78     pvr2_reset();
    79     pvr2_ta_reset();
    80 }
    82 static void pvr2_reset( void )
    83 {
    84     pvr2_state.line_count = 0;
    85     pvr2_state.line_remainder = 0;
    86     pvr2_state.irq_vpos1 = 0;
    87     pvr2_state.irq_vpos2 = 0;
    88     pvr2_state.retrace = FALSE;
    89     pvr2_state.timing = ntsc_timing;
    90     video_buffer_idx = 0;
    92     pvr2_ta_init();
    93     pvr2_render_init();
    94     texcache_flush();
    95 }
    97 static void pvr2_save_state( FILE *f )
    98 {
    99     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   100     pvr2_ta_save_state( f );
   101 }
   103 static int pvr2_load_state( FILE *f )
   104 {
   105     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   106 	return 1;
   107     return pvr2_ta_load_state(f);
   108 }
   110 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   111 {
   112     pvr2_state.line_remainder += nanosecs;
   113     while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
   114 	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
   116 	pvr2_state.line_count++;
   117 	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
   118 	    asic_event( EVENT_RETRACE );
   119 	    pvr2_state.line_count = 0;
   120 	    pvr2_state.retrace = TRUE;
   121 	}
   123 	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
   124 	    asic_event( EVENT_SCANLINE1 );
   125 	} 
   126 	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
   127 	    asic_event( EVENT_SCANLINE2 );
   128 	}
   130 	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
   131 	    if( pvr2_state.retrace ) {
   132 		pvr2_display_frame();
   133 		pvr2_state.retrace = FALSE;
   134 	    }
   135 	}
   136     }
   137     return nanosecs;
   138 }
   140 int pvr2_get_frame_count() 
   141 {
   142     return pvr2_state.frame_count;
   143 }
   145 /**
   146  * Display the next frame, copying the current contents of video ram to
   147  * the window. If the video configuration has changed, first recompute the
   148  * new frame size/depth.
   149  */
   150 void pvr2_display_frame( void )
   151 {
   152     uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   154     int dispsize = MMIO_READ( PVR2, DISP_SIZE );
   155     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   156     int vidcfg = MMIO_READ( PVR2, DISP_CFG );
   157     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
   158     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   159     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   160     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   161     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
   162     video_buffer_t buffer = &video_buffer[video_buffer_idx];
   163     video_buffer_idx = !video_buffer_idx;
   164     video_buffer_t last = &video_buffer[video_buffer_idx];
   165     buffer->rowstride = (vid_ppl + vid_stride) << 2;
   166     buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
   167     buffer->vres = vid_lpf;
   168     if( interlaced ) buffer->vres <<= 1;
   169     switch( (dispmode & DISPMODE_COL) >> 2 ) {
   170     case 0: 
   171 	buffer->colour_format = COLFMT_ARGB1555;
   172 	buffer->hres = vid_ppl << 1; 
   173 	break;
   174     case 1: 
   175 	buffer->colour_format = COLFMT_RGB565;
   176 	buffer->hres = vid_ppl << 1; 
   177 	break;
   178     case 2:
   179 	buffer->colour_format = COLFMT_RGB888;
   180 	buffer->hres = (vid_ppl << 2) / 3; 
   181 	break;
   182     case 3: 
   183 	buffer->colour_format = COLFMT_ARGB8888;
   184 	buffer->hres = vid_ppl; 
   185 	break;
   186     }
   188     if( buffer->hres <=8 )
   189 	buffer->hres = 640;
   190     if( buffer->vres <=8 )
   191 	buffer->vres = 480;
   192     if( display_driver != NULL ) {
   193 	if( buffer->hres != last->hres ||
   194 	    buffer->vres != last->vres ||
   195 	    buffer->colour_format != last->colour_format) {
   196 	    display_driver->set_display_format( buffer->hres, buffer->vres,
   197 						buffer->colour_format );
   198 	}
   199 	if( !bEnabled ) {
   200 	    display_driver->display_blank_frame( 0 );
   201 	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
   202 	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
   203 	    display_driver->display_blank_frame( colour );
   204 	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
   205 	    display_driver->display_frame( buffer );
   206 	}
   207     }
   208     pvr2_state.frame_count++;
   209 }
   211 /**
   212  * This has to handle every single register individually as they all get masked 
   213  * off differently (and its easier to do it at write time)
   214  */
   215 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   216 {
   217     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   218         MMIO_WRITE( PVR2, reg, val );
   219         return;
   220     }
   222     switch(reg) {
   223     case PVRID:
   224     case PVRVER:
   225     case GUNPOS:
   226     case TA_POLYPOS:
   227     case TA_LISTPOS:
   228 	/* Readonly registers */
   229 	break;
   230     case PVRRESET:
   231 	val &= 0x00000007; /* Do stuff? */
   232 	MMIO_WRITE( PVR2, reg, val );
   233 	break;
   234     case RENDER_START:
   235 	if( val == 0xFFFFFFFF )
   236 	    pvr2_render_scene();
   237 	break;
   238     case PVRUNK1:
   239     	MMIO_WRITE( PVR2, reg, val&0x000007FF );
   240     	break;
   241     case RENDER_POLYBASE:
   242     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   243     	break;
   244     case RENDER_TSPCFG:
   245     	MMIO_WRITE( PVR2, reg, val&0x00010101 );
   246     	break;
   247     case DISP_BORDER:
   248     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   249     	break;
   250     case DISP_MODE:
   251     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   252     	break;
   253     case RENDER_MODE:
   254     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   255     	break;
   256     case RENDER_SIZE:
   257     	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   258     	break;
   259     case DISP_ADDR1:
   260 	val &= 0x00FFFFFC;
   261 	MMIO_WRITE( PVR2, reg, val );
   262 	if( pvr2_state.retrace ) {
   263 	    pvr2_display_frame();
   264 	    pvr2_state.retrace = FALSE;
   265 	}
   266 	break;
   267     case DISP_ADDR2:
   268     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   269     	break;
   270     case DISP_SIZE:
   271     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   272     	break;
   273     case RENDER_ADDR1:
   274     case RENDER_ADDR2:
   275     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   276     	break;
   277     case RENDER_HCLIP:
   278 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   279 	break;
   280     case RENDER_VCLIP:
   281 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   282 	break;
   283     case DISP_HPOSIRQ:
   284 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   285 	break;
   286     case DISP_VPOSIRQ:
   287 	val = val & 0x03FF03FF;
   288 	pvr2_state.irq_vpos1 = (val >> 16);
   289 	pvr2_state.irq_vpos2 = val & 0x03FF;
   290 	MMIO_WRITE( PVR2, reg, val );
   291 	break;
   292     case RENDER_NEARCLIP:
   293 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   294 	break;
   295     case RENDER_SHADOW:
   296 	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   297 	break;
   298     case RENDER_OBJCFG:
   299     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   300     	break;
   301     case PVRUNK2:
   302 	MMIO_WRITE( PVR2, reg, val&0x00000007 );
   303 	break;
   304     case RENDER_TSPCLIP:
   305     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   306     	break;
   307     case RENDER_FARCLIP:
   308 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   309 	break;
   310     case RENDER_BGPLANE:
   311     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   312     	break;
   313     case RENDER_ISPCFG:
   314     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   315     	break;
   316     case VRAM_CFG1:
   317 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   318 	break;
   319     case VRAM_CFG2:
   320 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   321 	break;
   322     case VRAM_CFG3:
   323 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   324 	break;
   325     case RENDER_FOGTBLCOL:
   326     case RENDER_FOGVRTCOL:
   327 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   328 	break;
   329     case RENDER_FOGCOEFF:
   330 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   331 	break;
   332     case RENDER_CLAMPHI:
   333     case RENDER_CLAMPLO:
   334 	MMIO_WRITE( PVR2, reg, val );
   335 	break;
   336     case DISP_CFG:
   337 	MMIO_WRITE( PVR2, reg, val&0x000003FF );
   338 	break;
   339     case DISP_HBORDER:
   340     case DISP_SYNC:
   341     case DISP_VBORDER:
   342 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   343 	break;
   344     case DISP_SYNC2:
   345 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   346 	break;
   347     case RENDER_TEXSIZE:
   348 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   349 	break;
   350     case DISP_CFG2:
   351 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   352 	break;
   353     case DISP_HPOS:
   354 	MMIO_WRITE( PVR2, reg, val&0x000003FF );
   355 	break;
   356     case DISP_VPOS:
   357 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   358 	break;
   359     case SCALERCFG:
   360 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   361 	break;
   362     case RENDER_PALETTE:
   363 	MMIO_WRITE( PVR2, reg, val&0x00000003 );
   364 	break;
   365     case PVRUNK3:
   366 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   367 	break;
   368     case PVRUNK5:
   369 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   370 	break;
   371     case PVRUNK6:
   372 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   373 	break;
   374     case TA_TILEBASE:
   375     case TA_LISTEND:
   376     case TA_LISTBASE:
   377 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   378 	break;
   379     case RENDER_TILEBASE:
   380     case TA_POLYBASE:
   381     case TA_POLYEND:
   382 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   383 	break;
   384     case TA_TILESIZE:
   385 	MMIO_WRITE( PVR2, reg, val&0x000F003F );
   386 	break;
   387     case TA_TILECFG:
   388 	MMIO_WRITE( PVR2, reg, val&0x00133333 );
   389 	break;
   390     case YUV_ADDR:
   391 	MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
   392 	break;
   393     case YUV_CFG:
   394 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   395 	break;
   396     case TA_INIT:
   397 	if( val & 0x80000000 )
   398 	    pvr2_ta_init();
   399 	break;
   400     case TA_REINIT:
   401 	break;
   402     case PVRUNK7:
   403 	MMIO_WRITE( PVR2, reg, val&0x00000001 );
   404 	break;
   405     }
   406 }
   408 MMIO_REGION_READ_FN( PVR2, reg )
   409 {
   410     switch( reg ) {
   411         case DISP_BEAMPOS:
   412             return sh4r.icount&0x20 ? 0x2000 : 1;
   413         default:
   414             return MMIO_READ( PVR2, reg );
   415     }
   416 }
   418 MMIO_REGION_DEFFNS( PVR2PAL )
   420 void pvr2_set_base_address( uint32_t base ) 
   421 {
   422     mmio_region_PVR2_write( DISP_ADDR1, base );
   423 }
   428 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   429 {
   430     return 0xFFFFFFFF;
   431 }
   433 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   434 {
   435     pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
   436 }
   439 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
   440 {
   441     int bank_flag = (destaddr & 0x04) >> 2;
   442     uint32_t *banks[2];
   443     uint32_t *dwsrc;
   444     int i;
   446     destaddr = destaddr & 0x7FFFFF;
   447     if( destaddr + length > 0x800000 ) {
   448 	length = 0x800000 - destaddr;
   449     }
   451     for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
   452 	texcache_invalidate_page( i );
   453     }
   455     banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
   456     banks[1] = banks[0] + 0x100000;
   457     if( bank_flag ) 
   458 	banks[0]++;
   460     /* Handle non-aligned start of source */
   461     if( destaddr & 0x03 ) {
   462 	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
   463 	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   464 	    *dest++ = *src++;
   465 	}
   466 	bank_flag = !bank_flag;
   467     }
   469     dwsrc = (uint32_t *)src;
   470     while( length >= 4 ) {
   471 	*banks[bank_flag]++ = *dwsrc++;
   472 	bank_flag = !bank_flag;
   473 	length -= 4;
   474     }
   476     /* Handle non-aligned end of source */
   477     if( length ) {
   478 	src = (char *)dwsrc;
   479 	char *dest = (char *)banks[bank_flag];
   480 	while( length-- > 0 ) {
   481 	    *dest++ = *src++;
   482 	}
   483     }  
   485 }
   487 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
   488 {
   489     int bank_flag = (srcaddr & 0x04) >> 2;
   490     uint32_t *banks[2];
   491     uint32_t *dwdest;
   492     int i;
   494     srcaddr = srcaddr & 0x7FFFFF;
   495     if( srcaddr + length > 0x800000 )
   496 	length = 0x800000 - srcaddr;
   498     banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
   499     banks[1] = banks[0] + 0x100000;
   500     if( bank_flag )
   501 	banks[0]++;
   503     /* Handle non-aligned start of source */
   504     if( srcaddr & 0x03 ) {
   505 	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
   506 	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   507 	    *dest++ = *src++;
   508 	}
   509 	bank_flag = !bank_flag;
   510     }
   512     dwdest = (uint32_t *)dest;
   513     while( length >= 4 ) {
   514 	*dwdest++ = *banks[bank_flag]++;
   515 	bank_flag = !bank_flag;
   516 	length -= 4;
   517     }
   519     /* Handle non-aligned end of source */
   520     if( length ) {
   521 	dest = (char *)dwdest;
   522 	char *src = (char *)banks[bank_flag];
   523 	while( length-- > 0 ) {
   524 	    *dest++ = *src++;
   525 	}
   526     }
   527 }
   529 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
   530 {
   531     char tmp[length];
   532     pvr2_vram64_read( tmp, addr, length );
   533     fwrite_dump( tmp, length, f );
   534 }
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