Search
lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4x86.in
changeset 1003:7b2688cbbca3
prev996:2e8cf0a87243
next1004:eae001858134
author nkeynes
date Fri Mar 27 06:13:34 2009 +0000 (11 years ago)
permissions -rw-r--r--
last change Revert change to xltcache and fix breakpoint precision correctly
view annotate diff log raw
     1 /**
     2  * $Id$
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    22 #include <math.h>
    24 #ifndef NDEBUG
    25 #define DEBUG_JUMPS 1
    26 #endif
    28 #include "lxdream.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4trans.h"
    31 #include "sh4/sh4stat.h"
    32 #include "sh4/sh4mmio.h"
    33 #include "sh4/mmu.h"
    34 #include "xlat/xltcache.h"
    35 #include "xlat/x86/x86op.h"
    36 #include "clock.h"
    38 #define DEFAULT_BACKPATCH_SIZE 4096
    40 /* Offset of a reg relative to the sh4r structure */
    41 #define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
    43 #define R_T      REG_OFFSET(t)
    44 #define R_Q      REG_OFFSET(q)
    45 #define R_S      REG_OFFSET(s)
    46 #define R_M      REG_OFFSET(m)
    47 #define R_SR     REG_OFFSET(sr)
    48 #define R_GBR    REG_OFFSET(gbr)
    49 #define R_SSR    REG_OFFSET(ssr)
    50 #define R_SPC    REG_OFFSET(spc)
    51 #define R_VBR    REG_OFFSET(vbr)
    52 #define R_MACH   REG_OFFSET(mac)+4
    53 #define R_MACL   REG_OFFSET(mac)
    54 #define R_PC     REG_OFFSET(pc)
    55 #define R_NEW_PC REG_OFFSET(new_pc)
    56 #define R_PR     REG_OFFSET(pr)
    57 #define R_SGR    REG_OFFSET(sgr)
    58 #define R_FPUL   REG_OFFSET(fpul)
    59 #define R_FPSCR  REG_OFFSET(fpscr)
    60 #define R_DBR    REG_OFFSET(dbr)
    61 #define R_R(rn)  REG_OFFSET(r[rn])
    62 #define R_FR(f)  REG_OFFSET(fr[0][(f)^1])
    63 #define R_XF(f)  REG_OFFSET(fr[1][(f)^1])
    64 #define R_DR(f)  REG_OFFSET(fr[(f)&1][(f)&0x0E])
    65 #define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
    66 #define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
    68 #define DELAY_NONE 0
    69 #define DELAY_PC 1
    70 #define DELAY_PC_PR 2
    72 struct backpatch_record {
    73     uint32_t fixup_offset;
    74     uint32_t fixup_icount;
    75     int32_t exc_code;
    76 };
    78 /** 
    79  * Struct to manage internal translation state. This state is not saved -
    80  * it is only valid between calls to sh4_translate_begin_block() and
    81  * sh4_translate_end_block()
    82  */
    83 struct sh4_x86_state {
    84     int in_delay_slot;
    85     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    86     gboolean branch_taken; /* true if we branched unconditionally */
    87     gboolean double_prec; /* true if FPU is in double-precision mode */
    88     gboolean double_size; /* true if FPU is in double-size mode */
    89     gboolean sse3_enabled; /* true if host supports SSE3 instructions */
    90     uint32_t block_start_pc;
    91     uint32_t stack_posn;   /* Trace stack height for alignment purposes */
    92     int tstate;
    94     /* mode flags */
    95     gboolean tlb_on; /* True if tlb translation is active */
    97     /* Allocated memory for the (block-wide) back-patch list */
    98     struct backpatch_record *backpatch_list;
    99     uint32_t backpatch_posn;
   100     uint32_t backpatch_size;
   101 };
   103 static struct sh4_x86_state sh4_x86;
   105 static uint32_t max_int = 0x7FFFFFFF;
   106 static uint32_t min_int = 0x80000000;
   107 static uint32_t save_fcw; /* save value for fpu control word */
   108 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
   110 gboolean is_sse3_supported()
   111 {
   112     uint32_t features;
   114     __asm__ __volatile__(
   115         "mov $0x01, %%eax\n\t"
   116         "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
   117     return (features & 1) ? TRUE : FALSE;
   118 }
   120 void sh4_translate_init(void)
   121 {
   122     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
   123     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
   124     sh4_x86.sse3_enabled = is_sse3_supported();
   125 }
   128 static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
   129 {
   130     int reloc_size = 4;
   132     if( exc_code == -2 ) {
   133         reloc_size = sizeof(void *);
   134     }
   136     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
   137 	sh4_x86.backpatch_size <<= 1;
   138 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
   139 					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
   140 	assert( sh4_x86.backpatch_list != NULL );
   141     }
   142     if( sh4_x86.in_delay_slot ) {
   143 	fixup_pc -= 2;
   144     }
   146     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
   147 	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
   148     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
   149     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
   150     sh4_x86.backpatch_posn++;
   151 }
   153 #define TSTATE_NONE -1
   154 #define TSTATE_O    X86_COND_O
   155 #define TSTATE_C    X86_COND_C
   156 #define TSTATE_E    X86_COND_E
   157 #define TSTATE_NE   X86_COND_NE
   158 #define TSTATE_G    X86_COND_G
   159 #define TSTATE_GE   X86_COND_GE
   160 #define TSTATE_A    X86_COND_A
   161 #define TSTATE_AE   X86_COND_AE
   163 #define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
   164 #define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
   166 /* Convenience instructions */
   167 #define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
   168 #define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
   169 #define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
   170 #define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
   171 #define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
   172 #define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
   173 #define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
   174 #define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
   175 #define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
   176 #define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
   177 #define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
   178 #define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
   179 #define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
   180 #define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
   181 #define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
   182 #define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
   183 #define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
   184 #define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
   185 #define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
   187 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
   188 #define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
   189 	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
   190     JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
   192 /** Branch if T is clear (either in the current cflags or in sh4r.t) */
   193 #define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
   194 	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
   195     JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
   198 #define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
   199 #define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
   201 /**
   202  * Load an FR register (single-precision floating point) into an integer x86
   203  * register (eg for register-to-register moves)
   204  */
   205 #define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
   206 #define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
   208 /**
   209  * Load the low half of a DR register (DR or XD) into an integer x86 register 
   210  */
   211 #define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
   212 #define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
   214 /**
   215  * Store an FR register (single-precision floating point) from an integer x86+
   216  * register (eg for register-to-register moves)
   217  */
   218 #define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
   219 #define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
   221 #define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
   222 #define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
   225 #define push_fpul()  FLDF_rbpdisp(R_FPUL)
   226 #define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
   227 #define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
   228 #define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
   229 #define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
   230 #define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
   231 #define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
   232 #define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
   233 #define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
   234 #define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
   236 #ifdef ENABLE_SH4STATS
   237 #define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
   238 #else
   239 #define COUNT_INST(id)
   240 #endif
   243 /* Exception checks - Note that all exception checks will clobber EAX */
   245 #define check_priv( ) \
   246     if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
   247         if( sh4_x86.in_delay_slot ) { \
   248             exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \
   249         } else { \
   250             exit_block_exc(EXC_ILLEGAL, pc); \
   251         } \
   252         sh4_x86.branch_taken = TRUE; \
   253         sh4_x86.in_delay_slot = DELAY_NONE; \
   254         return 2; \
   255     }
   257 #define check_fpuen( ) \
   258     if( !sh4_x86.fpuen_checked ) {\
   259 	sh4_x86.fpuen_checked = TRUE;\
   260 	MOVL_rbpdisp_r32( R_SR, REG_EAX );\
   261 	ANDL_imms_r32( SR_FD, REG_EAX );\
   262 	if( sh4_x86.in_delay_slot ) {\
   263 	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
   264 	} else {\
   265 	    JNE_exc(EXC_FPU_DISABLED);\
   266 	}\
   267 	sh4_x86.tstate = TSTATE_NONE; \
   268     }
   270 #define check_ralign16( x86reg ) \
   271     TESTL_imms_r32( 0x00000001, x86reg ); \
   272     JNE_exc(EXC_DATA_ADDR_READ)
   274 #define check_walign16( x86reg ) \
   275     TESTL_imms_r32( 0x00000001, x86reg ); \
   276     JNE_exc(EXC_DATA_ADDR_WRITE);
   278 #define check_ralign32( x86reg ) \
   279     TESTL_imms_r32( 0x00000003, x86reg ); \
   280     JNE_exc(EXC_DATA_ADDR_READ)
   282 #define check_walign32( x86reg ) \
   283     TESTL_imms_r32( 0x00000003, x86reg ); \
   284     JNE_exc(EXC_DATA_ADDR_WRITE);
   286 #define check_ralign64( x86reg ) \
   287     TESTL_imms_r32( 0x00000007, x86reg ); \
   288     JNE_exc(EXC_DATA_ADDR_READ)
   290 #define check_walign64( x86reg ) \
   291     TESTL_imms_r32( 0x00000007, x86reg ); \
   292     JNE_exc(EXC_DATA_ADDR_WRITE);
   294 #define UNDEF(ir)
   295 /* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
   296  * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
   297  */
   298 #ifdef HAVE_FRAME_ADDRESS
   299 static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
   300 {
   301     decode_address(addr_reg);
   302     if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
   303         CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
   304     } else {
   305         if( addr_reg != REG_ARG1 ) {
   306             MOVL_r32_r32( addr_reg, REG_ARG1 );
   307         }
   308         MOVP_immptr_rptr( 0, REG_ARG2 );
   309         sh4_x86_add_backpatch( xlat_output, pc, -2 );
   310         CALL2_r32disp_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2);
   311     }
   312     if( value_reg != REG_RESULT1 ) { 
   313         MOVL_r32_r32( REG_RESULT1, value_reg );
   314     }
   315 }
   317 static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
   318 {
   319     decode_address(addr_reg);
   320     if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
   321         CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
   322     } else {
   323         if( value_reg != REG_ARG2 ) {
   324             MOVL_r32_r32( value_reg, REG_ARG2 );
   325 	}        
   326         if( addr_reg != REG_ARG1 ) {
   327             MOVL_r32_r32( addr_reg, REG_ARG1 );
   328         }
   329 #if MAX_REG_ARG > 2        
   330         MOVP_immptr_rptr( 0, REG_ARG3 );
   331         sh4_x86_add_backpatch( xlat_output, pc, -2 );
   332         CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, REG_ARG3);
   333 #else
   334         MOVL_imm32_rspdisp( 0, 0 );
   335         sh4_x86_add_backpatch( xlat_output, pc, -2 );
   336         CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, 0);
   337 #endif
   338     }
   339 }
   340 #else
   341 static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
   342 {
   343     decode_address(addr_reg);
   344     CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
   345     if( value_reg != REG_RESULT1 ) {
   346         MOVL_r32_r32( REG_RESULT1, value_reg );
   347     }
   348 }     
   350 static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
   351 {
   352     decode_address(addr_reg);
   353     CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
   354 }
   355 #endif
   357 #define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
   358 #define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc)
   359 #define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) 
   360 #define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc)
   361 #define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc)
   362 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc)
   363 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc)
   364 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc)
   365 #define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc)
   367 #define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
   369 void sh4_translate_begin_block( sh4addr_t pc ) 
   370 {
   371     enter_block();
   372     sh4_x86.in_delay_slot = FALSE;
   373     sh4_x86.fpuen_checked = FALSE;
   374     sh4_x86.branch_taken = FALSE;
   375     sh4_x86.backpatch_posn = 0;
   376     sh4_x86.block_start_pc = pc;
   377     sh4_x86.tlb_on = IS_TLB_ENABLED();
   378     sh4_x86.tstate = TSTATE_NONE;
   379     sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
   380     sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
   381 }
   384 uint32_t sh4_translate_end_block_size()
   385 {
   386     if( sh4_x86.backpatch_posn <= 3 ) {
   387         return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
   388     } else {
   389         return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
   390     }
   391 }
   394 /**
   395  * Embed a breakpoint into the generated code
   396  */
   397 void sh4_translate_emit_breakpoint( sh4vma_t pc )
   398 {
   399     MOVL_imm32_r32( pc, REG_EAX );
   400     CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX );
   401     sh4_x86.tstate = TSTATE_NONE;
   402 }
   405 #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
   407 /**
   408  * Exit the block with sh4r.pc already written
   409  */
   410 void exit_block_pcset( sh4addr_t pc )
   411 {
   412     MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
   413     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
   414     MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
   415     if( sh4_x86.tlb_on ) {
   416         CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
   417     } else {
   418         CALL1_ptr_r32(xlat_get_code,REG_ARG1);
   419     }
   420     exit_block();
   421 }
   423 /**
   424  * Exit the block with sh4r.new_pc written with the target pc
   425  */
   426 void exit_block_newpcset( sh4addr_t pc )
   427 {
   428     MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
   429     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
   430     MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 );
   431     MOVL_r32_rbpdisp( REG_ARG1, R_PC );
   432     if( sh4_x86.tlb_on ) {
   433         CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
   434     } else {
   435         CALL1_ptr_r32(xlat_get_code,REG_ARG1);
   436     }
   437     exit_block();
   438 }
   441 /**
   442  * Exit the block to an absolute PC
   443  */
   444 void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
   445 {
   446     MOVL_imm32_r32( pc, REG_ECX );
   447     MOVL_r32_rbpdisp( REG_ECX, R_PC );
   448     if( IS_IN_ICACHE(pc) ) {
   449         MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
   450         ANDP_imms_rptr( -4, REG_EAX );
   451     } else if( sh4_x86.tlb_on ) {
   452         CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
   453     } else {
   454         CALL1_ptr_r32(xlat_get_code, REG_ECX);
   455     }
   456     MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
   457     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
   458     exit_block();
   459 }
   461 /**
   462  * Exit the block to a relative PC
   463  */
   464 void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
   465 {
   466     MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
   467     ADDL_rbpdisp_r32( R_PC, REG_ECX );
   468     MOVL_r32_rbpdisp( REG_ECX, R_PC );
   469     if( IS_IN_ICACHE(pc) ) {
   470         MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
   471         ANDP_imms_rptr( -4, REG_EAX );
   472     } else if( sh4_x86.tlb_on ) {
   473         CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
   474     } else {
   475         CALL1_ptr_r32(xlat_get_code, REG_ECX);
   476     }
   477     MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
   478     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
   479     exit_block();
   480 }
   482 /**
   483  * Exit unconditionally with a general exception
   484  */
   485 void exit_block_exc( int code, sh4addr_t pc )
   486 {
   487     MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
   488     ADDL_r32_rbpdisp( REG_ECX, R_PC );
   489     MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
   490     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
   491     MOVL_imm32_r32( code, REG_ARG1 );
   492     CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
   493     MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
   494     if( sh4_x86.tlb_on ) {
   495         CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
   496     } else {
   497         CALL1_ptr_r32(xlat_get_code,REG_ARG1);
   498     }
   500     exit_block();
   501 }    
   503 /**
   504  * Embed a call to sh4_execute_instruction for situations that we
   505  * can't translate (just page-crossing delay slots at the moment).
   506  * Caller is responsible for setting new_pc before calling this function.
   507  *
   508  * Performs:
   509  *   Set PC = endpc
   510  *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
   511  *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
   512  *   Call sh4_execute_instruction
   513  *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
   514  */
   515 void exit_block_emu( sh4vma_t endpc )
   516 {
   517     MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX );   // 5
   518     ADDL_r32_rbpdisp( REG_ECX, R_PC );
   520     MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5
   521     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
   522     MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX );
   523     MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) );
   525     CALL_ptr( sh4_execute_instruction );    
   526     MOVL_rbpdisp_r32( R_PC, REG_EAX );
   527     if( sh4_x86.tlb_on ) {
   528 	CALL1_ptr_r32(xlat_get_code_by_vma,REG_EAX);
   529     } else {
   530 	CALL1_ptr_r32(xlat_get_code,REG_EAX);
   531     }
   532     exit_block();
   533 } 
   535 /**
   536  * Write the block trailer (exception handling block)
   537  */
   538 void sh4_translate_end_block( sh4addr_t pc ) {
   539     if( sh4_x86.branch_taken == FALSE ) {
   540         // Didn't exit unconditionally already, so write the termination here
   541         exit_block_rel( pc, pc );
   542     }
   543     if( sh4_x86.backpatch_posn != 0 ) {
   544         unsigned int i;
   545         // Exception raised - cleanup and exit
   546         uint8_t *end_ptr = xlat_output;
   547         MOVL_r32_r32( REG_EDX, REG_ECX );
   548         ADDL_r32_r32( REG_EDX, REG_ECX );
   549         ADDL_r32_rbpdisp( REG_ECX, R_SPC );
   550         MOVL_moffptr_eax( &sh4_cpu_period );
   551         MULL_r32( REG_EDX );
   552         ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
   553         MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
   554         if( sh4_x86.tlb_on ) {
   555             CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1);
   556         } else {
   557             CALL1_ptr_r32(xlat_get_code, REG_ARG1);
   558         }
   559         exit_block();
   561         for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
   562             uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
   563             if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
   564                 if( sh4_x86.backpatch_list[i].exc_code == -2 ) {
   565                     *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; 
   566                 } else {
   567                     *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
   568                 }
   569                 MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
   570                 int rel = end_ptr - xlat_output;
   571                 JMP_prerel(rel);
   572             } else {
   573                 *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
   574                 MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 );
   575                 CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
   576                 MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
   577                 int rel = end_ptr - xlat_output;
   578                 JMP_prerel(rel);
   579             }
   580         }
   581     }
   582 }
   584 /**
   585  * Translate a single instruction. Delayed branches are handled specially
   586  * by translating both branch and delayed instruction as a single unit (as
   587  * 
   588  * The instruction MUST be in the icache (assert check)
   589  *
   590  * @return true if the instruction marks the end of a basic block
   591  * (eg a branch or 
   592  */
   593 uint32_t sh4_translate_instruction( sh4vma_t pc )
   594 {
   595     uint32_t ir;
   596     /* Read instruction from icache */
   597     assert( IS_IN_ICACHE(pc) );
   598     ir = *(uint16_t *)GET_ICACHE_PTR(pc);
   600     if( !sh4_x86.in_delay_slot ) {
   601 	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
   602     }
   604     /* check for breakpoints at this pc */
   605     for( int i=0; i<sh4_breakpoint_count; i++ ) {
   606         if( sh4_breakpoints[i].address == pc ) {
   607             sh4_translate_emit_breakpoint(pc);
   608             break;
   609         }
   610     }
   611 %%
   612 /* ALU operations */
   613 ADD Rm, Rn {:
   614     COUNT_INST(I_ADD);
   615     load_reg( REG_EAX, Rm );
   616     load_reg( REG_ECX, Rn );
   617     ADDL_r32_r32( REG_EAX, REG_ECX );
   618     store_reg( REG_ECX, Rn );
   619     sh4_x86.tstate = TSTATE_NONE;
   620 :}
   621 ADD #imm, Rn {:  
   622     COUNT_INST(I_ADDI);
   623     ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
   624     sh4_x86.tstate = TSTATE_NONE;
   625 :}
   626 ADDC Rm, Rn {:
   627     COUNT_INST(I_ADDC);
   628     if( sh4_x86.tstate != TSTATE_C ) {
   629         LDC_t();
   630     }
   631     load_reg( REG_EAX, Rm );
   632     load_reg( REG_ECX, Rn );
   633     ADCL_r32_r32( REG_EAX, REG_ECX );
   634     store_reg( REG_ECX, Rn );
   635     SETC_t();
   636     sh4_x86.tstate = TSTATE_C;
   637 :}
   638 ADDV Rm, Rn {:
   639     COUNT_INST(I_ADDV);
   640     load_reg( REG_EAX, Rm );
   641     load_reg( REG_ECX, Rn );
   642     ADDL_r32_r32( REG_EAX, REG_ECX );
   643     store_reg( REG_ECX, Rn );
   644     SETO_t();
   645     sh4_x86.tstate = TSTATE_O;
   646 :}
   647 AND Rm, Rn {:
   648     COUNT_INST(I_AND);
   649     load_reg( REG_EAX, Rm );
   650     load_reg( REG_ECX, Rn );
   651     ANDL_r32_r32( REG_EAX, REG_ECX );
   652     store_reg( REG_ECX, Rn );
   653     sh4_x86.tstate = TSTATE_NONE;
   654 :}
   655 AND #imm, R0 {:  
   656     COUNT_INST(I_ANDI);
   657     load_reg( REG_EAX, 0 );
   658     ANDL_imms_r32(imm, REG_EAX); 
   659     store_reg( REG_EAX, 0 );
   660     sh4_x86.tstate = TSTATE_NONE;
   661 :}
   662 AND.B #imm, @(R0, GBR) {: 
   663     COUNT_INST(I_ANDB);
   664     load_reg( REG_EAX, 0 );
   665     ADDL_rbpdisp_r32( R_GBR, REG_EAX );
   666     MOVL_r32_rspdisp(REG_EAX, 0);
   667     MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
   668     MOVL_rspdisp_r32(0, REG_EAX);
   669     ANDL_imms_r32(imm, REG_EDX );
   670     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
   671     sh4_x86.tstate = TSTATE_NONE;
   672 :}
   673 CMP/EQ Rm, Rn {:  
   674     COUNT_INST(I_CMPEQ);
   675     load_reg( REG_EAX, Rm );
   676     load_reg( REG_ECX, Rn );
   677     CMPL_r32_r32( REG_EAX, REG_ECX );
   678     SETE_t();
   679     sh4_x86.tstate = TSTATE_E;
   680 :}
   681 CMP/EQ #imm, R0 {:  
   682     COUNT_INST(I_CMPEQI);
   683     load_reg( REG_EAX, 0 );
   684     CMPL_imms_r32(imm, REG_EAX);
   685     SETE_t();
   686     sh4_x86.tstate = TSTATE_E;
   687 :}
   688 CMP/GE Rm, Rn {:  
   689     COUNT_INST(I_CMPGE);
   690     load_reg( REG_EAX, Rm );
   691     load_reg( REG_ECX, Rn );
   692     CMPL_r32_r32( REG_EAX, REG_ECX );
   693     SETGE_t();
   694     sh4_x86.tstate = TSTATE_GE;
   695 :}
   696 CMP/GT Rm, Rn {: 
   697     COUNT_INST(I_CMPGT);
   698     load_reg( REG_EAX, Rm );
   699     load_reg( REG_ECX, Rn );
   700     CMPL_r32_r32( REG_EAX, REG_ECX );
   701     SETG_t();
   702     sh4_x86.tstate = TSTATE_G;
   703 :}
   704 CMP/HI Rm, Rn {:  
   705     COUNT_INST(I_CMPHI);
   706     load_reg( REG_EAX, Rm );
   707     load_reg( REG_ECX, Rn );
   708     CMPL_r32_r32( REG_EAX, REG_ECX );
   709     SETA_t();
   710     sh4_x86.tstate = TSTATE_A;
   711 :}
   712 CMP/HS Rm, Rn {: 
   713     COUNT_INST(I_CMPHS);
   714     load_reg( REG_EAX, Rm );
   715     load_reg( REG_ECX, Rn );
   716     CMPL_r32_r32( REG_EAX, REG_ECX );
   717     SETAE_t();
   718     sh4_x86.tstate = TSTATE_AE;
   719  :}
   720 CMP/PL Rn {: 
   721     COUNT_INST(I_CMPPL);
   722     load_reg( REG_EAX, Rn );
   723     CMPL_imms_r32( 0, REG_EAX );
   724     SETG_t();
   725     sh4_x86.tstate = TSTATE_G;
   726 :}
   727 CMP/PZ Rn {:  
   728     COUNT_INST(I_CMPPZ);
   729     load_reg( REG_EAX, Rn );
   730     CMPL_imms_r32( 0, REG_EAX );
   731     SETGE_t();
   732     sh4_x86.tstate = TSTATE_GE;
   733 :}
   734 CMP/STR Rm, Rn {:  
   735     COUNT_INST(I_CMPSTR);
   736     load_reg( REG_EAX, Rm );
   737     load_reg( REG_ECX, Rn );
   738     XORL_r32_r32( REG_ECX, REG_EAX );
   739     TESTB_r8_r8( REG_AL, REG_AL );
   740     JE_label(target1);
   741     TESTB_r8_r8( REG_AH, REG_AH );
   742     JE_label(target2);
   743     SHRL_imm_r32( 16, REG_EAX );
   744     TESTB_r8_r8( REG_AL, REG_AL );
   745     JE_label(target3);
   746     TESTB_r8_r8( REG_AH, REG_AH );
   747     JMP_TARGET(target1);
   748     JMP_TARGET(target2);
   749     JMP_TARGET(target3);
   750     SETE_t();
   751     sh4_x86.tstate = TSTATE_E;
   752 :}
   753 DIV0S Rm, Rn {:
   754     COUNT_INST(I_DIV0S);
   755     load_reg( REG_EAX, Rm );
   756     load_reg( REG_ECX, Rn );
   757     SHRL_imm_r32( 31, REG_EAX );
   758     SHRL_imm_r32( 31, REG_ECX );
   759     MOVL_r32_rbpdisp( REG_EAX, R_M );
   760     MOVL_r32_rbpdisp( REG_ECX, R_Q );
   761     CMPL_r32_r32( REG_EAX, REG_ECX );
   762     SETNE_t();
   763     sh4_x86.tstate = TSTATE_NE;
   764 :}
   765 DIV0U {:  
   766     COUNT_INST(I_DIV0U);
   767     XORL_r32_r32( REG_EAX, REG_EAX );
   768     MOVL_r32_rbpdisp( REG_EAX, R_Q );
   769     MOVL_r32_rbpdisp( REG_EAX, R_M );
   770     MOVL_r32_rbpdisp( REG_EAX, R_T );
   771     sh4_x86.tstate = TSTATE_C; // works for DIV1
   772 :}
   773 DIV1 Rm, Rn {:
   774     COUNT_INST(I_DIV1);
   775     MOVL_rbpdisp_r32( R_M, REG_ECX );
   776     load_reg( REG_EAX, Rn );
   777     if( sh4_x86.tstate != TSTATE_C ) {
   778 	LDC_t();
   779     }
   780     RCLL_imm_r32( 1, REG_EAX );
   781     SETC_r8( REG_DL ); // Q'
   782     CMPL_rbpdisp_r32( R_Q, REG_ECX );
   783     JE_label(mqequal);
   784     ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
   785     JMP_label(end);
   786     JMP_TARGET(mqequal);
   787     SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
   788     JMP_TARGET(end);
   789     store_reg( REG_EAX, Rn ); // Done with Rn now
   790     SETC_r8(REG_AL); // tmp1
   791     XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
   792     XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
   793     MOVL_r32_rbpdisp( REG_ECX, R_Q );
   794     XORL_imms_r32( 1, REG_AL );   // T = !Q'
   795     MOVZXL_r8_r32( REG_AL, REG_EAX );
   796     MOVL_r32_rbpdisp( REG_EAX, R_T );
   797     sh4_x86.tstate = TSTATE_NONE;
   798 :}
   799 DMULS.L Rm, Rn {:  
   800     COUNT_INST(I_DMULS);
   801     load_reg( REG_EAX, Rm );
   802     load_reg( REG_ECX, Rn );
   803     IMULL_r32(REG_ECX);
   804     MOVL_r32_rbpdisp( REG_EDX, R_MACH );
   805     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
   806     sh4_x86.tstate = TSTATE_NONE;
   807 :}
   808 DMULU.L Rm, Rn {:  
   809     COUNT_INST(I_DMULU);
   810     load_reg( REG_EAX, Rm );
   811     load_reg( REG_ECX, Rn );
   812     MULL_r32(REG_ECX);
   813     MOVL_r32_rbpdisp( REG_EDX, R_MACH );
   814     MOVL_r32_rbpdisp( REG_EAX, R_MACL );    
   815     sh4_x86.tstate = TSTATE_NONE;
   816 :}
   817 DT Rn {:  
   818     COUNT_INST(I_DT);
   819     load_reg( REG_EAX, Rn );
   820     ADDL_imms_r32( -1, REG_EAX );
   821     store_reg( REG_EAX, Rn );
   822     SETE_t();
   823     sh4_x86.tstate = TSTATE_E;
   824 :}
   825 EXTS.B Rm, Rn {:  
   826     COUNT_INST(I_EXTSB);
   827     load_reg( REG_EAX, Rm );
   828     MOVSXL_r8_r32( REG_EAX, REG_EAX );
   829     store_reg( REG_EAX, Rn );
   830 :}
   831 EXTS.W Rm, Rn {:  
   832     COUNT_INST(I_EXTSW);
   833     load_reg( REG_EAX, Rm );
   834     MOVSXL_r16_r32( REG_EAX, REG_EAX );
   835     store_reg( REG_EAX, Rn );
   836 :}
   837 EXTU.B Rm, Rn {:  
   838     COUNT_INST(I_EXTUB);
   839     load_reg( REG_EAX, Rm );
   840     MOVZXL_r8_r32( REG_EAX, REG_EAX );
   841     store_reg( REG_EAX, Rn );
   842 :}
   843 EXTU.W Rm, Rn {:  
   844     COUNT_INST(I_EXTUW);
   845     load_reg( REG_EAX, Rm );
   846     MOVZXL_r16_r32( REG_EAX, REG_EAX );
   847     store_reg( REG_EAX, Rn );
   848 :}
   849 MAC.L @Rm+, @Rn+ {:
   850     COUNT_INST(I_MACL);
   851     if( Rm == Rn ) {
   852 	load_reg( REG_EAX, Rm );
   853 	check_ralign32( REG_EAX );
   854 	MEM_READ_LONG( REG_EAX, REG_EAX );
   855 	MOVL_r32_rspdisp(REG_EAX, 0);
   856 	load_reg( REG_EAX, Rm );
   857 	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
   858 	MEM_READ_LONG( REG_EAX, REG_EAX );
   859         ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
   860     } else {
   861 	load_reg( REG_EAX, Rm );
   862 	check_ralign32( REG_EAX );
   863 	MEM_READ_LONG( REG_EAX, REG_EAX );
   864 	MOVL_r32_rspdisp( REG_EAX, 0 );
   865 	load_reg( REG_EAX, Rn );
   866 	check_ralign32( REG_EAX );
   867 	MEM_READ_LONG( REG_EAX, REG_EAX );
   868 	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
   869 	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
   870     }
   872     IMULL_rspdisp( 0 );
   873     ADDL_r32_rbpdisp( REG_EAX, R_MACL );
   874     ADCL_r32_rbpdisp( REG_EDX, R_MACH );
   876     MOVL_rbpdisp_r32( R_S, REG_ECX );
   877     TESTL_r32_r32(REG_ECX, REG_ECX);
   878     JE_label( nosat );
   879     CALL_ptr( signsat48 );
   880     JMP_TARGET( nosat );
   881     sh4_x86.tstate = TSTATE_NONE;
   882 :}
   883 MAC.W @Rm+, @Rn+ {:  
   884     COUNT_INST(I_MACW);
   885     if( Rm == Rn ) {
   886 	load_reg( REG_EAX, Rm );
   887 	check_ralign16( REG_EAX );
   888 	MEM_READ_WORD( REG_EAX, REG_EAX );
   889         MOVL_r32_rspdisp( REG_EAX, 0 );
   890 	load_reg( REG_EAX, Rm );
   891 	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
   892 	MEM_READ_WORD( REG_EAX, REG_EAX );
   893 	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
   894 	// Note translate twice in case of page boundaries. Maybe worth
   895 	// adding a page-boundary check to skip the second translation
   896     } else {
   897 	load_reg( REG_EAX, Rm );
   898 	check_ralign16( REG_EAX );
   899 	MEM_READ_WORD( REG_EAX, REG_EAX );
   900         MOVL_r32_rspdisp( REG_EAX, 0 );
   901 	load_reg( REG_EAX, Rn );
   902 	check_ralign16( REG_EAX );
   903 	MEM_READ_WORD( REG_EAX, REG_EAX );
   904 	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
   905 	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
   906     }
   907     IMULL_rspdisp( 0 );
   908     MOVL_rbpdisp_r32( R_S, REG_ECX );
   909     TESTL_r32_r32( REG_ECX, REG_ECX );
   910     JE_label( nosat );
   912     ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
   913     JNO_label( end );            // 2
   914     MOVL_imm32_r32( 1, REG_EDX );         // 5
   915     MOVL_r32_rbpdisp( REG_EDX, R_MACH );   // 6
   916     JS_label( positive );        // 2
   917     MOVL_imm32_r32( 0x80000000, REG_EAX );// 5
   918     MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
   919     JMP_label(end2);           // 2
   921     JMP_TARGET(positive);
   922     MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5
   923     MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
   924     JMP_label(end3);            // 2
   926     JMP_TARGET(nosat);
   927     ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
   928     ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
   929     JMP_TARGET(end);
   930     JMP_TARGET(end2);
   931     JMP_TARGET(end3);
   932     sh4_x86.tstate = TSTATE_NONE;
   933 :}
   934 MOVT Rn {:  
   935     COUNT_INST(I_MOVT);
   936     MOVL_rbpdisp_r32( R_T, REG_EAX );
   937     store_reg( REG_EAX, Rn );
   938 :}
   939 MUL.L Rm, Rn {:  
   940     COUNT_INST(I_MULL);
   941     load_reg( REG_EAX, Rm );
   942     load_reg( REG_ECX, Rn );
   943     MULL_r32( REG_ECX );
   944     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
   945     sh4_x86.tstate = TSTATE_NONE;
   946 :}
   947 MULS.W Rm, Rn {:
   948     COUNT_INST(I_MULSW);
   949     MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
   950     MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
   951     MULL_r32( REG_ECX );
   952     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
   953     sh4_x86.tstate = TSTATE_NONE;
   954 :}
   955 MULU.W Rm, Rn {:  
   956     COUNT_INST(I_MULUW);
   957     MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
   958     MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
   959     MULL_r32( REG_ECX );
   960     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
   961     sh4_x86.tstate = TSTATE_NONE;
   962 :}
   963 NEG Rm, Rn {:
   964     COUNT_INST(I_NEG);
   965     load_reg( REG_EAX, Rm );
   966     NEGL_r32( REG_EAX );
   967     store_reg( REG_EAX, Rn );
   968     sh4_x86.tstate = TSTATE_NONE;
   969 :}
   970 NEGC Rm, Rn {:  
   971     COUNT_INST(I_NEGC);
   972     load_reg( REG_EAX, Rm );
   973     XORL_r32_r32( REG_ECX, REG_ECX );
   974     LDC_t();
   975     SBBL_r32_r32( REG_EAX, REG_ECX );
   976     store_reg( REG_ECX, Rn );
   977     SETC_t();
   978     sh4_x86.tstate = TSTATE_C;
   979 :}
   980 NOT Rm, Rn {:  
   981     COUNT_INST(I_NOT);
   982     load_reg( REG_EAX, Rm );
   983     NOTL_r32( REG_EAX );
   984     store_reg( REG_EAX, Rn );
   985     sh4_x86.tstate = TSTATE_NONE;
   986 :}
   987 OR Rm, Rn {:  
   988     COUNT_INST(I_OR);
   989     load_reg( REG_EAX, Rm );
   990     load_reg( REG_ECX, Rn );
   991     ORL_r32_r32( REG_EAX, REG_ECX );
   992     store_reg( REG_ECX, Rn );
   993     sh4_x86.tstate = TSTATE_NONE;
   994 :}
   995 OR #imm, R0 {:
   996     COUNT_INST(I_ORI);
   997     load_reg( REG_EAX, 0 );
   998     ORL_imms_r32(imm, REG_EAX);
   999     store_reg( REG_EAX, 0 );
  1000     sh4_x86.tstate = TSTATE_NONE;
  1001 :}
  1002 OR.B #imm, @(R0, GBR) {:  
  1003     COUNT_INST(I_ORB);
  1004     load_reg( REG_EAX, 0 );
  1005     ADDL_rbpdisp_r32( R_GBR, REG_EAX );
  1006     MOVL_r32_rspdisp( REG_EAX, 0 );
  1007     MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
  1008     MOVL_rspdisp_r32( 0, REG_EAX );
  1009     ORL_imms_r32(imm, REG_EDX );
  1010     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  1011     sh4_x86.tstate = TSTATE_NONE;
  1012 :}
  1013 ROTCL Rn {:
  1014     COUNT_INST(I_ROTCL);
  1015     load_reg( REG_EAX, Rn );
  1016     if( sh4_x86.tstate != TSTATE_C ) {
  1017 	LDC_t();
  1019     RCLL_imm_r32( 1, REG_EAX );
  1020     store_reg( REG_EAX, Rn );
  1021     SETC_t();
  1022     sh4_x86.tstate = TSTATE_C;
  1023 :}
  1024 ROTCR Rn {:  
  1025     COUNT_INST(I_ROTCR);
  1026     load_reg( REG_EAX, Rn );
  1027     if( sh4_x86.tstate != TSTATE_C ) {
  1028 	LDC_t();
  1030     RCRL_imm_r32( 1, REG_EAX );
  1031     store_reg( REG_EAX, Rn );
  1032     SETC_t();
  1033     sh4_x86.tstate = TSTATE_C;
  1034 :}
  1035 ROTL Rn {:  
  1036     COUNT_INST(I_ROTL);
  1037     load_reg( REG_EAX, Rn );
  1038     ROLL_imm_r32( 1, REG_EAX );
  1039     store_reg( REG_EAX, Rn );
  1040     SETC_t();
  1041     sh4_x86.tstate = TSTATE_C;
  1042 :}
  1043 ROTR Rn {:  
  1044     COUNT_INST(I_ROTR);
  1045     load_reg( REG_EAX, Rn );
  1046     RORL_imm_r32( 1, REG_EAX );
  1047     store_reg( REG_EAX, Rn );
  1048     SETC_t();
  1049     sh4_x86.tstate = TSTATE_C;
  1050 :}
  1051 SHAD Rm, Rn {:
  1052     COUNT_INST(I_SHAD);
  1053     /* Annoyingly enough, not directly convertible */
  1054     load_reg( REG_EAX, Rn );
  1055     load_reg( REG_ECX, Rm );
  1056     CMPL_imms_r32( 0, REG_ECX );
  1057     JGE_label(doshl);
  1059     NEGL_r32( REG_ECX );      // 2
  1060     ANDB_imms_r8( 0x1F, REG_CL ); // 3
  1061     JE_label(emptysar);     // 2
  1062     SARL_cl_r32( REG_EAX );       // 2
  1063     JMP_label(end);          // 2
  1065     JMP_TARGET(emptysar);
  1066     SARL_imm_r32(31, REG_EAX );  // 3
  1067     JMP_label(end2);
  1069     JMP_TARGET(doshl);
  1070     ANDB_imms_r8( 0x1F, REG_CL ); // 3
  1071     SHLL_cl_r32( REG_EAX );       // 2
  1072     JMP_TARGET(end);
  1073     JMP_TARGET(end2);
  1074     store_reg( REG_EAX, Rn );
  1075     sh4_x86.tstate = TSTATE_NONE;
  1076 :}
  1077 SHLD Rm, Rn {:  
  1078     COUNT_INST(I_SHLD);
  1079     load_reg( REG_EAX, Rn );
  1080     load_reg( REG_ECX, Rm );
  1081     CMPL_imms_r32( 0, REG_ECX );
  1082     JGE_label(doshl);
  1084     NEGL_r32( REG_ECX );      // 2
  1085     ANDB_imms_r8( 0x1F, REG_CL ); // 3
  1086     JE_label(emptyshr );
  1087     SHRL_cl_r32( REG_EAX );       // 2
  1088     JMP_label(end);          // 2
  1090     JMP_TARGET(emptyshr);
  1091     XORL_r32_r32( REG_EAX, REG_EAX );
  1092     JMP_label(end2);
  1094     JMP_TARGET(doshl);
  1095     ANDB_imms_r8( 0x1F, REG_CL ); // 3
  1096     SHLL_cl_r32( REG_EAX );       // 2
  1097     JMP_TARGET(end);
  1098     JMP_TARGET(end2);
  1099     store_reg( REG_EAX, Rn );
  1100     sh4_x86.tstate = TSTATE_NONE;
  1101 :}
  1102 SHAL Rn {: 
  1103     COUNT_INST(I_SHAL);
  1104     load_reg( REG_EAX, Rn );
  1105     SHLL_imm_r32( 1, REG_EAX );
  1106     SETC_t();
  1107     store_reg( REG_EAX, Rn );
  1108     sh4_x86.tstate = TSTATE_C;
  1109 :}
  1110 SHAR Rn {:  
  1111     COUNT_INST(I_SHAR);
  1112     load_reg( REG_EAX, Rn );
  1113     SARL_imm_r32( 1, REG_EAX );
  1114     SETC_t();
  1115     store_reg( REG_EAX, Rn );
  1116     sh4_x86.tstate = TSTATE_C;
  1117 :}
  1118 SHLL Rn {:  
  1119     COUNT_INST(I_SHLL);
  1120     load_reg( REG_EAX, Rn );
  1121     SHLL_imm_r32( 1, REG_EAX );
  1122     SETC_t();
  1123     store_reg( REG_EAX, Rn );
  1124     sh4_x86.tstate = TSTATE_C;
  1125 :}
  1126 SHLL2 Rn {:
  1127     COUNT_INST(I_SHLL);
  1128     load_reg( REG_EAX, Rn );
  1129     SHLL_imm_r32( 2, REG_EAX );
  1130     store_reg( REG_EAX, Rn );
  1131     sh4_x86.tstate = TSTATE_NONE;
  1132 :}
  1133 SHLL8 Rn {:  
  1134     COUNT_INST(I_SHLL);
  1135     load_reg( REG_EAX, Rn );
  1136     SHLL_imm_r32( 8, REG_EAX );
  1137     store_reg( REG_EAX, Rn );
  1138     sh4_x86.tstate = TSTATE_NONE;
  1139 :}
  1140 SHLL16 Rn {:  
  1141     COUNT_INST(I_SHLL);
  1142     load_reg( REG_EAX, Rn );
  1143     SHLL_imm_r32( 16, REG_EAX );
  1144     store_reg( REG_EAX, Rn );
  1145     sh4_x86.tstate = TSTATE_NONE;
  1146 :}
  1147 SHLR Rn {:  
  1148     COUNT_INST(I_SHLR);
  1149     load_reg( REG_EAX, Rn );
  1150     SHRL_imm_r32( 1, REG_EAX );
  1151     SETC_t();
  1152     store_reg( REG_EAX, Rn );
  1153     sh4_x86.tstate = TSTATE_C;
  1154 :}
  1155 SHLR2 Rn {:  
  1156     COUNT_INST(I_SHLR);
  1157     load_reg( REG_EAX, Rn );
  1158     SHRL_imm_r32( 2, REG_EAX );
  1159     store_reg( REG_EAX, Rn );
  1160     sh4_x86.tstate = TSTATE_NONE;
  1161 :}
  1162 SHLR8 Rn {:  
  1163     COUNT_INST(I_SHLR);
  1164     load_reg( REG_EAX, Rn );
  1165     SHRL_imm_r32( 8, REG_EAX );
  1166     store_reg( REG_EAX, Rn );
  1167     sh4_x86.tstate = TSTATE_NONE;
  1168 :}
  1169 SHLR16 Rn {:  
  1170     COUNT_INST(I_SHLR);
  1171     load_reg( REG_EAX, Rn );
  1172     SHRL_imm_r32( 16, REG_EAX );
  1173     store_reg( REG_EAX, Rn );
  1174     sh4_x86.tstate = TSTATE_NONE;
  1175 :}
  1176 SUB Rm, Rn {:  
  1177     COUNT_INST(I_SUB);
  1178     load_reg( REG_EAX, Rm );
  1179     load_reg( REG_ECX, Rn );
  1180     SUBL_r32_r32( REG_EAX, REG_ECX );
  1181     store_reg( REG_ECX, Rn );
  1182     sh4_x86.tstate = TSTATE_NONE;
  1183 :}
  1184 SUBC Rm, Rn {:  
  1185     COUNT_INST(I_SUBC);
  1186     load_reg( REG_EAX, Rm );
  1187     load_reg( REG_ECX, Rn );
  1188     if( sh4_x86.tstate != TSTATE_C ) {
  1189 	LDC_t();
  1191     SBBL_r32_r32( REG_EAX, REG_ECX );
  1192     store_reg( REG_ECX, Rn );
  1193     SETC_t();
  1194     sh4_x86.tstate = TSTATE_C;
  1195 :}
  1196 SUBV Rm, Rn {:  
  1197     COUNT_INST(I_SUBV);
  1198     load_reg( REG_EAX, Rm );
  1199     load_reg( REG_ECX, Rn );
  1200     SUBL_r32_r32( REG_EAX, REG_ECX );
  1201     store_reg( REG_ECX, Rn );
  1202     SETO_t();
  1203     sh4_x86.tstate = TSTATE_O;
  1204 :}
  1205 SWAP.B Rm, Rn {:  
  1206     COUNT_INST(I_SWAPB);
  1207     load_reg( REG_EAX, Rm );
  1208     XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
  1209     store_reg( REG_EAX, Rn );
  1210 :}
  1211 SWAP.W Rm, Rn {:  
  1212     COUNT_INST(I_SWAPB);
  1213     load_reg( REG_EAX, Rm );
  1214     MOVL_r32_r32( REG_EAX, REG_ECX );
  1215     SHLL_imm_r32( 16, REG_ECX );
  1216     SHRL_imm_r32( 16, REG_EAX );
  1217     ORL_r32_r32( REG_EAX, REG_ECX );
  1218     store_reg( REG_ECX, Rn );
  1219     sh4_x86.tstate = TSTATE_NONE;
  1220 :}
  1221 TAS.B @Rn {:  
  1222     COUNT_INST(I_TASB);
  1223     load_reg( REG_EAX, Rn );
  1224     MOVL_r32_rspdisp( REG_EAX, 0 );
  1225     MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
  1226     TESTB_r8_r8( REG_DL, REG_DL );
  1227     SETE_t();
  1228     ORB_imms_r8( 0x80, REG_DL );
  1229     MOVL_rspdisp_r32( 0, REG_EAX );
  1230     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  1231     sh4_x86.tstate = TSTATE_NONE;
  1232 :}
  1233 TST Rm, Rn {:  
  1234     COUNT_INST(I_TST);
  1235     load_reg( REG_EAX, Rm );
  1236     load_reg( REG_ECX, Rn );
  1237     TESTL_r32_r32( REG_EAX, REG_ECX );
  1238     SETE_t();
  1239     sh4_x86.tstate = TSTATE_E;
  1240 :}
  1241 TST #imm, R0 {:  
  1242     COUNT_INST(I_TSTI);
  1243     load_reg( REG_EAX, 0 );
  1244     TESTL_imms_r32( imm, REG_EAX );
  1245     SETE_t();
  1246     sh4_x86.tstate = TSTATE_E;
  1247 :}
  1248 TST.B #imm, @(R0, GBR) {:  
  1249     COUNT_INST(I_TSTB);
  1250     load_reg( REG_EAX, 0);
  1251     ADDL_rbpdisp_r32( R_GBR, REG_EAX );
  1252     MEM_READ_BYTE( REG_EAX, REG_EAX );
  1253     TESTB_imms_r8( imm, REG_AL );
  1254     SETE_t();
  1255     sh4_x86.tstate = TSTATE_E;
  1256 :}
  1257 XOR Rm, Rn {:  
  1258     COUNT_INST(I_XOR);
  1259     load_reg( REG_EAX, Rm );
  1260     load_reg( REG_ECX, Rn );
  1261     XORL_r32_r32( REG_EAX, REG_ECX );
  1262     store_reg( REG_ECX, Rn );
  1263     sh4_x86.tstate = TSTATE_NONE;
  1264 :}
  1265 XOR #imm, R0 {:  
  1266     COUNT_INST(I_XORI);
  1267     load_reg( REG_EAX, 0 );
  1268     XORL_imms_r32( imm, REG_EAX );
  1269     store_reg( REG_EAX, 0 );
  1270     sh4_x86.tstate = TSTATE_NONE;
  1271 :}
  1272 XOR.B #imm, @(R0, GBR) {:  
  1273     COUNT_INST(I_XORB);
  1274     load_reg( REG_EAX, 0 );
  1275     ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
  1276     MOVL_r32_rspdisp( REG_EAX, 0 );
  1277     MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
  1278     MOVL_rspdisp_r32( 0, REG_EAX );
  1279     XORL_imms_r32( imm, REG_EDX );
  1280     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  1281     sh4_x86.tstate = TSTATE_NONE;
  1282 :}
  1283 XTRCT Rm, Rn {:
  1284     COUNT_INST(I_XTRCT);
  1285     load_reg( REG_EAX, Rm );
  1286     load_reg( REG_ECX, Rn );
  1287     SHLL_imm_r32( 16, REG_EAX );
  1288     SHRL_imm_r32( 16, REG_ECX );
  1289     ORL_r32_r32( REG_EAX, REG_ECX );
  1290     store_reg( REG_ECX, Rn );
  1291     sh4_x86.tstate = TSTATE_NONE;
  1292 :}
  1294 /* Data move instructions */
  1295 MOV Rm, Rn {:  
  1296     COUNT_INST(I_MOV);
  1297     load_reg( REG_EAX, Rm );
  1298     store_reg( REG_EAX, Rn );
  1299 :}
  1300 MOV #imm, Rn {:  
  1301     COUNT_INST(I_MOVI);
  1302     MOVL_imm32_r32( imm, REG_EAX );
  1303     store_reg( REG_EAX, Rn );
  1304 :}
  1305 MOV.B Rm, @Rn {:  
  1306     COUNT_INST(I_MOVB);
  1307     load_reg( REG_EAX, Rn );
  1308     load_reg( REG_EDX, Rm );
  1309     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  1310     sh4_x86.tstate = TSTATE_NONE;
  1311 :}
  1312 MOV.B Rm, @-Rn {:  
  1313     COUNT_INST(I_MOVB);
  1314     load_reg( REG_EAX, Rn );
  1315     LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
  1316     load_reg( REG_EDX, Rm );
  1317     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  1318     ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
  1319     sh4_x86.tstate = TSTATE_NONE;
  1320 :}
  1321 MOV.B Rm, @(R0, Rn) {:  
  1322     COUNT_INST(I_MOVB);
  1323     load_reg( REG_EAX, 0 );
  1324     ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
  1325     load_reg( REG_EDX, Rm );
  1326     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  1327     sh4_x86.tstate = TSTATE_NONE;
  1328 :}
  1329 MOV.B R0, @(disp, GBR) {:  
  1330     COUNT_INST(I_MOVB);
  1331     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
  1332     ADDL_imms_r32( disp, REG_EAX );
  1333     load_reg( REG_EDX, 0 );
  1334     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  1335     sh4_x86.tstate = TSTATE_NONE;
  1336 :}
  1337 MOV.B R0, @(disp, Rn) {:  
  1338     COUNT_INST(I_MOVB);
  1339     load_reg( REG_EAX, Rn );
  1340     ADDL_imms_r32( disp, REG_EAX );
  1341     load_reg( REG_EDX, 0 );
  1342     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  1343     sh4_x86.tstate = TSTATE_NONE;
  1344 :}
  1345 MOV.B @Rm, Rn {:  
  1346     COUNT_INST(I_MOVB);
  1347     load_reg( REG_EAX, Rm );
  1348     MEM_READ_BYTE( REG_EAX, REG_EAX );
  1349     store_reg( REG_EAX, Rn );
  1350     sh4_x86.tstate = TSTATE_NONE;
  1351 :}
  1352 MOV.B @Rm+, Rn {:  
  1353     COUNT_INST(I_MOVB);
  1354     load_reg( REG_EAX, Rm );
  1355     MEM_READ_BYTE( REG_EAX, REG_EAX );
  1356     if( Rm != Rn ) {
  1357     	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
  1359     store_reg( REG_EAX, Rn );
  1360     sh4_x86.tstate = TSTATE_NONE;
  1361 :}
  1362 MOV.B @(R0, Rm), Rn {:  
  1363     COUNT_INST(I_MOVB);
  1364     load_reg( REG_EAX, 0 );
  1365     ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
  1366     MEM_READ_BYTE( REG_EAX, REG_EAX );
  1367     store_reg( REG_EAX, Rn );
  1368     sh4_x86.tstate = TSTATE_NONE;
  1369 :}
  1370 MOV.B @(disp, GBR), R0 {:  
  1371     COUNT_INST(I_MOVB);
  1372     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
  1373     ADDL_imms_r32( disp, REG_EAX );
  1374     MEM_READ_BYTE( REG_EAX, REG_EAX );
  1375     store_reg( REG_EAX, 0 );
  1376     sh4_x86.tstate = TSTATE_NONE;
  1377 :}
  1378 MOV.B @(disp, Rm), R0 {:  
  1379     COUNT_INST(I_MOVB);
  1380     load_reg( REG_EAX, Rm );
  1381     ADDL_imms_r32( disp, REG_EAX );
  1382     MEM_READ_BYTE( REG_EAX, REG_EAX );
  1383     store_reg( REG_EAX, 0 );
  1384     sh4_x86.tstate = TSTATE_NONE;
  1385 :}
  1386 MOV.L Rm, @Rn {:
  1387     COUNT_INST(I_MOVL);
  1388     load_reg( REG_EAX, Rn );
  1389     check_walign32(REG_EAX);
  1390     MOVL_r32_r32( REG_EAX, REG_ECX );
  1391     ANDL_imms_r32( 0xFC000000, REG_ECX );
  1392     CMPL_imms_r32( 0xE0000000, REG_ECX );
  1393     JNE_label( notsq );
  1394     ANDL_imms_r32( 0x3C, REG_EAX );
  1395     load_reg( REG_EDX, Rm );
  1396     MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
  1397     JMP_label(end);
  1398     JMP_TARGET(notsq);
  1399     load_reg( REG_EDX, Rm );
  1400     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  1401     JMP_TARGET(end);
  1402     sh4_x86.tstate = TSTATE_NONE;
  1403 :}
  1404 MOV.L Rm, @-Rn {:  
  1405     COUNT_INST(I_MOVL);
  1406     load_reg( REG_EAX, Rn );
  1407     ADDL_imms_r32( -4, REG_EAX );
  1408     check_walign32( REG_EAX );
  1409     load_reg( REG_EDX, Rm );
  1410     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  1411     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  1412     sh4_x86.tstate = TSTATE_NONE;
  1413 :}
  1414 MOV.L Rm, @(R0, Rn) {:  
  1415     COUNT_INST(I_MOVL);
  1416     load_reg( REG_EAX, 0 );
  1417     ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
  1418     check_walign32( REG_EAX );
  1419     load_reg( REG_EDX, Rm );
  1420     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  1421     sh4_x86.tstate = TSTATE_NONE;
  1422 :}
  1423 MOV.L R0, @(disp, GBR) {:  
  1424     COUNT_INST(I_MOVL);
  1425     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
  1426     ADDL_imms_r32( disp, REG_EAX );
  1427     check_walign32( REG_EAX );
  1428     load_reg( REG_EDX, 0 );
  1429     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  1430     sh4_x86.tstate = TSTATE_NONE;
  1431 :}
  1432 MOV.L Rm, @(disp, Rn) {:  
  1433     COUNT_INST(I_MOVL);
  1434     load_reg( REG_EAX, Rn );
  1435     ADDL_imms_r32( disp, REG_EAX );
  1436     check_walign32( REG_EAX );
  1437     MOVL_r32_r32( REG_EAX, REG_ECX );
  1438     ANDL_imms_r32( 0xFC000000, REG_ECX );
  1439     CMPL_imms_r32( 0xE0000000, REG_ECX );
  1440     JNE_label( notsq );
  1441     ANDL_imms_r32( 0x3C, REG_EAX );
  1442     load_reg( REG_EDX, Rm );
  1443     MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
  1444     JMP_label(end);
  1445     JMP_TARGET(notsq);
  1446     load_reg( REG_EDX, Rm );
  1447     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  1448     JMP_TARGET(end);
  1449     sh4_x86.tstate = TSTATE_NONE;
  1450 :}
  1451 MOV.L @Rm, Rn {:  
  1452     COUNT_INST(I_MOVL);
  1453     load_reg( REG_EAX, Rm );
  1454     check_ralign32( REG_EAX );
  1455     MEM_READ_LONG( REG_EAX, REG_EAX );
  1456     store_reg( REG_EAX, Rn );
  1457     sh4_x86.tstate = TSTATE_NONE;
  1458 :}
  1459 MOV.L @Rm+, Rn {:  
  1460     COUNT_INST(I_MOVL);
  1461     load_reg( REG_EAX, Rm );
  1462     check_ralign32( REG_EAX );
  1463     MEM_READ_LONG( REG_EAX, REG_EAX );
  1464     if( Rm != Rn ) {
  1465     	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  1467     store_reg( REG_EAX, Rn );
  1468     sh4_x86.tstate = TSTATE_NONE;
  1469 :}
  1470 MOV.L @(R0, Rm), Rn {:  
  1471     COUNT_INST(I_MOVL);
  1472     load_reg( REG_EAX, 0 );
  1473     ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
  1474     check_ralign32( REG_EAX );
  1475     MEM_READ_LONG( REG_EAX, REG_EAX );
  1476     store_reg( REG_EAX, Rn );
  1477     sh4_x86.tstate = TSTATE_NONE;
  1478 :}
  1479 MOV.L @(disp, GBR), R0 {:
  1480     COUNT_INST(I_MOVL);
  1481     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
  1482     ADDL_imms_r32( disp, REG_EAX );
  1483     check_ralign32( REG_EAX );
  1484     MEM_READ_LONG( REG_EAX, REG_EAX );
  1485     store_reg( REG_EAX, 0 );
  1486     sh4_x86.tstate = TSTATE_NONE;
  1487 :}
  1488 MOV.L @(disp, PC), Rn {:  
  1489     COUNT_INST(I_MOVLPC);
  1490     if( sh4_x86.in_delay_slot ) {
  1491 	SLOTILLEGAL();
  1492     } else {
  1493 	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
  1494 	if( IS_IN_ICACHE(target) ) {
  1495 	    // If the target address is in the same page as the code, it's
  1496 	    // pretty safe to just ref it directly and circumvent the whole
  1497 	    // memory subsystem. (this is a big performance win)
  1499 	    // FIXME: There's a corner-case that's not handled here when
  1500 	    // the current code-page is in the ITLB but not in the UTLB.
  1501 	    // (should generate a TLB miss although need to test SH4 
  1502 	    // behaviour to confirm) Unlikely to be anyone depending on this
  1503 	    // behaviour though.
  1504 	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
  1505 	    MOVL_moffptr_eax( ptr );
  1506 	} else {
  1507 	    // Note: we use sh4r.pc for the calc as we could be running at a
  1508 	    // different virtual address than the translation was done with,
  1509 	    // but we can safely assume that the low bits are the same.
  1510 	    MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX );
  1511 	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
  1512 	    MEM_READ_LONG( REG_EAX, REG_EAX );
  1513 	    sh4_x86.tstate = TSTATE_NONE;
  1515 	store_reg( REG_EAX, Rn );
  1517 :}
  1518 MOV.L @(disp, Rm), Rn {:  
  1519     COUNT_INST(I_MOVL);
  1520     load_reg( REG_EAX, Rm );
  1521     ADDL_imms_r32( disp, REG_EAX );
  1522     check_ralign32( REG_EAX );
  1523     MEM_READ_LONG( REG_EAX, REG_EAX );
  1524     store_reg( REG_EAX, Rn );
  1525     sh4_x86.tstate = TSTATE_NONE;
  1526 :}
  1527 MOV.W Rm, @Rn {:  
  1528     COUNT_INST(I_MOVW);
  1529     load_reg( REG_EAX, Rn );
  1530     check_walign16( REG_EAX );
  1531     load_reg( REG_EDX, Rm );
  1532     MEM_WRITE_WORD( REG_EAX, REG_EDX );
  1533     sh4_x86.tstate = TSTATE_NONE;
  1534 :}
  1535 MOV.W Rm, @-Rn {:  
  1536     COUNT_INST(I_MOVW);
  1537     load_reg( REG_EAX, Rn );
  1538     check_walign16( REG_EAX );
  1539     LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
  1540     load_reg( REG_EDX, Rm );
  1541     MEM_WRITE_WORD( REG_EAX, REG_EDX );
  1542     ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
  1543     sh4_x86.tstate = TSTATE_NONE;
  1544 :}
  1545 MOV.W Rm, @(R0, Rn) {:  
  1546     COUNT_INST(I_MOVW);
  1547     load_reg( REG_EAX, 0 );
  1548     ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
  1549     check_walign16( REG_EAX );
  1550     load_reg( REG_EDX, Rm );
  1551     MEM_WRITE_WORD( REG_EAX, REG_EDX );
  1552     sh4_x86.tstate = TSTATE_NONE;
  1553 :}
  1554 MOV.W R0, @(disp, GBR) {:  
  1555     COUNT_INST(I_MOVW);
  1556     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
  1557     ADDL_imms_r32( disp, REG_EAX );
  1558     check_walign16( REG_EAX );
  1559     load_reg( REG_EDX, 0 );
  1560     MEM_WRITE_WORD( REG_EAX, REG_EDX );
  1561     sh4_x86.tstate = TSTATE_NONE;
  1562 :}
  1563 MOV.W R0, @(disp, Rn) {:  
  1564     COUNT_INST(I_MOVW);
  1565     load_reg( REG_EAX, Rn );
  1566     ADDL_imms_r32( disp, REG_EAX );
  1567     check_walign16( REG_EAX );
  1568     load_reg( REG_EDX, 0 );
  1569     MEM_WRITE_WORD( REG_EAX, REG_EDX );
  1570     sh4_x86.tstate = TSTATE_NONE;
  1571 :}
  1572 MOV.W @Rm, Rn {:  
  1573     COUNT_INST(I_MOVW);
  1574     load_reg( REG_EAX, Rm );
  1575     check_ralign16( REG_EAX );
  1576     MEM_READ_WORD( REG_EAX, REG_EAX );
  1577     store_reg( REG_EAX, Rn );
  1578     sh4_x86.tstate = TSTATE_NONE;
  1579 :}
  1580 MOV.W @Rm+, Rn {:  
  1581     COUNT_INST(I_MOVW);
  1582     load_reg( REG_EAX, Rm );
  1583     check_ralign16( REG_EAX );
  1584     MEM_READ_WORD( REG_EAX, REG_EAX );
  1585     if( Rm != Rn ) {
  1586         ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
  1588     store_reg( REG_EAX, Rn );
  1589     sh4_x86.tstate = TSTATE_NONE;
  1590 :}
  1591 MOV.W @(R0, Rm), Rn {:  
  1592     COUNT_INST(I_MOVW);
  1593     load_reg( REG_EAX, 0 );
  1594     ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
  1595     check_ralign16( REG_EAX );
  1596     MEM_READ_WORD( REG_EAX, REG_EAX );
  1597     store_reg( REG_EAX, Rn );
  1598     sh4_x86.tstate = TSTATE_NONE;
  1599 :}
  1600 MOV.W @(disp, GBR), R0 {:  
  1601     COUNT_INST(I_MOVW);
  1602     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
  1603     ADDL_imms_r32( disp, REG_EAX );
  1604     check_ralign16( REG_EAX );
  1605     MEM_READ_WORD( REG_EAX, REG_EAX );
  1606     store_reg( REG_EAX, 0 );
  1607     sh4_x86.tstate = TSTATE_NONE;
  1608 :}
  1609 MOV.W @(disp, PC), Rn {:  
  1610     COUNT_INST(I_MOVW);
  1611     if( sh4_x86.in_delay_slot ) {
  1612 	SLOTILLEGAL();
  1613     } else {
  1614 	// See comments for MOV.L @(disp, PC), Rn
  1615 	uint32_t target = pc + disp + 4;
  1616 	if( IS_IN_ICACHE(target) ) {
  1617 	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
  1618 	    MOVL_moffptr_eax( ptr );
  1619 	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
  1620 	} else {
  1621 	    MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX );
  1622 	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
  1623 	    MEM_READ_WORD( REG_EAX, REG_EAX );
  1624 	    sh4_x86.tstate = TSTATE_NONE;
  1626 	store_reg( REG_EAX, Rn );
  1628 :}
  1629 MOV.W @(disp, Rm), R0 {:  
  1630     COUNT_INST(I_MOVW);
  1631     load_reg( REG_EAX, Rm );
  1632     ADDL_imms_r32( disp, REG_EAX );
  1633     check_ralign16( REG_EAX );
  1634     MEM_READ_WORD( REG_EAX, REG_EAX );
  1635     store_reg( REG_EAX, 0 );
  1636     sh4_x86.tstate = TSTATE_NONE;
  1637 :}
  1638 MOVA @(disp, PC), R0 {:  
  1639     COUNT_INST(I_MOVA);
  1640     if( sh4_x86.in_delay_slot ) {
  1641 	SLOTILLEGAL();
  1642     } else {
  1643 	MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX );
  1644 	ADDL_rbpdisp_r32( R_PC, REG_ECX );
  1645 	store_reg( REG_ECX, 0 );
  1646 	sh4_x86.tstate = TSTATE_NONE;
  1648 :}
  1649 MOVCA.L R0, @Rn {:  
  1650     COUNT_INST(I_MOVCA);
  1651     load_reg( REG_EAX, Rn );
  1652     check_walign32( REG_EAX );
  1653     load_reg( REG_EDX, 0 );
  1654     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  1655     sh4_x86.tstate = TSTATE_NONE;
  1656 :}
  1658 /* Control transfer instructions */
  1659 BF disp {:
  1660     COUNT_INST(I_BF);
  1661     if( sh4_x86.in_delay_slot ) {
  1662 	SLOTILLEGAL();
  1663     } else {
  1664 	sh4vma_t target = disp + pc + 4;
  1665 	JT_label( nottaken );
  1666 	exit_block_rel(target, pc+2 );
  1667 	JMP_TARGET(nottaken);
  1668 	return 2;
  1670 :}
  1671 BF/S disp {:
  1672     COUNT_INST(I_BFS);
  1673     if( sh4_x86.in_delay_slot ) {
  1674 	SLOTILLEGAL();
  1675     } else {
  1676 	sh4_x86.in_delay_slot = DELAY_PC;
  1677 	if( UNTRANSLATABLE(pc+2) ) {
  1678 	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
  1679 	    JT_label(nottaken);
  1680 	    ADDL_imms_r32( disp, REG_EAX );
  1681 	    JMP_TARGET(nottaken);
  1682 	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
  1683 	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
  1684 	    exit_block_emu(pc+2);
  1685 	    sh4_x86.branch_taken = TRUE;
  1686 	    return 2;
  1687 	} else {
  1688 	    if( sh4_x86.tstate == TSTATE_NONE ) {
  1689 		CMPL_imms_rbpdisp( 1, R_T );
  1690 		sh4_x86.tstate = TSTATE_E;
  1692 	    sh4vma_t target = disp + pc + 4;
  1693 	    JCC_cc_rel32(sh4_x86.tstate,0);
  1694 	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
  1695 	    int save_tstate = sh4_x86.tstate;
  1696 	    sh4_translate_instruction(pc+2);
  1697 	    exit_block_rel( target, pc+4 );
  1699 	    // not taken
  1700 	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
  1701 	    sh4_x86.tstate = save_tstate;
  1702 	    sh4_translate_instruction(pc+2);
  1703 	    return 4;
  1706 :}
  1707 BRA disp {:  
  1708     COUNT_INST(I_BRA);
  1709     if( sh4_x86.in_delay_slot ) {
  1710 	SLOTILLEGAL();
  1711     } else {
  1712 	sh4_x86.in_delay_slot = DELAY_PC;
  1713 	sh4_x86.branch_taken = TRUE;
  1714 	if( UNTRANSLATABLE(pc+2) ) {
  1715 	    MOVL_rbpdisp_r32( R_PC, REG_EAX );
  1716 	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
  1717 	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
  1718 	    exit_block_emu(pc+2);
  1719 	    return 2;
  1720 	} else {
  1721 	    sh4_translate_instruction( pc + 2 );
  1722 	    exit_block_rel( disp + pc + 4, pc+4 );
  1723 	    return 4;
  1726 :}
  1727 BRAF Rn {:  
  1728     COUNT_INST(I_BRAF);
  1729     if( sh4_x86.in_delay_slot ) {
  1730 	SLOTILLEGAL();
  1731     } else {
  1732 	MOVL_rbpdisp_r32( R_PC, REG_EAX );
  1733 	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
  1734 	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
  1735 	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
  1736 	sh4_x86.in_delay_slot = DELAY_PC;
  1737 	sh4_x86.tstate = TSTATE_NONE;
  1738 	sh4_x86.branch_taken = TRUE;
  1739 	if( UNTRANSLATABLE(pc+2) ) {
  1740 	    exit_block_emu(pc+2);
  1741 	    return 2;
  1742 	} else {
  1743 	    sh4_translate_instruction( pc + 2 );
  1744 	    exit_block_newpcset(pc+4);
  1745 	    return 4;
  1748 :}
  1749 BSR disp {:  
  1750     COUNT_INST(I_BSR);
  1751     if( sh4_x86.in_delay_slot ) {
  1752 	SLOTILLEGAL();
  1753     } else {
  1754 	MOVL_rbpdisp_r32( R_PC, REG_EAX );
  1755 	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
  1756 	MOVL_r32_rbpdisp( REG_EAX, R_PR );
  1757 	sh4_x86.in_delay_slot = DELAY_PC;
  1758 	sh4_x86.branch_taken = TRUE;
  1759 	sh4_x86.tstate = TSTATE_NONE;
  1760 	if( UNTRANSLATABLE(pc+2) ) {
  1761 	    ADDL_imms_r32( disp, REG_EAX );
  1762 	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
  1763 	    exit_block_emu(pc+2);
  1764 	    return 2;
  1765 	} else {
  1766 	    sh4_translate_instruction( pc + 2 );
  1767 	    exit_block_rel( disp + pc + 4, pc+4 );
  1768 	    return 4;
  1771 :}
  1772 BSRF Rn {:  
  1773     COUNT_INST(I_BSRF);
  1774     if( sh4_x86.in_delay_slot ) {
  1775 	SLOTILLEGAL();
  1776     } else {
  1777 	MOVL_rbpdisp_r32( R_PC, REG_EAX );
  1778 	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
  1779 	MOVL_r32_rbpdisp( REG_EAX, R_PR );
  1780 	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
  1781 	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
  1783 	sh4_x86.in_delay_slot = DELAY_PC;
  1784 	sh4_x86.tstate = TSTATE_NONE;
  1785 	sh4_x86.branch_taken = TRUE;
  1786 	if( UNTRANSLATABLE(pc+2) ) {
  1787 	    exit_block_emu(pc+2);
  1788 	    return 2;
  1789 	} else {
  1790 	    sh4_translate_instruction( pc + 2 );
  1791 	    exit_block_newpcset(pc+4);
  1792 	    return 4;
  1795 :}
  1796 BT disp {:
  1797     COUNT_INST(I_BT);
  1798     if( sh4_x86.in_delay_slot ) {
  1799 	SLOTILLEGAL();
  1800     } else {
  1801 	sh4vma_t target = disp + pc + 4;
  1802 	JF_label( nottaken );
  1803 	exit_block_rel(target, pc+2 );
  1804 	JMP_TARGET(nottaken);
  1805 	return 2;
  1807 :}
  1808 BT/S disp {:
  1809     COUNT_INST(I_BTS);
  1810     if( sh4_x86.in_delay_slot ) {
  1811 	SLOTILLEGAL();
  1812     } else {
  1813 	sh4_x86.in_delay_slot = DELAY_PC;
  1814 	if( UNTRANSLATABLE(pc+2) ) {
  1815 	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
  1816 	    JF_label(nottaken);
  1817 	    ADDL_imms_r32( disp, REG_EAX );
  1818 	    JMP_TARGET(nottaken);
  1819 	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
  1820 	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
  1821 	    exit_block_emu(pc+2);
  1822 	    sh4_x86.branch_taken = TRUE;
  1823 	    return 2;
  1824 	} else {
  1825 	    if( sh4_x86.tstate == TSTATE_NONE ) {
  1826 		CMPL_imms_rbpdisp( 1, R_T );
  1827 		sh4_x86.tstate = TSTATE_E;
  1829 	    JCC_cc_rel32(sh4_x86.tstate^1,0);
  1830 	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
  1832 	    int save_tstate = sh4_x86.tstate;
  1833 	    sh4_translate_instruction(pc+2);
  1834 	    exit_block_rel( disp + pc + 4, pc+4 );
  1835 	    // not taken
  1836 	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
  1837 	    sh4_x86.tstate = save_tstate;
  1838 	    sh4_translate_instruction(pc+2);
  1839 	    return 4;
  1842 :}
  1843 JMP @Rn {:  
  1844     COUNT_INST(I_JMP);
  1845     if( sh4_x86.in_delay_slot ) {
  1846 	SLOTILLEGAL();
  1847     } else {
  1848 	load_reg( REG_ECX, Rn );
  1849 	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
  1850 	sh4_x86.in_delay_slot = DELAY_PC;
  1851 	sh4_x86.branch_taken = TRUE;
  1852 	if( UNTRANSLATABLE(pc+2) ) {
  1853 	    exit_block_emu(pc+2);
  1854 	    return 2;
  1855 	} else {
  1856 	    sh4_translate_instruction(pc+2);
  1857 	    exit_block_newpcset(pc+4);
  1858 	    return 4;
  1861 :}
  1862 JSR @Rn {:  
  1863     COUNT_INST(I_JSR);
  1864     if( sh4_x86.in_delay_slot ) {
  1865 	SLOTILLEGAL();
  1866     } else {
  1867 	MOVL_rbpdisp_r32( R_PC, REG_EAX );
  1868 	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
  1869 	MOVL_r32_rbpdisp( REG_EAX, R_PR );
  1870 	load_reg( REG_ECX, Rn );
  1871 	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
  1872 	sh4_x86.in_delay_slot = DELAY_PC;
  1873 	sh4_x86.branch_taken = TRUE;
  1874 	sh4_x86.tstate = TSTATE_NONE;
  1875 	if( UNTRANSLATABLE(pc+2) ) {
  1876 	    exit_block_emu(pc+2);
  1877 	    return 2;
  1878 	} else {
  1879 	    sh4_translate_instruction(pc+2);
  1880 	    exit_block_newpcset(pc+4);
  1881 	    return 4;
  1884 :}
  1885 RTE {:  
  1886     COUNT_INST(I_RTE);
  1887     if( sh4_x86.in_delay_slot ) {
  1888 	SLOTILLEGAL();
  1889     } else {
  1890 	check_priv();
  1891 	MOVL_rbpdisp_r32( R_SPC, REG_ECX );
  1892 	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
  1893 	MOVL_rbpdisp_r32( R_SSR, REG_EAX );
  1894 	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
  1895 	sh4_x86.in_delay_slot = DELAY_PC;
  1896 	sh4_x86.fpuen_checked = FALSE;
  1897 	sh4_x86.tstate = TSTATE_NONE;
  1898 	sh4_x86.branch_taken = TRUE;
  1899 	if( UNTRANSLATABLE(pc+2) ) {
  1900 	    exit_block_emu(pc+2);
  1901 	    return 2;
  1902 	} else {
  1903 	    sh4_translate_instruction(pc+2);
  1904 	    exit_block_newpcset(pc+4);
  1905 	    return 4;
  1908 :}
  1909 RTS {:  
  1910     COUNT_INST(I_RTS);
  1911     if( sh4_x86.in_delay_slot ) {
  1912 	SLOTILLEGAL();
  1913     } else {
  1914 	MOVL_rbpdisp_r32( R_PR, REG_ECX );
  1915 	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
  1916 	sh4_x86.in_delay_slot = DELAY_PC;
  1917 	sh4_x86.branch_taken = TRUE;
  1918 	if( UNTRANSLATABLE(pc+2) ) {
  1919 	    exit_block_emu(pc+2);
  1920 	    return 2;
  1921 	} else {
  1922 	    sh4_translate_instruction(pc+2);
  1923 	    exit_block_newpcset(pc+4);
  1924 	    return 4;
  1927 :}
  1928 TRAPA #imm {:  
  1929     COUNT_INST(I_TRAPA);
  1930     if( sh4_x86.in_delay_slot ) {
  1931 	SLOTILLEGAL();
  1932     } else {
  1933 	MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX );   // 5
  1934 	ADDL_r32_rbpdisp( REG_ECX, R_PC );
  1935 	MOVL_imm32_r32( imm, REG_EAX );
  1936 	CALL1_ptr_r32( sh4_raise_trap, REG_EAX );
  1937 	sh4_x86.tstate = TSTATE_NONE;
  1938 	exit_block_pcset(pc+2);
  1939 	sh4_x86.branch_taken = TRUE;
  1940 	return 2;
  1942 :}
  1943 UNDEF {:  
  1944     COUNT_INST(I_UNDEF);
  1945     if( sh4_x86.in_delay_slot ) {
  1946 	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2);    
  1947     } else {
  1948 	exit_block_exc(EXC_ILLEGAL, pc);    
  1949 	return 2;
  1951 :}
  1953 CLRMAC {:  
  1954     COUNT_INST(I_CLRMAC);
  1955     XORL_r32_r32(REG_EAX, REG_EAX);
  1956     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
  1957     MOVL_r32_rbpdisp( REG_EAX, R_MACH );
  1958     sh4_x86.tstate = TSTATE_NONE;
  1959 :}
  1960 CLRS {:
  1961     COUNT_INST(I_CLRS);
  1962     CLC();
  1963     SETCCB_cc_rbpdisp(X86_COND_C, R_S);
  1964     sh4_x86.tstate = TSTATE_NONE;
  1965 :}
  1966 CLRT {:  
  1967     COUNT_INST(I_CLRT);
  1968     CLC();
  1969     SETC_t();
  1970     sh4_x86.tstate = TSTATE_C;
  1971 :}
  1972 SETS {:  
  1973     COUNT_INST(I_SETS);
  1974     STC();
  1975     SETCCB_cc_rbpdisp(X86_COND_C, R_S);
  1976     sh4_x86.tstate = TSTATE_NONE;
  1977 :}
  1978 SETT {:  
  1979     COUNT_INST(I_SETT);
  1980     STC();
  1981     SETC_t();
  1982     sh4_x86.tstate = TSTATE_C;
  1983 :}
  1985 /* Floating point moves */
  1986 FMOV FRm, FRn {:  
  1987     COUNT_INST(I_FMOV1);
  1988     check_fpuen();
  1989     if( sh4_x86.double_size ) {
  1990         load_dr0( REG_EAX, FRm );
  1991         load_dr1( REG_ECX, FRm );
  1992         store_dr0( REG_EAX, FRn );
  1993         store_dr1( REG_ECX, FRn );
  1994     } else {
  1995         load_fr( REG_EAX, FRm ); // SZ=0 branch
  1996         store_fr( REG_EAX, FRn );
  1998 :}
  1999 FMOV FRm, @Rn {: 
  2000     COUNT_INST(I_FMOV2);
  2001     check_fpuen();
  2002     load_reg( REG_EAX, Rn );
  2003     if( sh4_x86.double_size ) {
  2004         check_walign64( REG_EAX );
  2005         load_dr0( REG_EDX, FRm );
  2006         MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2007         load_reg( REG_EAX, Rn );
  2008         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
  2009         load_dr1( REG_EDX, FRm );
  2010         MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2011     } else {
  2012         check_walign32( REG_EAX );
  2013         load_fr( REG_EDX, FRm );
  2014         MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2016     sh4_x86.tstate = TSTATE_NONE;
  2017 :}
  2018 FMOV @Rm, FRn {:  
  2019     COUNT_INST(I_FMOV5);
  2020     check_fpuen();
  2021     load_reg( REG_EAX, Rm );
  2022     if( sh4_x86.double_size ) {
  2023         check_ralign64( REG_EAX );
  2024         MEM_READ_LONG( REG_EAX, REG_EAX );
  2025         store_dr0( REG_EAX, FRn );
  2026         load_reg( REG_EAX, Rm );
  2027         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
  2028         MEM_READ_LONG( REG_EAX, REG_EAX );
  2029         store_dr1( REG_EAX, FRn );
  2030     } else {
  2031         check_ralign32( REG_EAX );
  2032         MEM_READ_LONG( REG_EAX, REG_EAX );
  2033         store_fr( REG_EAX, FRn );
  2035     sh4_x86.tstate = TSTATE_NONE;
  2036 :}
  2037 FMOV FRm, @-Rn {:  
  2038     COUNT_INST(I_FMOV3);
  2039     check_fpuen();
  2040     load_reg( REG_EAX, Rn );
  2041     if( sh4_x86.double_size ) {
  2042         check_walign64( REG_EAX );
  2043         LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
  2044         load_dr0( REG_EDX, FRm );
  2045         MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2046         load_reg( REG_EAX, Rn );
  2047         LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
  2048         load_dr1( REG_EDX, FRm );
  2049         MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2050         ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
  2051     } else {
  2052         check_walign32( REG_EAX );
  2053         LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
  2054         load_fr( REG_EDX, FRm );
  2055         MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2056         ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
  2058     sh4_x86.tstate = TSTATE_NONE;
  2059 :}
  2060 FMOV @Rm+, FRn {:
  2061     COUNT_INST(I_FMOV6);
  2062     check_fpuen();
  2063     load_reg( REG_EAX, Rm );
  2064     if( sh4_x86.double_size ) {
  2065         check_ralign64( REG_EAX );
  2066         MEM_READ_LONG( REG_EAX, REG_EAX );
  2067         store_dr0( REG_EAX, FRn );
  2068         load_reg( REG_EAX, Rm );
  2069         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
  2070         MEM_READ_LONG( REG_EAX, REG_EAX );
  2071         store_dr1( REG_EAX, FRn );
  2072         ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
  2073     } else {
  2074         check_ralign32( REG_EAX );
  2075         MEM_READ_LONG( REG_EAX, REG_EAX );
  2076         store_fr( REG_EAX, FRn );
  2077         ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2079     sh4_x86.tstate = TSTATE_NONE;
  2080 :}
  2081 FMOV FRm, @(R0, Rn) {:  
  2082     COUNT_INST(I_FMOV4);
  2083     check_fpuen();
  2084     load_reg( REG_EAX, Rn );
  2085     ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
  2086     if( sh4_x86.double_size ) {
  2087         check_walign64( REG_EAX );
  2088         load_dr0( REG_EDX, FRm );
  2089         MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2090         load_reg( REG_EAX, Rn );
  2091         ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
  2092         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
  2093         load_dr1( REG_EDX, FRm );
  2094         MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2095     } else {
  2096         check_walign32( REG_EAX );
  2097         load_fr( REG_EDX, FRm );
  2098         MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
  2100     sh4_x86.tstate = TSTATE_NONE;
  2101 :}
  2102 FMOV @(R0, Rm), FRn {:  
  2103     COUNT_INST(I_FMOV7);
  2104     check_fpuen();
  2105     load_reg( REG_EAX, Rm );
  2106     ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
  2107     if( sh4_x86.double_size ) {
  2108         check_ralign64( REG_EAX );
  2109         MEM_READ_LONG( REG_EAX, REG_EAX );
  2110         store_dr0( REG_EAX, FRn );
  2111         load_reg( REG_EAX, Rm );
  2112         ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
  2113         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
  2114         MEM_READ_LONG( REG_EAX, REG_EAX );
  2115         store_dr1( REG_EAX, FRn );
  2116     } else {
  2117         check_ralign32( REG_EAX );
  2118         MEM_READ_LONG( REG_EAX, REG_EAX );
  2119         store_fr( REG_EAX, FRn );
  2121     sh4_x86.tstate = TSTATE_NONE;
  2122 :}
  2123 FLDI0 FRn {:  /* IFF PR=0 */
  2124     COUNT_INST(I_FLDI0);
  2125     check_fpuen();
  2126     if( sh4_x86.double_prec == 0 ) {
  2127         XORL_r32_r32( REG_EAX, REG_EAX );
  2128         store_fr( REG_EAX, FRn );
  2130     sh4_x86.tstate = TSTATE_NONE;
  2131 :}
  2132 FLDI1 FRn {:  /* IFF PR=0 */
  2133     COUNT_INST(I_FLDI1);
  2134     check_fpuen();
  2135     if( sh4_x86.double_prec == 0 ) {
  2136         MOVL_imm32_r32( 0x3F800000, REG_EAX );
  2137         store_fr( REG_EAX, FRn );
  2139 :}
  2141 FLOAT FPUL, FRn {:  
  2142     COUNT_INST(I_FLOAT);
  2143     check_fpuen();
  2144     FILD_rbpdisp(R_FPUL);
  2145     if( sh4_x86.double_prec ) {
  2146         pop_dr( FRn );
  2147     } else {
  2148         pop_fr( FRn );
  2150 :}
  2151 FTRC FRm, FPUL {:  
  2152     COUNT_INST(I_FTRC);
  2153     check_fpuen();
  2154     if( sh4_x86.double_prec ) {
  2155         push_dr( FRm );
  2156     } else {
  2157         push_fr( FRm );
  2159     MOVP_immptr_rptr( &max_int, REG_ECX );
  2160     FILD_r32disp( REG_ECX, 0 );
  2161     FCOMIP_st(1);
  2162     JNA_label( sat );
  2163     MOVP_immptr_rptr( &min_int, REG_ECX );
  2164     FILD_r32disp( REG_ECX, 0 );
  2165     FCOMIP_st(1);              
  2166     JAE_label( sat2 );            
  2167     MOVP_immptr_rptr( &save_fcw, REG_EAX );
  2168     FNSTCW_r32disp( REG_EAX, 0 );
  2169     MOVP_immptr_rptr( &trunc_fcw, REG_EDX );
  2170     FLDCW_r32disp( REG_EDX, 0 );
  2171     FISTP_rbpdisp(R_FPUL);             
  2172     FLDCW_r32disp( REG_EAX, 0 );
  2173     JMP_label(end);             
  2175     JMP_TARGET(sat);
  2176     JMP_TARGET(sat2);
  2177     MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
  2178     MOVL_r32_rbpdisp( REG_ECX, R_FPUL );
  2179     FPOP_st();
  2180     JMP_TARGET(end);
  2181     sh4_x86.tstate = TSTATE_NONE;
  2182 :}
  2183 FLDS FRm, FPUL {:  
  2184     COUNT_INST(I_FLDS);
  2185     check_fpuen();
  2186     load_fr( REG_EAX, FRm );
  2187     MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
  2188 :}
  2189 FSTS FPUL, FRn {:  
  2190     COUNT_INST(I_FSTS);
  2191     check_fpuen();
  2192     MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
  2193     store_fr( REG_EAX, FRn );
  2194 :}
  2195 FCNVDS FRm, FPUL {:  
  2196     COUNT_INST(I_FCNVDS);
  2197     check_fpuen();
  2198     if( sh4_x86.double_prec ) {
  2199         push_dr( FRm );
  2200         pop_fpul();
  2202 :}
  2203 FCNVSD FPUL, FRn {:  
  2204     COUNT_INST(I_FCNVSD);
  2205     check_fpuen();
  2206     if( sh4_x86.double_prec ) {
  2207         push_fpul();
  2208         pop_dr( FRn );
  2210 :}
  2212 /* Floating point instructions */
  2213 FABS FRn {:  
  2214     COUNT_INST(I_FABS);
  2215     check_fpuen();
  2216     if( sh4_x86.double_prec ) {
  2217         push_dr(FRn);
  2218         FABS_st0();
  2219         pop_dr(FRn);
  2220     } else {
  2221         push_fr(FRn);
  2222         FABS_st0();
  2223         pop_fr(FRn);
  2225 :}
  2226 FADD FRm, FRn {:  
  2227     COUNT_INST(I_FADD);
  2228     check_fpuen();
  2229     if( sh4_x86.double_prec ) {
  2230         push_dr(FRm);
  2231         push_dr(FRn);
  2232         FADDP_st(1);
  2233         pop_dr(FRn);
  2234     } else {
  2235         push_fr(FRm);
  2236         push_fr(FRn);
  2237         FADDP_st(1);
  2238         pop_fr(FRn);
  2240 :}
  2241 FDIV FRm, FRn {:  
  2242     COUNT_INST(I_FDIV);
  2243     check_fpuen();
  2244     if( sh4_x86.double_prec ) {
  2245         push_dr(FRn);
  2246         push_dr(FRm);
  2247         FDIVP_st(1);
  2248         pop_dr(FRn);
  2249     } else {
  2250         push_fr(FRn);
  2251         push_fr(FRm);
  2252         FDIVP_st(1);
  2253         pop_fr(FRn);
  2255 :}
  2256 FMAC FR0, FRm, FRn {:  
  2257     COUNT_INST(I_FMAC);
  2258     check_fpuen();
  2259     if( sh4_x86.double_prec ) {
  2260         push_dr( 0 );
  2261         push_dr( FRm );
  2262         FMULP_st(1);
  2263         push_dr( FRn );
  2264         FADDP_st(1);
  2265         pop_dr( FRn );
  2266     } else {
  2267         push_fr( 0 );
  2268         push_fr( FRm );
  2269         FMULP_st(1);
  2270         push_fr( FRn );
  2271         FADDP_st(1);
  2272         pop_fr( FRn );
  2274 :}
  2276 FMUL FRm, FRn {:  
  2277     COUNT_INST(I_FMUL);
  2278     check_fpuen();
  2279     if( sh4_x86.double_prec ) {
  2280         push_dr(FRm);
  2281         push_dr(FRn);
  2282         FMULP_st(1);
  2283         pop_dr(FRn);
  2284     } else {
  2285         push_fr(FRm);
  2286         push_fr(FRn);
  2287         FMULP_st(1);
  2288         pop_fr(FRn);
  2290 :}
  2291 FNEG FRn {:  
  2292     COUNT_INST(I_FNEG);
  2293     check_fpuen();
  2294     if( sh4_x86.double_prec ) {
  2295         push_dr(FRn);
  2296         FCHS_st0();
  2297         pop_dr(FRn);
  2298     } else {
  2299         push_fr(FRn);
  2300         FCHS_st0();
  2301         pop_fr(FRn);
  2303 :}
  2304 FSRRA FRn {:  
  2305     COUNT_INST(I_FSRRA);
  2306     check_fpuen();
  2307     if( sh4_x86.double_prec == 0 ) {
  2308         FLD1_st0();
  2309         push_fr(FRn);
  2310         FSQRT_st0();
  2311         FDIVP_st(1);
  2312         pop_fr(FRn);
  2314 :}
  2315 FSQRT FRn {:  
  2316     COUNT_INST(I_FSQRT);
  2317     check_fpuen();
  2318     if( sh4_x86.double_prec ) {
  2319         push_dr(FRn);
  2320         FSQRT_st0();
  2321         pop_dr(FRn);
  2322     } else {
  2323         push_fr(FRn);
  2324         FSQRT_st0();
  2325         pop_fr(FRn);
  2327 :}
  2328 FSUB FRm, FRn {:  
  2329     COUNT_INST(I_FSUB);
  2330     check_fpuen();
  2331     if( sh4_x86.double_prec ) {
  2332         push_dr(FRn);
  2333         push_dr(FRm);
  2334         FSUBP_st(1);
  2335         pop_dr(FRn);
  2336     } else {
  2337         push_fr(FRn);
  2338         push_fr(FRm);
  2339         FSUBP_st(1);
  2340         pop_fr(FRn);
  2342 :}
  2344 FCMP/EQ FRm, FRn {:  
  2345     COUNT_INST(I_FCMPEQ);
  2346     check_fpuen();
  2347     if( sh4_x86.double_prec ) {
  2348         push_dr(FRm);
  2349         push_dr(FRn);
  2350     } else {
  2351         push_fr(FRm);
  2352         push_fr(FRn);
  2354     FCOMIP_st(1);
  2355     SETE_t();
  2356     FPOP_st();
  2357     sh4_x86.tstate = TSTATE_E;
  2358 :}
  2359 FCMP/GT FRm, FRn {:  
  2360     COUNT_INST(I_FCMPGT);
  2361     check_fpuen();
  2362     if( sh4_x86.double_prec ) {
  2363         push_dr(FRm);
  2364         push_dr(FRn);
  2365     } else {
  2366         push_fr(FRm);
  2367         push_fr(FRn);
  2369     FCOMIP_st(1);
  2370     SETA_t();
  2371     FPOP_st();
  2372     sh4_x86.tstate = TSTATE_A;
  2373 :}
  2375 FSCA FPUL, FRn {:  
  2376     COUNT_INST(I_FSCA);
  2377     check_fpuen();
  2378     if( sh4_x86.double_prec == 0 ) {
  2379         LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
  2380         MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
  2381         CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX );
  2383     sh4_x86.tstate = TSTATE_NONE;
  2384 :}
  2385 FIPR FVm, FVn {:  
  2386     COUNT_INST(I_FIPR);
  2387     check_fpuen();
  2388     if( sh4_x86.double_prec == 0 ) {
  2389         if( sh4_x86.sse3_enabled ) {
  2390             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
  2391             MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
  2392             HADDPS_xmm_xmm( 4, 4 ); 
  2393             HADDPS_xmm_xmm( 4, 4 );
  2394             MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
  2395         } else {
  2396             push_fr( FVm<<2 );
  2397             push_fr( FVn<<2 );
  2398             FMULP_st(1);
  2399             push_fr( (FVm<<2)+1);
  2400             push_fr( (FVn<<2)+1);
  2401             FMULP_st(1);
  2402             FADDP_st(1);
  2403             push_fr( (FVm<<2)+2);
  2404             push_fr( (FVn<<2)+2);
  2405             FMULP_st(1);
  2406             FADDP_st(1);
  2407             push_fr( (FVm<<2)+3);
  2408             push_fr( (FVn<<2)+3);
  2409             FMULP_st(1);
  2410             FADDP_st(1);
  2411             pop_fr( (FVn<<2)+3);
  2414 :}
  2415 FTRV XMTRX, FVn {:  
  2416     COUNT_INST(I_FTRV);
  2417     check_fpuen();
  2418     if( sh4_x86.double_prec == 0 ) {
  2419         if( sh4_x86.sse3_enabled ) {
  2420             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
  2421             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
  2422             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
  2423             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
  2425             MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
  2426             MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
  2427             MOV_xmm_xmm( 4, 6 );
  2428             MOV_xmm_xmm( 5, 7 );
  2429             MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
  2430             MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
  2431             MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
  2432             MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
  2433             MULPS_xmm_xmm( 0, 4 );
  2434             MULPS_xmm_xmm( 1, 5 );
  2435             MULPS_xmm_xmm( 2, 6 );
  2436             MULPS_xmm_xmm( 3, 7 );
  2437             ADDPS_xmm_xmm( 5, 4 );
  2438             ADDPS_xmm_xmm( 7, 6 );
  2439             ADDPS_xmm_xmm( 6, 4 );
  2440             MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
  2441         } else {
  2442             LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );
  2443             CALL1_ptr_r32( sh4_ftrv, REG_EAX );
  2446     sh4_x86.tstate = TSTATE_NONE;
  2447 :}
  2449 FRCHG {:  
  2450     COUNT_INST(I_FRCHG);
  2451     check_fpuen();
  2452     XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR );
  2453     CALL_ptr( sh4_switch_fr_banks );
  2454     sh4_x86.tstate = TSTATE_NONE;
  2455 :}
  2456 FSCHG {:  
  2457     COUNT_INST(I_FSCHG);
  2458     check_fpuen();
  2459     XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR);
  2460     XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
  2461     sh4_x86.tstate = TSTATE_NONE;
  2462     sh4_x86.double_size = !sh4_x86.double_size;
  2463 :}
  2465 /* Processor control instructions */
  2466 LDC Rm, SR {:
  2467     COUNT_INST(I_LDCSR);
  2468     if( sh4_x86.in_delay_slot ) {
  2469 	SLOTILLEGAL();
  2470     } else {
  2471 	check_priv();
  2472 	load_reg( REG_EAX, Rm );
  2473 	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
  2474 	sh4_x86.fpuen_checked = FALSE;
  2475 	sh4_x86.tstate = TSTATE_NONE;
  2476 	return 2;
  2478 :}
  2479 LDC Rm, GBR {: 
  2480     COUNT_INST(I_LDC);
  2481     load_reg( REG_EAX, Rm );
  2482     MOVL_r32_rbpdisp( REG_EAX, R_GBR );
  2483 :}
  2484 LDC Rm, VBR {:  
  2485     COUNT_INST(I_LDC);
  2486     check_priv();
  2487     load_reg( REG_EAX, Rm );
  2488     MOVL_r32_rbpdisp( REG_EAX, R_VBR );
  2489     sh4_x86.tstate = TSTATE_NONE;
  2490 :}
  2491 LDC Rm, SSR {:  
  2492     COUNT_INST(I_LDC);
  2493     check_priv();
  2494     load_reg( REG_EAX, Rm );
  2495     MOVL_r32_rbpdisp( REG_EAX, R_SSR );
  2496     sh4_x86.tstate = TSTATE_NONE;
  2497 :}
  2498 LDC Rm, SGR {:  
  2499     COUNT_INST(I_LDC);
  2500     check_priv();
  2501     load_reg( REG_EAX, Rm );
  2502     MOVL_r32_rbpdisp( REG_EAX, R_SGR );
  2503     sh4_x86.tstate = TSTATE_NONE;
  2504 :}
  2505 LDC Rm, SPC {:  
  2506     COUNT_INST(I_LDC);
  2507     check_priv();
  2508     load_reg( REG_EAX, Rm );
  2509     MOVL_r32_rbpdisp( REG_EAX, R_SPC );
  2510     sh4_x86.tstate = TSTATE_NONE;
  2511 :}
  2512 LDC Rm, DBR {:  
  2513     COUNT_INST(I_LDC);
  2514     check_priv();
  2515     load_reg( REG_EAX, Rm );
  2516     MOVL_r32_rbpdisp( REG_EAX, R_DBR );
  2517     sh4_x86.tstate = TSTATE_NONE;
  2518 :}
  2519 LDC Rm, Rn_BANK {:  
  2520     COUNT_INST(I_LDC);
  2521     check_priv();
  2522     load_reg( REG_EAX, Rm );
  2523     MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2524     sh4_x86.tstate = TSTATE_NONE;
  2525 :}
  2526 LDC.L @Rm+, GBR {:  
  2527     COUNT_INST(I_LDCM);
  2528     load_reg( REG_EAX, Rm );
  2529     check_ralign32( REG_EAX );
  2530     MEM_READ_LONG( REG_EAX, REG_EAX );
  2531     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2532     MOVL_r32_rbpdisp( REG_EAX, R_GBR );
  2533     sh4_x86.tstate = TSTATE_NONE;
  2534 :}
  2535 LDC.L @Rm+, SR {:
  2536     COUNT_INST(I_LDCSRM);
  2537     if( sh4_x86.in_delay_slot ) {
  2538 	SLOTILLEGAL();
  2539     } else {
  2540 	check_priv();
  2541 	load_reg( REG_EAX, Rm );
  2542 	check_ralign32( REG_EAX );
  2543 	MEM_READ_LONG( REG_EAX, REG_EAX );
  2544 	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2545 	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
  2546 	sh4_x86.fpuen_checked = FALSE;
  2547 	sh4_x86.tstate = TSTATE_NONE;
  2548 	return 2;
  2550 :}
  2551 LDC.L @Rm+, VBR {:  
  2552     COUNT_INST(I_LDCM);
  2553     check_priv();
  2554     load_reg( REG_EAX, Rm );
  2555     check_ralign32( REG_EAX );
  2556     MEM_READ_LONG( REG_EAX, REG_EAX );
  2557     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2558     MOVL_r32_rbpdisp( REG_EAX, R_VBR );
  2559     sh4_x86.tstate = TSTATE_NONE;
  2560 :}
  2561 LDC.L @Rm+, SSR {:
  2562     COUNT_INST(I_LDCM);
  2563     check_priv();
  2564     load_reg( REG_EAX, Rm );
  2565     check_ralign32( REG_EAX );
  2566     MEM_READ_LONG( REG_EAX, REG_EAX );
  2567     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2568     MOVL_r32_rbpdisp( REG_EAX, R_SSR );
  2569     sh4_x86.tstate = TSTATE_NONE;
  2570 :}
  2571 LDC.L @Rm+, SGR {:  
  2572     COUNT_INST(I_LDCM);
  2573     check_priv();
  2574     load_reg( REG_EAX, Rm );
  2575     check_ralign32( REG_EAX );
  2576     MEM_READ_LONG( REG_EAX, REG_EAX );
  2577     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2578     MOVL_r32_rbpdisp( REG_EAX, R_SGR );
  2579     sh4_x86.tstate = TSTATE_NONE;
  2580 :}
  2581 LDC.L @Rm+, SPC {:  
  2582     COUNT_INST(I_LDCM);
  2583     check_priv();
  2584     load_reg( REG_EAX, Rm );
  2585     check_ralign32( REG_EAX );
  2586     MEM_READ_LONG( REG_EAX, REG_EAX );
  2587     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2588     MOVL_r32_rbpdisp( REG_EAX, R_SPC );
  2589     sh4_x86.tstate = TSTATE_NONE;
  2590 :}
  2591 LDC.L @Rm+, DBR {:  
  2592     COUNT_INST(I_LDCM);
  2593     check_priv();
  2594     load_reg( REG_EAX, Rm );
  2595     check_ralign32( REG_EAX );
  2596     MEM_READ_LONG( REG_EAX, REG_EAX );
  2597     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2598     MOVL_r32_rbpdisp( REG_EAX, R_DBR );
  2599     sh4_x86.tstate = TSTATE_NONE;
  2600 :}
  2601 LDC.L @Rm+, Rn_BANK {:  
  2602     COUNT_INST(I_LDCM);
  2603     check_priv();
  2604     load_reg( REG_EAX, Rm );
  2605     check_ralign32( REG_EAX );
  2606     MEM_READ_LONG( REG_EAX, REG_EAX );
  2607     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2608     MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2609     sh4_x86.tstate = TSTATE_NONE;
  2610 :}
  2611 LDS Rm, FPSCR {:
  2612     COUNT_INST(I_LDSFPSCR);
  2613     check_fpuen();
  2614     load_reg( REG_EAX, Rm );
  2615     CALL1_ptr_r32( sh4_write_fpscr, REG_EAX );
  2616     sh4_x86.tstate = TSTATE_NONE;
  2617     return 2;
  2618 :}
  2619 LDS.L @Rm+, FPSCR {:  
  2620     COUNT_INST(I_LDSFPSCRM);
  2621     check_fpuen();
  2622     load_reg( REG_EAX, Rm );
  2623     check_ralign32( REG_EAX );
  2624     MEM_READ_LONG( REG_EAX, REG_EAX );
  2625     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2626     CALL1_ptr_r32( sh4_write_fpscr, REG_EAX );
  2627     sh4_x86.tstate = TSTATE_NONE;
  2628     return 2;
  2629 :}
  2630 LDS Rm, FPUL {:  
  2631     COUNT_INST(I_LDS);
  2632     check_fpuen();
  2633     load_reg( REG_EAX, Rm );
  2634     MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
  2635 :}
  2636 LDS.L @Rm+, FPUL {:  
  2637     COUNT_INST(I_LDSM);
  2638     check_fpuen();
  2639     load_reg( REG_EAX, Rm );
  2640     check_ralign32( REG_EAX );
  2641     MEM_READ_LONG( REG_EAX, REG_EAX );
  2642     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2643     MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
  2644     sh4_x86.tstate = TSTATE_NONE;
  2645 :}
  2646 LDS Rm, MACH {: 
  2647     COUNT_INST(I_LDS);
  2648     load_reg( REG_EAX, Rm );
  2649     MOVL_r32_rbpdisp( REG_EAX, R_MACH );
  2650 :}
  2651 LDS.L @Rm+, MACH {:  
  2652     COUNT_INST(I_LDSM);
  2653     load_reg( REG_EAX, Rm );
  2654     check_ralign32( REG_EAX );
  2655     MEM_READ_LONG( REG_EAX, REG_EAX );
  2656     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2657     MOVL_r32_rbpdisp( REG_EAX, R_MACH );
  2658     sh4_x86.tstate = TSTATE_NONE;
  2659 :}
  2660 LDS Rm, MACL {:  
  2661     COUNT_INST(I_LDS);
  2662     load_reg( REG_EAX, Rm );
  2663     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
  2664 :}
  2665 LDS.L @Rm+, MACL {:  
  2666     COUNT_INST(I_LDSM);
  2667     load_reg( REG_EAX, Rm );
  2668     check_ralign32( REG_EAX );
  2669     MEM_READ_LONG( REG_EAX, REG_EAX );
  2670     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2671     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
  2672     sh4_x86.tstate = TSTATE_NONE;
  2673 :}
  2674 LDS Rm, PR {:  
  2675     COUNT_INST(I_LDS);
  2676     load_reg( REG_EAX, Rm );
  2677     MOVL_r32_rbpdisp( REG_EAX, R_PR );
  2678 :}
  2679 LDS.L @Rm+, PR {:  
  2680     COUNT_INST(I_LDSM);
  2681     load_reg( REG_EAX, Rm );
  2682     check_ralign32( REG_EAX );
  2683     MEM_READ_LONG( REG_EAX, REG_EAX );
  2684     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  2685     MOVL_r32_rbpdisp( REG_EAX, R_PR );
  2686     sh4_x86.tstate = TSTATE_NONE;
  2687 :}
  2688 LDTLB {:  
  2689     COUNT_INST(I_LDTLB);
  2690     CALL_ptr( MMU_ldtlb );
  2691     sh4_x86.tstate = TSTATE_NONE;
  2692 :}
  2693 OCBI @Rn {:
  2694     COUNT_INST(I_OCBI);
  2695 :}
  2696 OCBP @Rn {:
  2697     COUNT_INST(I_OCBP);
  2698 :}
  2699 OCBWB @Rn {:
  2700     COUNT_INST(I_OCBWB);
  2701 :}
  2702 PREF @Rn {:
  2703     COUNT_INST(I_PREF);
  2704     load_reg( REG_EAX, Rn );
  2705     MEM_PREFETCH( REG_EAX );
  2706     sh4_x86.tstate = TSTATE_NONE;
  2707 :}
  2708 SLEEP {: 
  2709     COUNT_INST(I_SLEEP);
  2710     check_priv();
  2711     CALL_ptr( sh4_sleep );
  2712     sh4_x86.tstate = TSTATE_NONE;
  2713     sh4_x86.in_delay_slot = DELAY_NONE;
  2714     return 2;
  2715 :}
  2716 STC SR, Rn {:
  2717     COUNT_INST(I_STCSR);
  2718     check_priv();
  2719     CALL_ptr(sh4_read_sr);
  2720     store_reg( REG_EAX, Rn );
  2721     sh4_x86.tstate = TSTATE_NONE;
  2722 :}
  2723 STC GBR, Rn {:  
  2724     COUNT_INST(I_STC);
  2725     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
  2726     store_reg( REG_EAX, Rn );
  2727 :}
  2728 STC VBR, Rn {:  
  2729     COUNT_INST(I_STC);
  2730     check_priv();
  2731     MOVL_rbpdisp_r32( R_VBR, REG_EAX );
  2732     store_reg( REG_EAX, Rn );
  2733     sh4_x86.tstate = TSTATE_NONE;
  2734 :}
  2735 STC SSR, Rn {:  
  2736     COUNT_INST(I_STC);
  2737     check_priv();
  2738     MOVL_rbpdisp_r32( R_SSR, REG_EAX );
  2739     store_reg( REG_EAX, Rn );
  2740     sh4_x86.tstate = TSTATE_NONE;
  2741 :}
  2742 STC SPC, Rn {:  
  2743     COUNT_INST(I_STC);
  2744     check_priv();
  2745     MOVL_rbpdisp_r32( R_SPC, REG_EAX );
  2746     store_reg( REG_EAX, Rn );
  2747     sh4_x86.tstate = TSTATE_NONE;
  2748 :}
  2749 STC SGR, Rn {:  
  2750     COUNT_INST(I_STC);
  2751     check_priv();
  2752     MOVL_rbpdisp_r32( R_SGR, REG_EAX );
  2753     store_reg( REG_EAX, Rn );
  2754     sh4_x86.tstate = TSTATE_NONE;
  2755 :}
  2756 STC DBR, Rn {:  
  2757     COUNT_INST(I_STC);
  2758     check_priv();
  2759     MOVL_rbpdisp_r32( R_DBR, REG_EAX );
  2760     store_reg( REG_EAX, Rn );
  2761     sh4_x86.tstate = TSTATE_NONE;
  2762 :}
  2763 STC Rm_BANK, Rn {:
  2764     COUNT_INST(I_STC);
  2765     check_priv();
  2766     MOVL_rbpdisp_r32( REG_OFFSET(r_bank[Rm_BANK]), REG_EAX );
  2767     store_reg( REG_EAX, Rn );
  2768     sh4_x86.tstate = TSTATE_NONE;
  2769 :}
  2770 STC.L SR, @-Rn {:
  2771     COUNT_INST(I_STCSRM);
  2772     check_priv();
  2773     CALL_ptr( sh4_read_sr );
  2774     MOVL_r32_r32( REG_EAX, REG_EDX );
  2775     load_reg( REG_EAX, Rn );
  2776     check_walign32( REG_EAX );
  2777     LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
  2778     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2779     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2780     sh4_x86.tstate = TSTATE_NONE;
  2781 :}
  2782 STC.L VBR, @-Rn {:  
  2783     COUNT_INST(I_STCM);
  2784     check_priv();
  2785     load_reg( REG_EAX, Rn );
  2786     check_walign32( REG_EAX );
  2787     ADDL_imms_r32( -4, REG_EAX );
  2788     MOVL_rbpdisp_r32( R_VBR, REG_EDX );
  2789     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2790     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2791     sh4_x86.tstate = TSTATE_NONE;
  2792 :}
  2793 STC.L SSR, @-Rn {:  
  2794     COUNT_INST(I_STCM);
  2795     check_priv();
  2796     load_reg( REG_EAX, Rn );
  2797     check_walign32( REG_EAX );
  2798     ADDL_imms_r32( -4, REG_EAX );
  2799     MOVL_rbpdisp_r32( R_SSR, REG_EDX );
  2800     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2801     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2802     sh4_x86.tstate = TSTATE_NONE;
  2803 :}
  2804 STC.L SPC, @-Rn {:
  2805     COUNT_INST(I_STCM);
  2806     check_priv();
  2807     load_reg( REG_EAX, Rn );
  2808     check_walign32( REG_EAX );
  2809     ADDL_imms_r32( -4, REG_EAX );
  2810     MOVL_rbpdisp_r32( R_SPC, REG_EDX );
  2811     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2812     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2813     sh4_x86.tstate = TSTATE_NONE;
  2814 :}
  2815 STC.L SGR, @-Rn {:  
  2816     COUNT_INST(I_STCM);
  2817     check_priv();
  2818     load_reg( REG_EAX, Rn );
  2819     check_walign32( REG_EAX );
  2820     ADDL_imms_r32( -4, REG_EAX );
  2821     MOVL_rbpdisp_r32( R_SGR, REG_EDX );
  2822     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2823     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2824     sh4_x86.tstate = TSTATE_NONE;
  2825 :}
  2826 STC.L DBR, @-Rn {:  
  2827     COUNT_INST(I_STCM);
  2828     check_priv();
  2829     load_reg( REG_EAX, Rn );
  2830     check_walign32( REG_EAX );
  2831     ADDL_imms_r32( -4, REG_EAX );
  2832     MOVL_rbpdisp_r32( R_DBR, REG_EDX );
  2833     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2834     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2835     sh4_x86.tstate = TSTATE_NONE;
  2836 :}
  2837 STC.L Rm_BANK, @-Rn {:  
  2838     COUNT_INST(I_STCM);
  2839     check_priv();
  2840     load_reg( REG_EAX, Rn );
  2841     check_walign32( REG_EAX );
  2842     ADDL_imms_r32( -4, REG_EAX );
  2843     MOVL_rbpdisp_r32( REG_OFFSET(r_bank[Rm_BANK]), REG_EDX );
  2844     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2845     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2846     sh4_x86.tstate = TSTATE_NONE;
  2847 :}
  2848 STC.L GBR, @-Rn {:  
  2849     COUNT_INST(I_STCM);
  2850     load_reg( REG_EAX, Rn );
  2851     check_walign32( REG_EAX );
  2852     ADDL_imms_r32( -4, REG_EAX );
  2853     MOVL_rbpdisp_r32( R_GBR, REG_EDX );
  2854     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2855     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2856     sh4_x86.tstate = TSTATE_NONE;
  2857 :}
  2858 STS FPSCR, Rn {:  
  2859     COUNT_INST(I_STSFPSCR);
  2860     check_fpuen();
  2861     MOVL_rbpdisp_r32( R_FPSCR, REG_EAX );
  2862     store_reg( REG_EAX, Rn );
  2863 :}
  2864 STS.L FPSCR, @-Rn {:  
  2865     COUNT_INST(I_STSFPSCRM);
  2866     check_fpuen();
  2867     load_reg( REG_EAX, Rn );
  2868     check_walign32( REG_EAX );
  2869     ADDL_imms_r32( -4, REG_EAX );
  2870     MOVL_rbpdisp_r32( R_FPSCR, REG_EDX );
  2871     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2872     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2873     sh4_x86.tstate = TSTATE_NONE;
  2874 :}
  2875 STS FPUL, Rn {:  
  2876     COUNT_INST(I_STS);
  2877     check_fpuen();
  2878     MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
  2879     store_reg( REG_EAX, Rn );
  2880 :}
  2881 STS.L FPUL, @-Rn {:  
  2882     COUNT_INST(I_STSM);
  2883     check_fpuen();
  2884     load_reg( REG_EAX, Rn );
  2885     check_walign32( REG_EAX );
  2886     ADDL_imms_r32( -4, REG_EAX );
  2887     MOVL_rbpdisp_r32( R_FPUL, REG_EDX );
  2888     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2889     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2890     sh4_x86.tstate = TSTATE_NONE;
  2891 :}
  2892 STS MACH, Rn {:  
  2893     COUNT_INST(I_STS);
  2894     MOVL_rbpdisp_r32( R_MACH, REG_EAX );
  2895     store_reg( REG_EAX, Rn );
  2896 :}
  2897 STS.L MACH, @-Rn {:  
  2898     COUNT_INST(I_STSM);
  2899     load_reg( REG_EAX, Rn );
  2900     check_walign32( REG_EAX );
  2901     ADDL_imms_r32( -4, REG_EAX );
  2902     MOVL_rbpdisp_r32( R_MACH, REG_EDX );
  2903     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2904     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2905     sh4_x86.tstate = TSTATE_NONE;
  2906 :}
  2907 STS MACL, Rn {:  
  2908     COUNT_INST(I_STS);
  2909     MOVL_rbpdisp_r32( R_MACL, REG_EAX );
  2910     store_reg( REG_EAX, Rn );
  2911 :}
  2912 STS.L MACL, @-Rn {:  
  2913     COUNT_INST(I_STSM);
  2914     load_reg( REG_EAX, Rn );
  2915     check_walign32( REG_EAX );
  2916     ADDL_imms_r32( -4, REG_EAX );
  2917     MOVL_rbpdisp_r32( R_MACL, REG_EDX );
  2918     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2919     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2920     sh4_x86.tstate = TSTATE_NONE;
  2921 :}
  2922 STS PR, Rn {:  
  2923     COUNT_INST(I_STS);
  2924     MOVL_rbpdisp_r32( R_PR, REG_EAX );
  2925     store_reg( REG_EAX, Rn );
  2926 :}
  2927 STS.L PR, @-Rn {:  
  2928     COUNT_INST(I_STSM);
  2929     load_reg( REG_EAX, Rn );
  2930     check_walign32( REG_EAX );
  2931     ADDL_imms_r32( -4, REG_EAX );
  2932     MOVL_rbpdisp_r32( R_PR, REG_EDX );
  2933     MEM_WRITE_LONG( REG_EAX, REG_EDX );
  2934     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
  2935     sh4_x86.tstate = TSTATE_NONE;
  2936 :}
  2938 NOP {: 
  2939     COUNT_INST(I_NOP);
  2940     /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ 
  2941 :}
  2942 %%
  2943     sh4_x86.in_delay_slot = DELAY_NONE;
  2944     return 0;
  2948 /**
  2949  * The unwind methods only work if we compiled with DWARF2 frame information
  2950  * (ie -fexceptions), otherwise we have to use the direct frame scan.
  2951  */
  2952 #ifdef HAVE_EXCEPTIONS
  2953 #include <unwind.h>
  2955 struct UnwindInfo {
  2956     uintptr_t block_start;
  2957     uintptr_t block_end;
  2958     void *pc;
  2959 };
  2961 static _Unwind_Reason_Code xlat_check_frame( struct _Unwind_Context *context, void *arg )
  2963     struct UnwindInfo *info = arg;
  2964     void *pc = (void *)_Unwind_GetIP(context);
  2965     if( ((uintptr_t)pc) >= info->block_start && ((uintptr_t)pc) < info->block_end ) {
  2966         info->pc = pc;
  2967         return _URC_NORMAL_STOP;
  2969     return _URC_NO_REASON;
  2972 void *xlat_get_native_pc( void *code, uint32_t code_size )
  2974     struct _Unwind_Exception exc;
  2975     struct UnwindInfo info;
  2977     info.pc = NULL;
  2978     info.block_start = (uintptr_t)code;
  2979     info.block_end = info.block_start + code_size;
  2980     void *result = NULL;
  2981     _Unwind_Backtrace( xlat_check_frame, &info );
  2982     return info.pc;
  2984 #else
  2985 /* Assume this is an ia32 build - amd64 should always have dwarf information */
  2986 void *xlat_get_native_pc( void *code, uint32_t code_size )
  2988     void *result = NULL;
  2989     asm(
  2990         "mov %%ebp, %%eax\n\t"
  2991         "mov $0x8, %%ecx\n\t"
  2992         "mov %1, %%edx\n"
  2993         "frame_loop: test %%eax, %%eax\n\t"
  2994         "je frame_not_found\n\t"
  2995         "cmp (%%eax), %%edx\n\t"
  2996         "je frame_found\n\t"
  2997         "sub $0x1, %%ecx\n\t"
  2998         "je frame_not_found\n\t"
  2999         "movl (%%eax), %%eax\n\t"
  3000         "jmp frame_loop\n"
  3001         "frame_found: movl 0x4(%%eax), %0\n"
  3002         "frame_not_found:"
  3003         : "=r" (result)
  3004         : "r" (((uint8_t *)&sh4r) + 128 )
  3005         : "eax", "ecx", "edx" );
  3006     return result;
  3008 #endif
.