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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 144:7f0714e89aaa
prev133:249aeda31f02
next151:3d3135644b8e
author nkeynes
date Mon May 15 08:28:52 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Rename video_driver to display_driver
Add input source to display
Implement configuration file support
Hook controllers up to configuration
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     1 /**
     2  * $Id: pvr2.c,v 1.23 2006-05-15 08:28:52 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "display.h"
    22 #include "mem.h"
    23 #include "asic.h"
    24 #include "pvr2/pvr2.h"
    25 #include "sh4/sh4core.h"
    26 #define MMIO_IMPL
    27 #include "pvr2/pvr2mmio.h"
    29 char *video_base;
    31 static void pvr2_init( void );
    32 static void pvr2_reset( void );
    33 static uint32_t pvr2_run_slice( uint32_t );
    34 static void pvr2_save_state( FILE *f );
    35 static int pvr2_load_state( FILE *f );
    37 void pvr2_display_frame( void );
    39 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    40 					pvr2_run_slice, NULL,
    41 					pvr2_save_state, pvr2_load_state };
    44 display_driver_t display_driver = NULL;
    46 struct video_timing {
    47     int fields_per_second;
    48     int total_lines;
    49     int retrace_lines;
    50     int line_time_ns;
    51 };
    53 struct video_timing pal_timing = { 50, 625, 65, 32000 };
    54 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    56 struct pvr2_state {
    57     uint32_t frame_count;
    58     uint32_t line_count;
    59     uint32_t line_remainder;
    60     uint32_t irq_vpos1;
    61     uint32_t irq_vpos2;
    62     gboolean retrace;
    63     struct video_timing timing;
    64 } pvr2_state;
    66 struct video_buffer video_buffer[2];
    67 int video_buffer_idx = 0;
    69 static void pvr2_init( void )
    70 {
    71     register_io_region( &mmio_region_PVR2 );
    72     register_io_region( &mmio_region_PVR2PAL );
    73     register_io_region( &mmio_region_PVR2TA );
    74     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    75     texcache_init();
    76     pvr2_reset();
    77 }
    79 static void pvr2_reset( void )
    80 {
    81     pvr2_state.line_count = 0;
    82     pvr2_state.line_remainder = 0;
    83     pvr2_state.irq_vpos1 = 0;
    84     pvr2_state.irq_vpos2 = 0;
    85     pvr2_state.retrace = FALSE;
    86     pvr2_state.timing = ntsc_timing;
    87     video_buffer_idx = 0;
    89     pvr2_ta_init();
    90     pvr2_render_init();
    91     texcache_flush();
    92 }
    94 static void pvr2_save_state( FILE *f )
    95 {
    96     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
    97 }
    99 static int pvr2_load_state( FILE *f )
   100 {
   101     fread( &pvr2_state, sizeof(pvr2_state), 1, f );
   102 }
   104 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   105 {
   106     pvr2_state.line_remainder += nanosecs;
   107     while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
   108 	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
   110 	pvr2_state.line_count++;
   111 	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
   112 	    asic_event( EVENT_RETRACE );
   113 	    pvr2_state.line_count = 0;
   114 	    pvr2_state.retrace = TRUE;
   115 	}
   117 	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
   118 	    asic_event( EVENT_SCANLINE1 );
   119 	} 
   120 	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
   121 	    asic_event( EVENT_SCANLINE2 );
   122 	}
   124 	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
   125 	    if( pvr2_state.retrace ) {
   126 		pvr2_display_frame();
   127 		pvr2_state.retrace = FALSE;
   128 	    }
   129 	}
   130     }
   131     return nanosecs;
   132 }
   134 int pvr2_get_frame_count() 
   135 {
   136     return pvr2_state.frame_count;
   137 }
   139 /**
   140  * Display the next frame, copying the current contents of video ram to
   141  * the window. If the video configuration has changed, first recompute the
   142  * new frame size/depth.
   143  */
   144 void pvr2_display_frame( void )
   145 {
   146     uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
   148     int dispsize = MMIO_READ( PVR2, DISPSIZE );
   149     int dispmode = MMIO_READ( PVR2, DISPMODE );
   150     int vidcfg = MMIO_READ( PVR2, DISPCFG );
   151     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
   152     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   153     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   154     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   155     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
   156     if( bEnabled ) {
   157 	video_buffer_t buffer = &video_buffer[video_buffer_idx];
   158 	video_buffer_idx = !video_buffer_idx;
   159 	video_buffer_t last = &video_buffer[video_buffer_idx];
   160 	buffer->rowstride = (vid_ppl + vid_stride) << 2;
   161 	buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
   162 	buffer->vres = vid_lpf;
   163 	if( interlaced ) buffer->vres <<= 1;
   164 	switch( (dispmode & DISPMODE_COL) >> 2 ) {
   165 	case 0: 
   166 	    buffer->colour_format = COLFMT_ARGB1555;
   167 	    buffer->hres = vid_ppl << 1; 
   168 	    break;
   169 	case 1: 
   170 	    buffer->colour_format = COLFMT_RGB565;
   171 	    buffer->hres = vid_ppl << 1; 
   172 	    break;
   173 	case 2:
   174 	    buffer->colour_format = COLFMT_RGB888;
   175 	    buffer->hres = (vid_ppl << 2) / 3; 
   176 	    break;
   177 	case 3: 
   178 	    buffer->colour_format = COLFMT_ARGB8888;
   179 	    buffer->hres = vid_ppl; 
   180 	    break;
   181 	}
   183 	if( display_driver != NULL ) {
   184 	    if( buffer->hres != last->hres ||
   185 		buffer->vres != last->vres ||
   186 		buffer->colour_format != last->colour_format) {
   187 		display_driver->set_display_format( buffer->hres, buffer->vres,
   188 						  buffer->colour_format );
   189 	    }
   190 	    if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
   191 		uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
   192 		display_driver->display_blank_frame( colour );
   193 	    } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
   194 		display_driver->display_frame( buffer );
   195 	    }
   196 	}
   197     } else {
   198 	video_buffer_idx = 0;
   199 	video_buffer[0].hres = video_buffer[0].vres = 0;
   200     }
   201     pvr2_state.frame_count++;
   202 }
   204 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   205 {
   206     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   207         MMIO_WRITE( PVR2, reg, val );
   208         /* I don't want to hear about these */
   209         return;
   210     }
   212     INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
   213           MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
   215     MMIO_WRITE( PVR2, reg, val );
   217     switch(reg) {
   218     case DISPADDR1:
   219 	if( pvr2_state.retrace ) {
   220 	    pvr2_display_frame();
   221 	    pvr2_state.retrace = FALSE;
   222 	}
   223 	break;
   224     case VPOS_IRQ:
   225 	pvr2_state.irq_vpos1 = (val >> 16) & 0x03FF;
   226 	pvr2_state.irq_vpos2 = val & 0x03FF;
   227 	break;
   228     case TAINIT:
   229 	if( val & 0x80000000 )
   230 	    pvr2_ta_init();
   231 	break;
   232     case RENDSTART:
   233 	if( val == 0xFFFFFFFF )
   234 	    pvr2_render_scene();
   235 	break;
   236     }
   237 }
   239 MMIO_REGION_READ_FN( PVR2, reg )
   240 {
   241     switch( reg ) {
   242         case BEAMPOS:
   243             return sh4r.icount&0x20 ? 0x2000 : 1;
   244         default:
   245             return MMIO_READ( PVR2, reg );
   246     }
   247 }
   249 MMIO_REGION_DEFFNS( PVR2PAL )
   251 void pvr2_set_base_address( uint32_t base ) 
   252 {
   253     mmio_region_PVR2_write( DISPADDR1, base );
   254 }
   259 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   260 {
   261     return 0xFFFFFFFF;
   262 }
   264 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   265 {
   266     pvr2_ta_write( &val, sizeof(uint32_t) );
   267 }
   270 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
   271 {
   272     int bank_flag = (destaddr & 0x04) >> 2;
   273     uint32_t *banks[2];
   274     uint32_t *dwsrc;
   275     int i;
   277     destaddr = destaddr & 0x7FFFFF;
   278     if( destaddr + length > 0x800000 ) {
   279 	length = 0x800000 - destaddr;
   280     }
   282     for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
   283 	texcache_invalidate_page( i );
   284     }
   286     banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
   287     banks[1] = banks[0] + 0x100000;
   288     if( bank_flag ) 
   289 	banks[0]++;
   291     /* Handle non-aligned start of source */
   292     if( destaddr & 0x03 ) {
   293 	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
   294 	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   295 	    *dest++ = *src++;
   296 	}
   297 	bank_flag = !bank_flag;
   298     }
   300     dwsrc = (uint32_t *)src;
   301     while( length >= 4 ) {
   302 	*banks[bank_flag]++ = *dwsrc++;
   303 	bank_flag = !bank_flag;
   304 	length -= 4;
   305     }
   307     /* Handle non-aligned end of source */
   308     if( length ) {
   309 	src = (char *)dwsrc;
   310 	char *dest = (char *)banks[bank_flag];
   311 	while( length-- > 0 ) {
   312 	    *dest++ = *src++;
   313 	}
   314     }  
   316 }
   318 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
   319 {
   320     int bank_flag = (srcaddr & 0x04) >> 2;
   321     uint32_t *banks[2];
   322     uint32_t *dwdest;
   323     int i;
   325     srcaddr = srcaddr & 0x7FFFFF;
   326     if( srcaddr + length > 0x800000 )
   327 	length = 0x800000 - srcaddr;
   329     banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
   330     banks[1] = banks[0] + 0x100000;
   331     if( bank_flag )
   332 	banks[0]++;
   334     /* Handle non-aligned start of source */
   335     if( srcaddr & 0x03 ) {
   336 	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
   337 	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   338 	    *dest++ = *src++;
   339 	}
   340 	bank_flag = !bank_flag;
   341     }
   343     dwdest = (uint32_t *)dest;
   344     while( length >= 4 ) {
   345 	*dwdest++ = *banks[bank_flag]++;
   346 	bank_flag = !bank_flag;
   347 	length -= 4;
   348     }
   350     /* Handle non-aligned end of source */
   351     if( length ) {
   352 	dest = (char *)dwdest;
   353 	char *src = (char *)banks[bank_flag];
   354 	while( length-- > 0 ) {
   355 	    *dest++ = *src++;
   356 	}
   357     }
   358 }
   360 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
   361 {
   362     char tmp[length];
   363     pvr2_vram64_read( tmp, addr, length );
   364     fwrite_dump( tmp, length, f );
   365 }
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