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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 279:7bb759c23271
prev255:ade289880b8d
next302:96b5cc24309c
author nkeynes
date Mon Jan 15 08:32:09 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Break vram routines out into pvr2mem.c
Initial (untested) implementation of stride textures
Hookup YUV converter code in pvr2.c
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     1 /**
     2  * $Id: asic.c,v 1.23 2007-01-14 02:54:40 nkeynes Exp $
     3  *
     4  * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
     5  * and DMA). 
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE asic_module
    22 #include <assert.h>
    23 #include <stdlib.h>
    24 #include "dream.h"
    25 #include "mem.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/dmac.h"
    28 #include "dreamcast.h"
    29 #include "maple/maple.h"
    30 #include "gdrom/ide.h"
    31 #include "asic.h"
    32 #define MMIO_IMPL
    33 #include "asic.h"
    34 /*
    35  * Open questions:
    36  *   1) Does changing the mask after event occurance result in the
    37  *      interrupt being delivered immediately?
    38  * TODO: Logic diagram of ASIC event/interrupt logic.
    39  *
    40  * ... don't even get me started on the "EXTDMA" page, about which, apparently,
    41  * practically nothing is publicly known...
    42  */
    44 static void asic_check_cleared_events( void );
    45 static void asic_init( void );
    46 static void asic_reset( void );
    47 static void asic_save_state( FILE *f );
    48 static int asic_load_state( FILE *f );
    50 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, NULL,
    51 					NULL, asic_save_state, asic_load_state };
    53 #define G2_BIT5_TICKS 8
    54 #define G2_BIT4_TICKS 16
    55 #define G2_BIT0_ON_TICKS 24
    56 #define G2_BIT0_OFF_TICKS 24
    58 struct asic_g2_state {
    59     unsigned int last_update_time;
    60     unsigned int bit5_off_timer;
    61     unsigned int bit4_on_timer;
    62     unsigned int bit4_off_timer;
    63     unsigned int bit0_on_timer;
    64     unsigned int bit0_off_timer;
    65 };
    67 static struct asic_g2_state g2_state;
    69 static void asic_init( void )
    70 {
    71     register_io_region( &mmio_region_ASIC );
    72     register_io_region( &mmio_region_EXTDMA );
    73     asic_reset();
    74 }
    76 static void asic_reset( void )
    77 {
    78     memset( &g2_state, 0, sizeof(g2_state) );
    79 }    
    81 static void asic_save_state( FILE *f )
    82 {
    83     fwrite( &g2_state, sizeof(g2_state), 1, f );
    84 }
    86 static int asic_load_state( FILE *f )
    87 {
    88     if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
    89 	return 1;
    90     else
    91 	return 0;
    92 }
    95 /* FIXME: Handle rollover */
    96 void asic_g2_write_word()
    97 {
    98     g2_state.last_update_time = sh4r.icount;
    99     g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
   100     if( g2_state.bit4_off_timer < sh4r.icount )
   101 	g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
   102     g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
   103     if( g2_state.bit0_off_timer < sh4r.icount ) {
   104 	g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
   105 	g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
   106     } else {
   107 	g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
   108     }
   109     MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
   110 }
   112 static uint32_t g2_read_status()
   113 {
   114     if( sh4r.icount < g2_state.last_update_time ) {
   115 	/* Rollover */
   116 	if( g2_state.last_update_time < g2_state.bit5_off_timer )
   117 	    g2_state.bit5_off_timer = 0;
   118 	if( g2_state.last_update_time < g2_state.bit4_off_timer )
   119 	    g2_state.bit4_off_timer = 0;
   120 	if( g2_state.last_update_time < g2_state.bit4_on_timer )
   121 	    g2_state.bit4_on_timer = 0;
   122 	if( g2_state.last_update_time < g2_state.bit0_off_timer )
   123 	    g2_state.bit0_off_timer = 0;
   124 	if( g2_state.last_update_time < g2_state.bit0_on_timer )
   125 	    g2_state.bit0_on_timer = 0;
   126     }
   127     uint32_t val = MMIO_READ( ASIC, G2STATUS );
   128     if( g2_state.bit5_off_timer <= sh4r.icount )
   129 	val = val & (~0x20);
   130     if( g2_state.bit4_off_timer <= sh4r.icount ||
   131 	(sh4r.icount + G2_BIT5_TICKS) < g2_state.bit4_off_timer )
   132 	val = val & (~0x10);
   133     else if( g2_state.bit4_on_timer <= sh4r.icount )
   134 	val = val | 0x10;
   135     if( g2_state.bit0_off_timer <= sh4r.icount )
   136 	val = val & (~0x01);
   137     else if( g2_state.bit0_on_timer <= sh4r.icount )
   138 	val = val | 0x01;
   139     return val | 0x0E;
   140 }   
   143 void asic_event( int event )
   144 {
   145     int offset = ((event&0x60)>>3);
   146     int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
   148     if( result & MMIO_READ(ASIC, IRQA0 + offset) )
   149         intc_raise_interrupt( INT_IRQ13 );
   150     if( result & MMIO_READ(ASIC, IRQB0 + offset) )
   151         intc_raise_interrupt( INT_IRQ11 );
   152     if( result & MMIO_READ(ASIC, IRQC0 + offset) )
   153         intc_raise_interrupt( INT_IRQ9 );
   154 }
   156 void asic_clear_event( int event ) {
   157     int offset = ((event&0x60)>>3);
   158     uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
   159     MMIO_WRITE( ASIC, PIRQ0 + offset, result );
   161     asic_check_cleared_events();
   162 }
   164 void asic_check_cleared_events( )
   165 {
   166     int i, setA = 0, setB = 0, setC = 0;
   167     uint32_t bits;
   168     for( i=0; i<3; i++ ) {
   169 	bits = MMIO_READ( ASIC, PIRQ0 + i );
   170 	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
   171 	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
   172 	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
   173     }
   174     if( setA == 0 )
   175 	intc_clear_interrupt( INT_IRQ13 );
   176     if( setB == 0 )
   177 	intc_clear_interrupt( INT_IRQ11 );
   178     if( setC == 0 )
   179 	intc_clear_interrupt( INT_IRQ9 );
   180 }
   182 void g2_dma_transfer( int channel )
   183 {
   184     uint32_t offset = channel << 5;
   186     if( MMIO_READ( EXTDMA, SPUDMA0CTL1 + offset ) == 1 ) {
   187 	if( MMIO_READ( EXTDMA, SPUDMA0CTL2 + offset ) == 1 ) {
   188 	    uint32_t extaddr = MMIO_READ( EXTDMA, SPUDMA0EXT + offset );
   189 	    uint32_t sh4addr = MMIO_READ( EXTDMA, SPUDMA0SH4 + offset );
   190 	    uint32_t length = MMIO_READ( EXTDMA, SPUDMA0SIZ + offset ) & 0x1FFFFFFF;
   191 	    uint32_t dir = MMIO_READ( EXTDMA, SPUDMA0DIR + offset );
   192 	    uint32_t mode = MMIO_READ( EXTDMA, SPUDMA0MOD + offset );
   193 	    char buf[length];
   194 	    if( dir == 0 ) { /* SH4 to device */
   195 		mem_copy_from_sh4( buf, sh4addr, length );
   196 		mem_copy_to_sh4( extaddr, buf, length );
   197 	    } else { /* Device to SH4 */
   198 		mem_copy_from_sh4( buf, extaddr, length );
   199 		mem_copy_to_sh4( sh4addr, buf, length );
   200 	    }
   201 	    MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
   202 	    asic_event( EVENT_SPU_DMA0 + channel );
   203 	} else {
   204 	    MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
   205 	}
   206     }
   207 }
   209 void asic_ide_dma_transfer( )
   210 {	
   211     if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
   212 	if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
   213 	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
   215 	    uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
   216 	    uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
   217 	    int dir = MMIO_READ( EXTDMA, IDEDMADIR );
   219 	    uint32_t xfer = ide_read_data_dma( addr, length );
   220 	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
   221 	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
   222 	} else { /* 0 */
   223 	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
   224 	}
   225     }
   227 }
   230 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
   231 {
   232     switch( reg ) {
   233     case PIRQ1:
   234 	val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
   235 	/* fallthrough */
   236     case PIRQ0:
   237     case PIRQ2:
   238 	/* Clear any interrupts */
   239 	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
   240 	asic_check_cleared_events();
   241 	break;
   242     case SYSRESET:
   243 	if( val == 0x7611 ) {
   244 	    dreamcast_reset();
   245 	    sh4r.new_pc = sh4r.pc;
   246 	} else {
   247 	    WARN( "Unknown value %08X written to SYSRESET port", val );
   248 	}
   249 	break;
   250     case MAPLE_STATE:
   251 	MMIO_WRITE( ASIC, reg, val );
   252 	if( val & 1 ) {
   253 	    uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
   254 	    maple_handle_buffer( maple_addr );
   255 	    MMIO_WRITE( ASIC, reg, 0 );
   256 	}
   257 	break;
   258     case PVRDMACTL: /* Initiate PVR DMA transfer */
   259 	MMIO_WRITE( ASIC, reg, val );
   260 	if( val & 1 ) {
   261 	    uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
   262 	    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
   263 	    char *data = alloca( count );
   264 	    uint32_t rcount = DMAC_get_buffer( 2, data, count );
   265 	    if( rcount != count )
   266 		WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
   267 	    mem_copy_to_sh4( dest_addr, data, rcount );
   268 	    asic_event( EVENT_PVR_DMA );
   269 	    MMIO_WRITE( ASIC, PVRDMACTL, 0 );
   270 	    MMIO_WRITE( ASIC, PVRDMACNT, 0 );
   271 	}
   272 	break;
   273     case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:
   274 	MMIO_WRITE( ASIC, reg, val );
   275 	break;
   276     default:
   277 	MMIO_WRITE( ASIC, reg, val );
   278     }
   279 }
   281 int32_t mmio_region_ASIC_read( uint32_t reg )
   282 {
   283     int32_t val;
   284     switch( reg ) {
   285         /*
   286         case 0x89C:
   287             sh4_stop();
   288             return 0x000000B;
   289         */     
   290     case PIRQ0:
   291     case PIRQ1:
   292     case PIRQ2:
   293     case IRQA0:
   294     case IRQA1:
   295     case IRQA2:
   296     case IRQB0:
   297     case IRQB1:
   298     case IRQB2:
   299     case IRQC0:
   300     case IRQC1:
   301     case IRQC2:
   302     case MAPLE_STATE:
   303 	val = MMIO_READ(ASIC, reg);
   304 	return val;            
   305     case G2STATUS:
   306 	return g2_read_status();
   307     default:
   308 	val = MMIO_READ(ASIC, reg);
   309 	return val;
   310     }
   312 }
   314 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
   315 {
   316     if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
   317 	return; /* disabled */
   318     }
   320     switch( reg ) {
   321     case IDEALTSTATUS: /* Device control */
   322 	ide_write_control( val );
   323 	break;
   324     case IDEDATA:
   325 	ide_write_data_pio( val );
   326 	break;
   327     case IDEFEAT:
   328 	if( ide_can_write_regs() )
   329 	    idereg.feature = (uint8_t)val;
   330 	break;
   331     case IDECOUNT:
   332 	if( ide_can_write_regs() )
   333 	    idereg.count = (uint8_t)val;
   334 	break;
   335     case IDELBA0:
   336 	if( ide_can_write_regs() )
   337 	    idereg.lba0 = (uint8_t)val;
   338 	break;
   339     case IDELBA1:
   340 	if( ide_can_write_regs() )
   341 	    idereg.lba1 = (uint8_t)val;
   342 	break;
   343     case IDELBA2:
   344 	if( ide_can_write_regs() )
   345 	    idereg.lba2 = (uint8_t)val;
   346 	break;
   347     case IDEDEV:
   348 	if( ide_can_write_regs() )
   349 	    idereg.device = (uint8_t)val;
   350 	break;
   351     case IDECMD:
   352 	if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
   353 	    ide_write_command( (uint8_t)val );
   354 	}
   355 	break;
   356     case IDEDMACTL1:
   357     case IDEDMACTL2:
   358 	MMIO_WRITE( EXTDMA, reg, val );
   359 	asic_ide_dma_transfer( );
   360 	break;
   361     case IDEACTIVATE:
   362 	if( val == 0x001FFFFF ) {
   363 	    idereg.interface_enabled = TRUE;
   364 	    /* Conventional wisdom says that this is necessary but not
   365 	     * sufficient to enable the IDE interface.
   366 	     */
   367 	} else if( val == 0x000042FE ) {
   368 	    idereg.interface_enabled = FALSE;
   369 	}
   370 	break;
   371     case SPUDMA0CTL1:
   372     case SPUDMA0CTL2:
   373 	MMIO_WRITE( EXTDMA, reg, val );
   374 	g2_dma_transfer( 0 );
   375 	break;
   376     case SPUDMA0UN1:
   377 	break;
   378     case SPUDMA1CTL1:
   379     case SPUDMA1CTL2:
   380 	MMIO_WRITE( EXTDMA, reg, val );
   381 	g2_dma_transfer( 1 );
   382 	break;
   384     case SPUDMA1UN1:
   385 	break;
   386     case SPUDMA2CTL1:
   387     case SPUDMA2CTL2:
   388 	MMIO_WRITE( EXTDMA, reg, val );
   389 	g2_dma_transfer( 2 );
   390 	break;
   391     case SPUDMA2UN1:
   392 	break;
   393     case SPUDMA3CTL1:
   394     case SPUDMA3CTL2:
   395 	MMIO_WRITE( EXTDMA, reg, val );
   396 	g2_dma_transfer( 3 );
   397 	break;
   398     case SPUDMA3UN1:
   399 	break;
   400     case PVRDMA2CTL1:
   401     case PVRDMA2CTL2:
   402 	if( val != 0 ) {
   403 	    ERROR( "Write to unimplemented DMA control register %08X", reg );
   404 	    //dreamcast_stop();
   405 	    //sh4_stop();
   406 	}
   407 	break;
   408     default:
   409             MMIO_WRITE( EXTDMA, reg, val );
   410     }
   411 }
   413 MMIO_REGION_READ_FN( EXTDMA, reg )
   414 {
   415     uint32_t val;
   416     if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
   417 	return 0xFFFFFFFF; /* disabled */
   418     }
   420     switch( reg ) {
   421     case IDEALTSTATUS: 
   422 	val = idereg.status;
   423 	return val;
   424     case IDEDATA: return ide_read_data_pio( );
   425     case IDEFEAT: return idereg.error;
   426     case IDECOUNT:return idereg.count;
   427     case IDELBA0: return idereg.disc;
   428     case IDELBA1: return idereg.lba1;
   429     case IDELBA2: return idereg.lba2;
   430     case IDEDEV: return idereg.device;
   431     case IDECMD:
   432 	val = ide_read_status();
   433 	return val;
   434     default:
   435 	val = MMIO_READ( EXTDMA, reg );
   436 	return val;
   437     }
   438 }
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