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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 284:808617ee7135
prev282:01e53698ff38
next295:6637664291a8
author nkeynes
date Mon Jan 15 08:32:09 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Break vram routines out into pvr2mem.c
Initial (untested) implementation of stride textures
Hookup YUV converter code in pvr2.c
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     1 /**
     2  * $Id: pvr2.c,v 1.39 2007-01-15 08:32:09 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "eventq.h"
    22 #include "display.h"
    23 #include "mem.h"
    24 #include "asic.h"
    25 #include "clock.h"
    26 #include "pvr2/pvr2.h"
    27 #include "sh4/sh4core.h"
    28 #define MMIO_IMPL
    29 #include "pvr2/pvr2mmio.h"
    31 char *video_base;
    33 static void pvr2_init( void );
    34 static void pvr2_reset( void );
    35 static uint32_t pvr2_run_slice( uint32_t );
    36 static void pvr2_save_state( FILE *f );
    37 static int pvr2_load_state( FILE *f );
    38 static void pvr2_update_raster_posn( uint32_t nanosecs );
    39 static void pvr2_schedule_line_event( int eventid, int line );
    40 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines );
    41 uint32_t pvr2_get_sync_status();
    43 void pvr2_display_frame( void );
    45 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
    47 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    48 					pvr2_run_slice, NULL,
    49 					pvr2_save_state, pvr2_load_state };
    52 display_driver_t display_driver = NULL;
    54 struct video_timing {
    55     int fields_per_second;
    56     int total_lines;
    57     int retrace_lines;
    58     int line_time_ns;
    59 };
    61 struct video_timing pal_timing = { 50, 625, 65, 31945 };
    62 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    64 struct pvr2_state {
    65     uint32_t frame_count;
    66     uint32_t line_count;
    67     uint32_t line_remainder;
    68     uint32_t cycles_run; /* Cycles already executed prior to main time slice */
    69     uint32_t irq_vpos1;
    70     uint32_t irq_vpos2;
    71     uint32_t odd_even_field; /* 1 = odd, 0 = even */
    73     /* timing */
    74     uint32_t dot_clock;
    75     uint32_t total_lines;
    76     uint32_t line_size;
    77     uint32_t line_time_ns;
    78     uint32_t vsync_lines;
    79     uint32_t hsync_width_ns;
    80     uint32_t front_porch_ns;
    81     uint32_t back_porch_ns;
    82     uint32_t retrace_start_line;
    83     uint32_t retrace_end_line;
    84     gboolean interlaced;
    85     struct video_timing timing;
    86 } pvr2_state;
    88 struct video_buffer video_buffer[2];
    89 int video_buffer_idx = 0;
    91 /**
    92  * Event handler for the retrace callback (fires on line 0 normally)
    93  */
    94 static void pvr2_retrace_callback( int eventid ) {
    95     asic_event( eventid );
    96     pvr2_update_raster_posn(sh4r.slice_cycle);
    97     pvr2_schedule_line_event( EVENT_RETRACE, 0 );
    98 }
   100 /**
   101  * Event handler for the scanline callbacks. Fires the corresponding
   102  * ASIC event, and resets the timer for the next field.
   103  */
   104 static void pvr2_scanline_callback( int eventid ) {
   105     asic_event( eventid );
   106     pvr2_update_raster_posn(sh4r.slice_cycle);
   107     if( eventid == EVENT_SCANLINE1 ) {
   108 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1 );
   109     } else {
   110 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1 );
   111     }
   112 }
   114 static void pvr2_init( void )
   115 {
   116     register_io_region( &mmio_region_PVR2 );
   117     register_io_region( &mmio_region_PVR2PAL );
   118     register_io_region( &mmio_region_PVR2TA );
   119     register_event_callback( EVENT_RETRACE, pvr2_retrace_callback );
   120     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   121     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   122     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
   123     texcache_init();
   124     pvr2_reset();
   125     pvr2_ta_reset();
   126 }
   128 static void pvr2_reset( void )
   129 {
   130     pvr2_state.line_count = 0;
   131     pvr2_state.line_remainder = 0;
   132     pvr2_state.cycles_run = 0;
   133     pvr2_state.irq_vpos1 = 0;
   134     pvr2_state.irq_vpos2 = 0;
   135     pvr2_state.timing = ntsc_timing;
   136     pvr2_state.dot_clock = PVR2_DOT_CLOCK;
   137     pvr2_state.back_porch_ns = 4000;
   138     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
   139     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
   140     mmio_region_PVR2_write( YUV_ADDR, 0 );
   141     mmio_region_PVR2_write( YUV_CFG, 0 );
   142     video_buffer_idx = 0;
   144     pvr2_ta_init();
   145     pvr2_render_init();
   146     texcache_flush();
   147 }
   149 static void pvr2_save_state( FILE *f )
   150 {
   151     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   152     pvr2_ta_save_state( f );
   153 }
   155 static int pvr2_load_state( FILE *f )
   156 {
   157     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   158 	return 1;
   159     return pvr2_ta_load_state(f);
   160 }
   162 /**
   163  * Update the current raster position to the given number of nanoseconds,
   164  * relative to the last time slice. (ie the raster will be adjusted forward
   165  * by nanosecs - nanosecs_already_run_this_timeslice)
   166  */
   167 static void pvr2_update_raster_posn( uint32_t nanosecs )
   168 {
   169     uint32_t old_line_count = pvr2_state.line_count;
   170     if( pvr2_state.line_time_ns == 0 ) {
   171 	return; /* do nothing */
   172     }
   173     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
   174     pvr2_state.cycles_run = nanosecs;
   175     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
   176 	pvr2_state.line_count ++;
   177 	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
   178     }
   180     if( pvr2_state.line_count >= pvr2_state.total_lines ) {
   181 	pvr2_state.line_count -= pvr2_state.total_lines;
   182 	if( pvr2_state.interlaced ) {
   183 	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
   184 	}
   185     }
   186     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
   187 	(old_line_count < pvr2_state.retrace_end_line ||
   188 	 old_line_count > pvr2_state.line_count) ) {
   189 	pvr2_display_frame();
   190     }
   191 }
   193 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   194 {
   195     pvr2_update_raster_posn( nanosecs );
   196     pvr2_state.cycles_run = 0;
   197     return nanosecs;
   198 }
   200 int pvr2_get_frame_count() 
   201 {
   202     return pvr2_state.frame_count;
   203 }
   205 /**
   206  * Display the next frame, copying the current contents of video ram to
   207  * the window. If the video configuration has changed, first recompute the
   208  * new frame size/depth.
   209  */
   210 void pvr2_display_frame( void )
   211 {
   212     uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   214     int dispsize = MMIO_READ( PVR2, DISP_SIZE );
   215     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   216     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
   217     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
   218     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   219     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   220     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   221     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
   222     video_buffer_t buffer = &video_buffer[video_buffer_idx];
   223     video_buffer_idx = !video_buffer_idx;
   224     video_buffer_t last = &video_buffer[video_buffer_idx];
   225     buffer->rowstride = (vid_ppl + vid_stride) << 2;
   226     buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
   227     buffer->vres = vid_lpf;
   228     if( interlaced ) buffer->vres <<= 1;
   229     switch( (dispmode & DISPMODE_COL) >> 2 ) {
   230     case 0: 
   231 	buffer->colour_format = COLFMT_ARGB1555;
   232 	buffer->hres = vid_ppl << 1; 
   233 	break;
   234     case 1: 
   235 	buffer->colour_format = COLFMT_RGB565;
   236 	buffer->hres = vid_ppl << 1; 
   237 	break;
   238     case 2:
   239 	buffer->colour_format = COLFMT_RGB888;
   240 	buffer->hres = (vid_ppl << 2) / 3; 
   241 	break;
   242     case 3: 
   243 	buffer->colour_format = COLFMT_ARGB8888;
   244 	buffer->hres = vid_ppl; 
   245 	break;
   246     }
   248     if( buffer->hres <=8 )
   249 	buffer->hres = 640;
   250     if( buffer->vres <=8 )
   251 	buffer->vres = 480;
   252     if( display_driver != NULL ) {
   253 	if( buffer->hres != last->hres ||
   254 	    buffer->vres != last->vres ||
   255 	    buffer->colour_format != last->colour_format) {
   256 	    display_driver->set_display_format( buffer->hres, buffer->vres,
   257 						buffer->colour_format );
   258 	}
   259 	if( !bEnabled ) {
   260 	    display_driver->display_blank_frame( 0 );
   261 	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
   262 	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
   263 	    display_driver->display_blank_frame( colour );
   264 	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
   265 	    display_driver->display_frame( buffer );
   266 	}
   267     }
   268     pvr2_state.frame_count++;
   269 }
   271 /**
   272  * This has to handle every single register individually as they all get masked 
   273  * off differently (and its easier to do it at write time)
   274  */
   275 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   276 {
   277     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   278         MMIO_WRITE( PVR2, reg, val );
   279         return;
   280     }
   282     switch(reg) {
   283     case PVRID:
   284     case PVRVER:
   285     case GUNPOS: /* Read only registers */
   286 	break;
   287     case PVRRESET:
   288 	val &= 0x00000007; /* Do stuff? */
   289 	MMIO_WRITE( PVR2, reg, val );
   290 	break;
   291     case RENDER_START:
   292 	if( val == 0xFFFFFFFF || val == 0x00000001 )
   293 	    pvr2_render_scene();
   294 	break;
   295     case RENDER_POLYBASE:
   296     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   297     	break;
   298     case RENDER_TSPCFG:
   299     	MMIO_WRITE( PVR2, reg, val&0x00010101 );
   300     	break;
   301     case DISP_BORDER:
   302     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   303     	break;
   304     case DISP_MODE:
   305     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   306     	break;
   307     case RENDER_MODE:
   308     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   309     	break;
   310     case RENDER_SIZE:
   311     	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   312     	break;
   313     case DISP_ADDR1:
   314 	val &= 0x00FFFFFC;
   315 	MMIO_WRITE( PVR2, reg, val );
   316 	pvr2_update_raster_posn(sh4r.slice_cycle);
   317 	if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||
   318 	    pvr2_state.line_count < pvr2_state.retrace_end_line ) {
   319 	    pvr2_display_frame();
   320 	}
   321 	break;
   322     case DISP_ADDR2:
   323     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   324     	break;
   325     case DISP_SIZE:
   326     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   327     	break;
   328     case RENDER_ADDR1:
   329     case RENDER_ADDR2:
   330     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   331     	break;
   332     case RENDER_HCLIP:
   333 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   334 	break;
   335     case RENDER_VCLIP:
   336 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   337 	break;
   338     case DISP_HPOSIRQ:
   339 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   340 	break;
   341     case DISP_VPOSIRQ:
   342 	val = val & 0x03FF03FF;
   343 	pvr2_state.irq_vpos1 = (val >> 16);
   344 	pvr2_state.irq_vpos2 = val & 0x03FF;
   345 	pvr2_update_raster_posn(sh4r.slice_cycle);
   346 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
   347 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
   348 	MMIO_WRITE( PVR2, reg, val );
   349 	break;
   350     case RENDER_NEARCLIP:
   351 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   352 	break;
   353     case RENDER_SHADOW:
   354 	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   355 	break;
   356     case RENDER_OBJCFG:
   357     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   358     	break;
   359     case RENDER_TSPCLIP:
   360     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   361     	break;
   362     case RENDER_FARCLIP:
   363 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   364 	break;
   365     case RENDER_BGPLANE:
   366     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   367     	break;
   368     case RENDER_ISPCFG:
   369     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   370     	break;
   371     case VRAM_CFG1:
   372 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   373 	break;
   374     case VRAM_CFG2:
   375 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   376 	break;
   377     case VRAM_CFG3:
   378 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   379 	break;
   380     case RENDER_FOGTBLCOL:
   381     case RENDER_FOGVRTCOL:
   382 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   383 	break;
   384     case RENDER_FOGCOEFF:
   385 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   386 	break;
   387     case RENDER_CLAMPHI:
   388     case RENDER_CLAMPLO:
   389 	MMIO_WRITE( PVR2, reg, val );
   390 	break;
   391     case RENDER_TEXSIZE:
   392 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   393 	break;
   394     case RENDER_PALETTE:
   395 	MMIO_WRITE( PVR2, reg, val&0x00000003 );
   396 	break;
   398 	/********** CRTC registers *************/
   399     case DISP_HBORDER:
   400     case DISP_VBORDER:
   401 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   402 	break;
   403     case DISP_TOTAL:
   404 	val = val & 0x03FF03FF;
   405 	MMIO_WRITE( PVR2, reg, val );
   406 	pvr2_update_raster_posn(sh4r.slice_cycle);
   407 	pvr2_state.total_lines = (val >> 16) + 1;
   408 	pvr2_state.line_size = (val & 0x03FF) + 1;
   409 	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
   410 	pvr2_state.retrace_end_line = 0x2A;
   411 	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
   412 	pvr2_schedule_line_event( EVENT_RETRACE, 0 );
   413 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
   414 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
   415 	break;
   416     case DISP_SYNCCFG:
   417 	MMIO_WRITE( PVR2, reg, val&0x000003FF );
   418 	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
   419 	break;
   420     case DISP_SYNCTIME:
   421 	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
   422 	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
   423 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   424 	break;
   425     case DISP_CFG2:
   426 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   427 	break;
   428     case DISP_HPOS:
   429 	val = val & 0x03FF;
   430 	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
   431 	MMIO_WRITE( PVR2, reg, val );
   432 	break;
   433     case DISP_VPOS:
   434 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   435 	break;
   437 	/*********** Tile accelerator registers ***********/
   438     case TA_POLYPOS:
   439     case TA_LISTPOS:
   440 	/* Readonly registers */
   441 	break;
   442     case TA_TILEBASE:
   443     case TA_LISTEND:
   444     case TA_LISTBASE:
   445 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   446 	break;
   447     case RENDER_TILEBASE:
   448     case TA_POLYBASE:
   449     case TA_POLYEND:
   450 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   451 	break;
   452     case TA_TILESIZE:
   453 	MMIO_WRITE( PVR2, reg, val&0x000F003F );
   454 	break;
   455     case TA_TILECFG:
   456 	MMIO_WRITE( PVR2, reg, val&0x00133333 );
   457 	break;
   458     case TA_INIT:
   459 	if( val & 0x80000000 )
   460 	    pvr2_ta_init();
   461 	break;
   462     case TA_REINIT:
   463 	break;
   464 	/**************** Scaler registers? ****************/
   465     case SCALERCFG:
   466 	/* KOS suggests bits as follows:
   467 	 *   0: enable vertical scaling
   468 	 *  10: ???
   469 	 *  16: enable FSAA
   470 	 */
   471 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   472 	break;
   474     case YUV_ADDR:
   475 	val = val & 0x00FFFFF8;
   476 	MMIO_WRITE( PVR2, reg, val );
   477 	pvr2_yuv_init( val );
   478 	break;
   479     case YUV_CFG:
   480 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   481 	pvr2_yuv_set_config(val);
   482 	break;
   484 	/**************** Unknowns ***************/
   485     case PVRUNK1:
   486     	MMIO_WRITE( PVR2, reg, val&0x000007FF );
   487     	break;
   488     case PVRUNK2:
   489 	MMIO_WRITE( PVR2, reg, val&0x00000007 );
   490 	break;
   491     case PVRUNK3:
   492 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   493 	break;
   494     case PVRUNK5:
   495 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   496 	break;
   497     case PVRUNK6:
   498 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   499 	break;
   500     case PVRUNK7:
   501 	MMIO_WRITE( PVR2, reg, val&0x00000001 );
   502 	break;
   503     }
   504 }
   506 /**
   507  * Calculate the current read value of the syncstat register, using
   508  * the current SH4 clock time as an offset from the last timeslice.
   509  * The register reads (LSB to MSB) as:
   510  *     0..9  Current scan line
   511  *     10    Odd/even field (1 = odd, 0 = even)
   512  *     11    Display active (including border and overscan)
   513  *     12    Horizontal sync off
   514  *     13    Vertical sync off
   515  * Note this method is probably incorrect for anything other than straight
   516  * interlaced PAL/NTSC, and needs further testing. 
   517  */
   518 uint32_t pvr2_get_sync_status()
   519 {
   520     pvr2_update_raster_posn(sh4r.slice_cycle);
   521     uint32_t result = pvr2_state.line_count;
   523     if( pvr2_state.odd_even_field ) {
   524 	result |= 0x0400;
   525     }
   526     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
   527 	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
   528 	    result |= 0x1000; /* !HSYNC */
   529 	}
   530 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   531 	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
   532 		result |= 0x2800; /* Display active */
   533 	    } else {
   534 		result |= 0x2000; /* Front porch */
   535 	    }
   536 	}
   537     } else {
   538 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   539 	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
   540 		result |= 0x3800; /* Display active */
   541 	    } else {
   542 		result |= 0x3000;
   543 	    }
   544 	} else {
   545 	    result |= 0x1000; /* Back porch */
   546 	}
   547     }
   548     return result;
   549 }
   551 /**
   552  * Schedule an event for the start of the given line. If the line is actually
   553  * the current line, schedules it for the next field. 
   554  * The raster position should be updated before calling this method.
   555  */
   556 static void pvr2_schedule_line_event( int eventid, int line )
   557 {
   558     uint32_t time;
   559     if( line <= pvr2_state.line_count ) {
   560 	time = (pvr2_state.total_lines - pvr2_state.line_count + line) * pvr2_state.line_time_ns
   561 	    - pvr2_state.line_remainder;
   562     } else {
   563 	time = (line - pvr2_state.line_count) * pvr2_state.line_time_ns - pvr2_state.line_remainder;
   564     }
   566     if( line < pvr2_state.total_lines ) {
   567 	event_schedule( eventid, time );
   568     } else {
   569 	event_cancel( eventid );
   570     }
   571 }
   573 /**
   574  * Schedule a "scanline" event. This actually goes off at
   575  * 2 * line in even fields and 2 * line + 1 in odd fields.
   576  * Otherwise this behaves as per pvr2_schedule_line_event().
   577  * The raster position should be updated before calling this
   578  * method.
   579  */
   580 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines )
   581 {
   582     uint32_t field = pvr2_state.odd_even_field;
   583     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
   584 	field = !field;
   585     }
   587     line <<= 1;
   588     if( field ) {
   589 	line += 1;
   590     }
   592     if( line < pvr2_state.total_lines ) {
   593 	uint32_t lines;
   594 	uint32_t time;
   595 	if( line <= pvr2_state.line_count ) {
   596 	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
   597 	} else {
   598 	    lines = (line - pvr2_state.line_count);
   599 	}
   600 	if( lines <= minimum_lines ) {
   601 	    lines += pvr2_state.total_lines;
   602 	}
   603 	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder;
   604 	event_schedule( eventid, time );
   605     } else {
   606 	event_cancel( eventid );
   607     }
   608 }
   610 MMIO_REGION_READ_FN( PVR2, reg )
   611 {
   612     switch( reg ) {
   613         case DISP_SYNCSTAT:
   614             return pvr2_get_sync_status();
   615         default:
   616             return MMIO_READ( PVR2, reg );
   617     }
   618 }
   620 MMIO_REGION_DEFFNS( PVR2PAL )
   622 void pvr2_set_base_address( uint32_t base ) 
   623 {
   624     mmio_region_PVR2_write( DISP_ADDR1, base );
   625 }
   630 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   631 {
   632     return 0xFFFFFFFF;
   633 }
   635 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   636 {
   637     pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
   638 }
.