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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 937:81b0c79d9788
prev936:f394309c399a
next939:6f2302afeb89
author nkeynes
date Sat Dec 27 03:14:59 2008 +0000 (13 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Update sh4x86 to take advantage of SR assumptions. nice 2% there :)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include <setjmp.h>
    23 #include <assert.h>
    24 #include "lxdream.h"
    25 #include "dreamcast.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "eventq.h"
    29 #include "syscall.h"
    30 #include "sh4/intc.h"
    31 #include "sh4/sh4core.h"
    32 #include "sh4/sh4mmio.h"
    33 #include "sh4/sh4stat.h"
    34 #include "sh4/sh4trans.h"
    35 #include "sh4/xltcache.h"
    37 void sh4_init( void );
    38 void sh4_xlat_init( void );
    39 void sh4_reset( void );
    40 void sh4_start( void );
    41 void sh4_stop( void );
    42 void sh4_save_state( FILE *f );
    43 int sh4_load_state( FILE *f );
    45 uint32_t sh4_run_slice( uint32_t );
    46 uint32_t sh4_xlat_run_slice( uint32_t );
    48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    49         sh4_start, sh4_run_slice, sh4_stop,
    50         sh4_save_state, sh4_load_state };
    52 struct sh4_registers sh4r __attribute__((aligned(16)));
    53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    54 int sh4_breakpoint_count = 0;
    56 gboolean sh4_starting = FALSE;
    57 static gboolean sh4_use_translator = FALSE;
    58 static jmp_buf sh4_exit_jmp_buf;
    59 static gboolean sh4_running = FALSE;
    60 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
    62 void sh4_translate_set_enabled( gboolean use )
    63 {
    64     // No-op if the translator was not built
    65 #ifdef SH4_TRANSLATOR
    66     if( use ) {
    67         sh4_translate_init();
    68     }
    69     sh4_use_translator = use;
    70 #endif
    71 }
    73 gboolean sh4_translate_is_enabled()
    74 {
    75     return sh4_use_translator;
    76 }
    78 void sh4_init(void)
    79 {
    80     register_io_regions( mmio_list_sh4mmio );
    81     TMU_init();
    82     xlat_cache_init();
    83     sh4_mem_init();
    84     sh4_reset();
    85 #ifdef ENABLE_SH4STATS
    86     sh4_stats_reset();
    87 #endif
    88 }
    90 void sh4_start(void)
    91 {
    92     sh4_starting = TRUE;
    93 }
    95 void sh4_reset(void)
    96 {
    97     if(	sh4_use_translator ) {
    98         xlat_flush_cache();
    99     }
   101     /* zero everything out, for the sake of having a consistent state. */
   102     memset( &sh4r, 0, sizeof(sh4r) );
   104     /* Resume running if we were halted */
   105     sh4r.sh4_state = SH4_STATE_RUNNING;
   107     sh4r.pc    = 0xA0000000;
   108     sh4r.new_pc= 0xA0000002;
   109     sh4r.vbr   = 0x00000000;
   110     sh4r.fpscr = 0x00040001;
   111     sh4_write_sr(0x700000F0);
   113     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   114     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   116     /* Peripheral modules */
   117     CPG_reset();
   118     INTC_reset();
   119     MMU_reset();
   120     PMM_reset();
   121     TMU_reset();
   122     SCIF_reset();
   124 #ifdef ENABLE_SH4STATS
   125     sh4_stats_reset();
   126 #endif
   127 }
   129 void sh4_stop(void)
   130 {
   131     if(	sh4_use_translator ) {
   132         /* If we were running with the translator, update new_pc and in_delay_slot */
   133         sh4r.new_pc = sh4r.pc+2;
   134         sh4r.in_delay_slot = FALSE;
   135     }
   137 }
   139 /**
   140  * Execute a timeslice using translated code only (ie translate/execute loop)
   141  */
   142 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   143 {
   144     sh4r.slice_cycle = 0;
   146     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   147         sh4_sleep_run_slice(nanosecs);
   148     }
   150     /* Setup for sudden vm exits */
   151     switch( setjmp(sh4_exit_jmp_buf) ) {
   152     case CORE_EXIT_BREAKPOINT:
   153         sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   154         /* fallthrough */
   155     case CORE_EXIT_HALT:
   156         if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   157             TMU_run_slice( sh4r.slice_cycle );
   158             SCIF_run_slice( sh4r.slice_cycle );
   159             PMM_run_slice( sh4r.slice_cycle );
   160             dreamcast_stop();
   161             return sh4r.slice_cycle;
   162         }
   163     case CORE_EXIT_SYSRESET:
   164         dreamcast_reset();
   165         break;
   166     case CORE_EXIT_SLEEP:
   167         sh4_sleep_run_slice(nanosecs);
   168         break;  
   169     case CORE_EXIT_FLUSH_ICACHE:
   170 #ifdef SH4_TRANSLATOR
   171         xlat_flush_cache();
   172 #endif
   173         break;
   174     }
   176     sh4_running = TRUE;
   178     /* Execute the core's real slice */
   179 #ifdef SH4_TRANSLATOR
   180     if( sh4_use_translator ) {
   181         sh4_translate_run_slice(nanosecs);
   182     } else {
   183         sh4_emulate_run_slice(nanosecs);
   184     }
   185 #else
   186     sh4_emulate_run_slice(nanosecs);
   187 #endif
   189     /* And finish off the peripherals afterwards */
   191     sh4_running = FALSE;
   192     sh4_starting = FALSE;
   193     sh4r.slice_cycle = nanosecs;
   194     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   195         TMU_run_slice( nanosecs );
   196         SCIF_run_slice( nanosecs );
   197         PMM_run_slice( sh4r.slice_cycle );
   198     }
   199     return nanosecs;   
   200 }
   202 void sh4_core_exit( int exit_code )
   203 {
   204     if( sh4_running ) {
   205 #ifdef SH4_TRANSLATOR
   206         if( sh4_use_translator ) {
   207             sh4_translate_exit_recover();
   208         }
   209 #endif
   210         // longjmp back into sh4_run_slice
   211         sh4_running = FALSE;
   212         longjmp(sh4_exit_jmp_buf, exit_code);
   213     }
   214 }
   216 void sh4_flush_icache()
   217 {
   218 #ifdef SH4_TRANSLATOR
   219     // FIXME: Special case needs to be generalized
   220     if( sh4_use_translator ) {
   221         if( sh4_translate_flush_cache() ) {
   222             longjmp(sh4_exit_jmp_buf, CORE_EXIT_CONTINUE);
   223         }
   224     }
   225 #endif
   226 }
   228 void sh4_save_state( FILE *f )
   229 {
   230     if(	sh4_use_translator ) {
   231         /* If we were running with the translator, update new_pc and in_delay_slot */
   232         sh4r.new_pc = sh4r.pc+2;
   233         sh4r.in_delay_slot = FALSE;
   234     }
   236     fwrite( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
   237     MMU_save_state( f );
   238     CCN_save_state( f );
   239     PMM_save_state( f );
   240     INTC_save_state( f );
   241     TMU_save_state( f );
   242     SCIF_save_state( f );
   243 }
   245 int sh4_load_state( FILE * f )
   246 {
   247     if(	sh4_use_translator ) {
   248         xlat_flush_cache();
   249     }
   250     fread( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
   251     sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
   252     MMU_load_state( f );
   253     CCN_load_state( f );
   254     PMM_load_state( f );
   255     INTC_load_state( f );
   256     TMU_load_state( f );
   257     return SCIF_load_state( f );
   258 }
   260 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   261 {
   262     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   263     sh4_breakpoints[sh4_breakpoint_count].type = type;
   264     if( sh4_use_translator ) {
   265         xlat_invalidate_word( pc );
   266     }
   267     sh4_breakpoint_count++;
   268 }
   270 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   271 {
   272     int i;
   274     for( i=0; i<sh4_breakpoint_count; i++ ) {
   275         if( sh4_breakpoints[i].address == pc && 
   276                 sh4_breakpoints[i].type == type ) {
   277             while( ++i < sh4_breakpoint_count ) {
   278                 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   279                 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   280             }
   281             if( sh4_use_translator ) {
   282                 xlat_invalidate_word( pc );
   283             }
   284             sh4_breakpoint_count--;
   285             return TRUE;
   286         }
   287     }
   288     return FALSE;
   289 }
   291 int sh4_get_breakpoint( uint32_t pc )
   292 {
   293     int i;
   294     for( i=0; i<sh4_breakpoint_count; i++ ) {
   295         if( sh4_breakpoints[i].address == pc )
   296             return sh4_breakpoints[i].type;
   297     }
   298     return 0;
   299 }
   301 void sh4_set_pc( int pc )
   302 {
   303     sh4r.pc = pc;
   304     sh4r.new_pc = pc+2;
   305 }
   308 /******************************* Support methods ***************************/
   310 static void sh4_switch_banks( )
   311 {
   312     uint32_t tmp[8];
   314     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   315     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   316     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   317 }
   319 void FASTCALL sh4_switch_fr_banks()
   320 {
   321     int i;
   322     for( i=0; i<16; i++ ) {
   323         float tmp = sh4r.fr[0][i];
   324         sh4r.fr[0][i] = sh4r.fr[1][i];
   325         sh4r.fr[1][i] = tmp;
   326     }
   327 }
   329 void FASTCALL sh4_write_sr( uint32_t newval )
   330 {
   331     int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
   332     int newbank = (newval&SR_MDRB) == SR_MDRB;
   333     if( oldbank != newbank )
   334         sh4_switch_banks();
   335     sh4r.sr = newval & SR_MASK;
   336     sh4r.t = (newval&SR_T) ? 1 : 0;
   337     sh4r.s = (newval&SR_S) ? 1 : 0;
   338     sh4r.m = (newval&SR_M) ? 1 : 0;
   339     sh4r.q = (newval&SR_Q) ? 1 : 0;
   340     sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
   341     intc_mask_changed();
   342 }
   344 void FASTCALL sh4_write_fpscr( uint32_t newval )
   345 {
   346     if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
   347         sh4_switch_fr_banks();
   348     }
   349     sh4r.fpscr = newval & FPSCR_MASK;
   350     sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
   351 }
   353 uint32_t FASTCALL sh4_read_sr( void )
   354 {
   355     /* synchronize sh4r.sr with the various bitflags */
   356     sh4r.sr &= SR_MQSTMASK;
   357     if( sh4r.t ) sh4r.sr |= SR_T;
   358     if( sh4r.s ) sh4r.sr |= SR_S;
   359     if( sh4r.m ) sh4r.sr |= SR_M;
   360     if( sh4r.q ) sh4r.sr |= SR_Q;
   361     return sh4r.sr;
   362 }
   366 #define RAISE( x, v ) do{			\
   367     if( sh4r.vbr == 0 ) { \
   368         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   369         sh4_core_exit(CORE_EXIT_HALT); return FALSE;	\
   370     } else { \
   371         sh4r.spc = sh4r.pc;	\
   372         sh4r.ssr = sh4_read_sr(); \
   373         sh4r.sgr = sh4r.r[15]; \
   374         MMIO_WRITE(MMU,EXPEVT,x); \
   375         sh4r.pc = sh4r.vbr + v; \
   376         sh4r.new_pc = sh4r.pc + 2; \
   377         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   378         if( sh4r.in_delay_slot ) { \
   379             sh4r.in_delay_slot = 0; \
   380             sh4r.spc -= 2; \
   381         } \
   382     } \
   383     return TRUE; } while(0)
   385 /**
   386  * Raise a general CPU exception for the specified exception code.
   387  * (NOT for TRAPA or TLB exceptions)
   388  */
   389 gboolean FASTCALL sh4_raise_exception( int code )
   390 {
   391     RAISE( code, EXV_EXCEPTION );
   392 }
   394 /**
   395  * Raise a CPU reset exception with the specified exception code.
   396  */
   397 gboolean FASTCALL sh4_raise_reset( int code )
   398 {
   399     // FIXME: reset modules as per "manual reset"
   400     sh4_reset();
   401     MMIO_WRITE(MMU,EXPEVT,code);
   402     sh4r.vbr = 0;
   403     sh4r.pc = 0xA0000000;
   404     sh4r.new_pc = sh4r.pc + 2;
   405     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   406                   &(~SR_FD) );
   407     return TRUE;
   408 }
   410 gboolean FASTCALL sh4_raise_trap( int trap )
   411 {
   412     MMIO_WRITE( MMU, TRA, trap<<2 );
   413     RAISE( EXC_TRAP, EXV_EXCEPTION );
   414 }
   416 gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
   417     if( sh4r.in_delay_slot ) {
   418         return sh4_raise_exception(slot_code);
   419     } else {
   420         return sh4_raise_exception(normal_code);
   421     }
   422 }
   424 gboolean FASTCALL sh4_raise_tlb_exception( int code )
   425 {
   426     RAISE( code, EXV_TLBMISS );
   427 }
   429 void FASTCALL sh4_accept_interrupt( void )
   430 {
   431     uint32_t code = intc_accept_interrupt();
   432     sh4r.ssr = sh4_read_sr();
   433     sh4r.spc = sh4r.pc;
   434     sh4r.sgr = sh4r.r[15];
   435     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   436     MMIO_WRITE( MMU, INTEVT, code );
   437     sh4r.pc = sh4r.vbr + 0x600;
   438     sh4r.new_pc = sh4r.pc + 2;
   439     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   440 }
   442 void FASTCALL signsat48( void )
   443 {
   444     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   445         sh4r.mac = 0xFFFF800000000000LL;
   446     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   447         sh4r.mac = 0x00007FFFFFFFFFFFLL;
   448 }
   450 void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
   451 {
   452     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   453     *fr++ = cosf(angle);
   454     *fr = sinf(angle);
   455 }
   457 /**
   458  * Enter sleep mode (eg by executing a SLEEP instruction).
   459  * Sets sh4_state appropriately and ensures any stopping peripheral modules
   460  * are up to date.
   461  */
   462 void FASTCALL sh4_sleep(void)
   463 {
   464     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   465         sh4r.sh4_state = SH4_STATE_STANDBY;
   466         /* Bring all running peripheral modules up to date, and then halt them. */
   467         TMU_run_slice( sh4r.slice_cycle );
   468         SCIF_run_slice( sh4r.slice_cycle );
   469         PMM_run_slice( sh4r.slice_cycle );
   470     } else {
   471         if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
   472             sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
   473             /* Halt DMAC but other peripherals still running */
   475         } else {
   476             sh4r.sh4_state = SH4_STATE_SLEEP;
   477         }
   478     }
   479     sh4_core_exit( CORE_EXIT_SLEEP );
   480 }
   482 /**
   483  * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
   484  * and restarts any peripheral devices that were stopped.
   485  */
   486 void sh4_wakeup(void)
   487 {
   488     switch( sh4r.sh4_state ) {
   489     case SH4_STATE_STANDBY:
   490         break;
   491     case SH4_STATE_DEEP_SLEEP:
   492         break;
   493     case SH4_STATE_SLEEP:
   494         break;
   495     }
   496     sh4r.sh4_state = SH4_STATE_RUNNING;
   497 }
   499 /**
   500  * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
   501  * Returns when either the SH4 wakes up (interrupt received) or the end of
   502  * the slice is reached. Updates sh4.slice_cycle with the exit time and
   503  * returns the same value.
   504  */
   505 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
   506 {
   507     int sleep_state = sh4r.sh4_state;
   508     assert( sleep_state != SH4_STATE_RUNNING );
   510     while( sh4r.event_pending < nanosecs ) {
   511         sh4r.slice_cycle = sh4r.event_pending;
   512         if( sh4r.event_types & PENDING_EVENT ) {
   513             event_execute();
   514         }
   515         if( sh4r.event_types & PENDING_IRQ ) {
   516             sh4_wakeup();
   517             return sh4r.slice_cycle;
   518         }
   519     }
   520     sh4r.slice_cycle = nanosecs;
   521     return sh4r.slice_cycle;
   522 }
   525 /**
   526  * Compute the matrix tranform of fv given the matrix xf.
   527  * Both fv and xf are word-swapped as per the sh4r.fr banks
   528  */
   529 void FASTCALL sh4_ftrv( float *target )
   530 {
   531     float fv[4] = { target[1], target[0], target[3], target[2] };
   532     target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
   533     sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
   534     target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
   535     sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
   536     target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
   537     sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
   538     target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
   539     sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
   540 }
   542 gboolean sh4_has_page( sh4vma_t vma )
   543 {
   544     sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
   545     return addr != MMU_VMA_ERROR && mem_has_page(addr);
   546 }
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