4 * SH4 parent module for all CPU modes and SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
25 #include "dreamcast.h"
31 #include "sh4/sh4core.h"
32 #include "sh4/sh4mmio.h"
33 #include "sh4/sh4stat.h"
34 #include "sh4/sh4trans.h"
35 #include "sh4/xltcache.h"
37 void sh4_init( void );
38 void sh4_xlat_init( void );
39 void sh4_reset( void );
40 void sh4_start( void );
41 void sh4_stop( void );
42 void sh4_save_state( FILE *f );
43 int sh4_load_state( FILE *f );
45 uint32_t sh4_run_slice( uint32_t );
46 uint32_t sh4_xlat_run_slice( uint32_t );
48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
49 sh4_start, sh4_run_slice, sh4_stop,
50 sh4_save_state, sh4_load_state };
52 struct sh4_registers sh4r __attribute__((aligned(16)));
53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
54 int sh4_breakpoint_count = 0;
56 gboolean sh4_starting = FALSE;
57 static gboolean sh4_use_translator = FALSE;
58 static jmp_buf sh4_exit_jmp_buf;
59 static gboolean sh4_running = FALSE;
60 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
62 void sh4_translate_set_enabled( gboolean use )
64 // No-op if the translator was not built
69 sh4_use_translator = use;
73 gboolean sh4_translate_is_enabled()
75 return sh4_use_translator;
80 register_io_regions( mmio_list_sh4mmio );
85 #ifdef ENABLE_SH4STATS
97 if( sh4_use_translator ) {
101 /* zero everything out, for the sake of having a consistent state. */
102 memset( &sh4r, 0, sizeof(sh4r) );
104 /* Resume running if we were halted */
105 sh4r.sh4_state = SH4_STATE_RUNNING;
107 sh4r.pc = 0xA0000000;
108 sh4r.new_pc= 0xA0000002;
109 sh4r.vbr = 0x00000000;
110 sh4r.fpscr = 0x00040001;
111 sh4_write_sr(0x700000F0);
113 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
114 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
116 /* Peripheral modules */
124 #ifdef ENABLE_SH4STATS
131 if( sh4_use_translator ) {
132 /* If we were running with the translator, update new_pc and in_delay_slot */
133 sh4r.new_pc = sh4r.pc+2;
134 sh4r.in_delay_slot = FALSE;
140 * Execute a timeslice using translated code only (ie translate/execute loop)
142 uint32_t sh4_run_slice( uint32_t nanosecs )
144 sh4r.slice_cycle = 0;
146 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
147 sh4_sleep_run_slice(nanosecs);
150 /* Setup for sudden vm exits */
151 switch( setjmp(sh4_exit_jmp_buf) ) {
152 case CORE_EXIT_BREAKPOINT:
153 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
156 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
157 TMU_run_slice( sh4r.slice_cycle );
158 SCIF_run_slice( sh4r.slice_cycle );
159 PMM_run_slice( sh4r.slice_cycle );
161 return sh4r.slice_cycle;
163 case CORE_EXIT_SYSRESET:
166 case CORE_EXIT_SLEEP:
167 sh4_sleep_run_slice(nanosecs);
169 case CORE_EXIT_FLUSH_ICACHE:
170 #ifdef SH4_TRANSLATOR
178 /* Execute the core's real slice */
179 #ifdef SH4_TRANSLATOR
180 if( sh4_use_translator ) {
181 sh4_translate_run_slice(nanosecs);
183 sh4_emulate_run_slice(nanosecs);
186 sh4_emulate_run_slice(nanosecs);
189 /* And finish off the peripherals afterwards */
192 sh4_starting = FALSE;
193 sh4r.slice_cycle = nanosecs;
194 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
195 TMU_run_slice( nanosecs );
196 SCIF_run_slice( nanosecs );
197 PMM_run_slice( sh4r.slice_cycle );
202 void sh4_core_exit( int exit_code )
205 #ifdef SH4_TRANSLATOR
206 if( sh4_use_translator ) {
207 sh4_translate_exit_recover();
210 // longjmp back into sh4_run_slice
212 longjmp(sh4_exit_jmp_buf, exit_code);
216 void sh4_flush_icache()
218 #ifdef SH4_TRANSLATOR
219 // FIXME: Special case needs to be generalized
220 if( sh4_use_translator ) {
221 if( sh4_translate_flush_cache() ) {
222 longjmp(sh4_exit_jmp_buf, CORE_EXIT_CONTINUE);
228 void sh4_save_state( FILE *f )
230 if( sh4_use_translator ) {
231 /* If we were running with the translator, update new_pc and in_delay_slot */
232 sh4r.new_pc = sh4r.pc+2;
233 sh4r.in_delay_slot = FALSE;
236 fwrite( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
240 INTC_save_state( f );
242 SCIF_save_state( f );
245 int sh4_load_state( FILE * f )
247 if( sh4_use_translator ) {
250 fread( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
251 sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
255 INTC_load_state( f );
257 return SCIF_load_state( f );
260 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
262 sh4_breakpoints[sh4_breakpoint_count].address = pc;
263 sh4_breakpoints[sh4_breakpoint_count].type = type;
264 if( sh4_use_translator ) {
265 xlat_invalidate_word( pc );
267 sh4_breakpoint_count++;
270 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
274 for( i=0; i<sh4_breakpoint_count; i++ ) {
275 if( sh4_breakpoints[i].address == pc &&
276 sh4_breakpoints[i].type == type ) {
277 while( ++i < sh4_breakpoint_count ) {
278 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
279 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
281 if( sh4_use_translator ) {
282 xlat_invalidate_word( pc );
284 sh4_breakpoint_count--;
291 int sh4_get_breakpoint( uint32_t pc )
294 for( i=0; i<sh4_breakpoint_count; i++ ) {
295 if( sh4_breakpoints[i].address == pc )
296 return sh4_breakpoints[i].type;
301 void sh4_set_pc( int pc )
308 /******************************* Support methods ***************************/
310 static void sh4_switch_banks( )
314 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
315 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
316 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
319 void FASTCALL sh4_switch_fr_banks()
322 for( i=0; i<16; i++ ) {
323 float tmp = sh4r.fr[0][i];
324 sh4r.fr[0][i] = sh4r.fr[1][i];
329 void FASTCALL sh4_write_sr( uint32_t newval )
331 int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
332 int newbank = (newval&SR_MDRB) == SR_MDRB;
333 if( oldbank != newbank )
335 sh4r.sr = newval & SR_MASK;
336 sh4r.t = (newval&SR_T) ? 1 : 0;
337 sh4r.s = (newval&SR_S) ? 1 : 0;
338 sh4r.m = (newval&SR_M) ? 1 : 0;
339 sh4r.q = (newval&SR_Q) ? 1 : 0;
340 sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
344 void FASTCALL sh4_write_fpscr( uint32_t newval )
346 if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
347 sh4_switch_fr_banks();
349 sh4r.fpscr = newval & FPSCR_MASK;
350 sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
353 uint32_t FASTCALL sh4_read_sr( void )
355 /* synchronize sh4r.sr with the various bitflags */
356 sh4r.sr &= SR_MQSTMASK;
357 if( sh4r.t ) sh4r.sr |= SR_T;
358 if( sh4r.s ) sh4r.sr |= SR_S;
359 if( sh4r.m ) sh4r.sr |= SR_M;
360 if( sh4r.q ) sh4r.sr |= SR_Q;
366 #define RAISE( x, v ) do{ \
367 if( sh4r.vbr == 0 ) { \
368 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
369 sh4_core_exit(CORE_EXIT_HALT); return FALSE; \
371 sh4r.spc = sh4r.pc; \
372 sh4r.ssr = sh4_read_sr(); \
373 sh4r.sgr = sh4r.r[15]; \
374 MMIO_WRITE(MMU,EXPEVT,x); \
375 sh4r.pc = sh4r.vbr + v; \
376 sh4r.new_pc = sh4r.pc + 2; \
377 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
378 if( sh4r.in_delay_slot ) { \
379 sh4r.in_delay_slot = 0; \
383 return TRUE; } while(0)
386 * Raise a general CPU exception for the specified exception code.
387 * (NOT for TRAPA or TLB exceptions)
389 gboolean FASTCALL sh4_raise_exception( int code )
391 RAISE( code, EXV_EXCEPTION );
395 * Raise a CPU reset exception with the specified exception code.
397 gboolean FASTCALL sh4_raise_reset( int code )
399 // FIXME: reset modules as per "manual reset"
401 MMIO_WRITE(MMU,EXPEVT,code);
403 sh4r.pc = 0xA0000000;
404 sh4r.new_pc = sh4r.pc + 2;
405 sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
410 gboolean FASTCALL sh4_raise_trap( int trap )
412 MMIO_WRITE( MMU, TRA, trap<<2 );
413 RAISE( EXC_TRAP, EXV_EXCEPTION );
416 gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
417 if( sh4r.in_delay_slot ) {
418 return sh4_raise_exception(slot_code);
420 return sh4_raise_exception(normal_code);
424 gboolean FASTCALL sh4_raise_tlb_exception( int code )
426 RAISE( code, EXV_TLBMISS );
429 void FASTCALL sh4_accept_interrupt( void )
431 uint32_t code = intc_accept_interrupt();
432 sh4r.ssr = sh4_read_sr();
434 sh4r.sgr = sh4r.r[15];
435 sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
436 MMIO_WRITE( MMU, INTEVT, code );
437 sh4r.pc = sh4r.vbr + 0x600;
438 sh4r.new_pc = sh4r.pc + 2;
439 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
442 void FASTCALL signsat48( void )
444 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
445 sh4r.mac = 0xFFFF800000000000LL;
446 else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
447 sh4r.mac = 0x00007FFFFFFFFFFFLL;
450 void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
452 float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
458 * Enter sleep mode (eg by executing a SLEEP instruction).
459 * Sets sh4_state appropriately and ensures any stopping peripheral modules
462 void FASTCALL sh4_sleep(void)
464 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
465 sh4r.sh4_state = SH4_STATE_STANDBY;
466 /* Bring all running peripheral modules up to date, and then halt them. */
467 TMU_run_slice( sh4r.slice_cycle );
468 SCIF_run_slice( sh4r.slice_cycle );
469 PMM_run_slice( sh4r.slice_cycle );
471 if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
472 sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
473 /* Halt DMAC but other peripherals still running */
476 sh4r.sh4_state = SH4_STATE_SLEEP;
479 sh4_core_exit( CORE_EXIT_SLEEP );
483 * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
484 * and restarts any peripheral devices that were stopped.
486 void sh4_wakeup(void)
488 switch( sh4r.sh4_state ) {
489 case SH4_STATE_STANDBY:
491 case SH4_STATE_DEEP_SLEEP:
493 case SH4_STATE_SLEEP:
496 sh4r.sh4_state = SH4_STATE_RUNNING;
500 * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
501 * Returns when either the SH4 wakes up (interrupt received) or the end of
502 * the slice is reached. Updates sh4.slice_cycle with the exit time and
503 * returns the same value.
505 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
507 int sleep_state = sh4r.sh4_state;
508 assert( sleep_state != SH4_STATE_RUNNING );
510 while( sh4r.event_pending < nanosecs ) {
511 sh4r.slice_cycle = sh4r.event_pending;
512 if( sh4r.event_types & PENDING_EVENT ) {
515 if( sh4r.event_types & PENDING_IRQ ) {
517 return sh4r.slice_cycle;
520 sh4r.slice_cycle = nanosecs;
521 return sh4r.slice_cycle;
526 * Compute the matrix tranform of fv given the matrix xf.
527 * Both fv and xf are word-swapped as per the sh4r.fr banks
529 void FASTCALL sh4_ftrv( float *target )
531 float fv[4] = { target[1], target[0], target[3], target[2] };
532 target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
533 sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
534 target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
535 sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
536 target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
537 sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
538 target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
539 sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
542 gboolean sh4_has_page( sh4vma_t vma )
544 sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
545 return addr != MMU_VMA_ERROR && mem_has_page(addr);
.