2 * $Id: armcore.c,v 1.20 2006-01-22 22:40:05 nkeynes Exp $
4 * ARM7TDMI CPU emulation core.
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #define MODULE aica_module
22 #include "aica/armcore.h"
23 #include "aica/aica.h"
25 #define STM_R15_OFFSET 12
27 struct arm_registers armr;
29 void arm_set_mode( int mode );
31 uint32_t arm_exceptions[][2] = {{ MODE_SVC, 0x00000000 },
32 { MODE_UND, 0x00000004 },
33 { MODE_SVC, 0x00000008 },
34 { MODE_ABT, 0x0000000C },
35 { MODE_ABT, 0x00000010 },
36 { MODE_IRQ, 0x00000018 },
37 { MODE_FIQ, 0x0000001C } };
40 #define EXC_UNDEFINED 1
41 #define EXC_SOFTWARE 2
42 #define EXC_PREFETCH_ABORT 3
43 #define EXC_DATA_ABORT 4
45 #define EXC_FAST_IRQ 6
47 uint32_t arm_cpu_freq = ARM_BASE_RATE;
48 uint32_t arm_cpu_period = 1000 / ARM_BASE_RATE;
50 #define CYCLES_PER_SAMPLE ((ARM_BASE_RATE * 1000000) / AICA_SAMPLE_RATE)
52 static struct breakpoint_struct arm_breakpoints[MAX_BREAKPOINTS];
53 static int arm_breakpoint_count = 0;
55 void arm_set_breakpoint( uint32_t pc, int type )
57 arm_breakpoints[arm_breakpoint_count].address = pc;
58 arm_breakpoints[arm_breakpoint_count].type = type;
59 arm_breakpoint_count++;
62 gboolean arm_clear_breakpoint( uint32_t pc, int type )
66 for( i=0; i<arm_breakpoint_count; i++ ) {
67 if( arm_breakpoints[i].address == pc &&
68 arm_breakpoints[i].type == type ) {
69 while( ++i < arm_breakpoint_count ) {
70 arm_breakpoints[i-1].address = arm_breakpoints[i].address;
71 arm_breakpoints[i-1].type = arm_breakpoints[i].type;
73 arm_breakpoint_count--;
80 int arm_get_breakpoint( uint32_t pc )
83 for( i=0; i<arm_breakpoint_count; i++ ) {
84 if( arm_breakpoints[i].address == pc )
85 return arm_breakpoints[i].type;
90 uint32_t arm_run_slice( uint32_t num_samples )
97 for( i=0; i<num_samples; i++ ) {
98 for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {
100 if( !arm_execute_instruction() )
102 #ifdef ENABLE_DEBUG_MODE
103 for( k=0; k<arm_breakpoint_count; k++ ) {
104 if( arm_breakpoints[k].address == armr.r[15] ) {
106 if( arm_breakpoints[k].type == BREAK_ONESHOT )
107 arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );
114 k = MMIO_READ( AICA2, AICA_TCR );
116 uint8_t val = MMIO_READ( AICA2, AICA_TIMER );
119 aica_event( AICA_EVENT_TIMER );
120 MMIO_WRITE( AICA2, AICA_TCR, k & ~0x40 );
122 MMIO_WRITE( AICA2, AICA_TIMER, val );
124 if( !dreamcast_is_running() )
131 void arm_save_state( FILE *f )
133 fwrite( &armr, sizeof(armr), 1, f );
136 int arm_load_state( FILE *f )
138 fread( &armr, sizeof(armr), 1, f );
143 void arm_reset( void )
145 /* Wipe all processor state */
146 memset( &armr, 0, sizeof(armr) );
148 armr.cpsr = MODE_SVC | CPSR_I | CPSR_F;
149 armr.r[15] = 0x00000000;
153 #define SET_CPSR_CONTROL 0x00010000
154 #define SET_CPSR_EXTENSION 0x00020000
155 #define SET_CPSR_STATUS 0x00040000
156 #define SET_CPSR_FLAGS 0x00080000
158 uint32_t arm_get_cpsr( void )
160 /* write back all flags to the cpsr */
161 armr.cpsr = armr.cpsr & CPSR_COMPACT_MASK;
162 if( armr.n ) armr.cpsr |= CPSR_N;
163 if( armr.z ) armr.cpsr |= CPSR_Z;
164 if( armr.c ) armr.cpsr |= CPSR_C;
165 if( armr.v ) armr.cpsr |= CPSR_V;
166 if( armr.t ) armr.cpsr |= CPSR_T;
171 * Return a pointer to the specified register in the user bank,
172 * regardless of the active bank
174 static uint32_t *arm_user_reg( int reg )
176 if( IS_EXCEPTION_MODE() ) {
177 if( reg == 13 || reg == 14 )
178 return &armr.user_r[reg-8];
179 if( IS_FIQ_MODE() ) {
180 if( reg >= 8 || reg <= 12 )
181 return &armr.user_r[reg-8];
187 #define USER_R(n) *arm_user_reg(n)
190 * Set the CPSR to the specified value.
192 * @param value values to set in CPSR
193 * @param fields set of mask values to define which sections of the
194 * CPSR to set (one of the SET_CPSR_* values above)
196 void arm_set_cpsr( uint32_t value, uint32_t fields )
198 if( IS_PRIVILEGED_MODE() ) {
199 if( fields & SET_CPSR_CONTROL ) {
200 int mode = value & CPSR_MODE;
201 arm_set_mode( mode );
202 armr.t = ( value & CPSR_T ); /* Technically illegal to change */
203 armr.cpsr = (armr.cpsr & 0xFFFFFF00) | (value & 0x000000FF);
206 /* Middle 16 bits not currently defined */
208 if( fields & SET_CPSR_FLAGS ) {
209 /* Break flags directly out of given value - don't bother writing
212 armr.n = ( value & CPSR_N );
213 armr.z = ( value & CPSR_Z );
214 armr.c = ( value & CPSR_C );
215 armr.v = ( value & CPSR_V );
219 void arm_set_spsr( uint32_t value, uint32_t fields )
221 /* Only defined if we actually have an SPSR register */
222 if( IS_EXCEPTION_MODE() ) {
223 if( fields & SET_CPSR_CONTROL ) {
224 armr.spsr = (armr.spsr & 0xFFFFFF00) | (value & 0x000000FF);
227 /* Middle 16 bits not currently defined */
229 if( fields & SET_CPSR_FLAGS ) {
230 armr.spsr = (armr.spsr & 0x00FFFFFF) | (value & 0xFF000000);
236 * Raise an ARM exception (other than reset, which uses arm_reset().
237 * @param exception one of the EXC_* exception codes defined above.
239 void arm_raise_exception( int exception )
241 int mode = arm_exceptions[exception][0];
242 uint32_t spsr = arm_get_cpsr();
243 arm_set_mode( mode );
245 armr.r[14] = armr.r[15] + 4;
246 armr.cpsr = (spsr & 0xFFFFFF00) | mode | CPSR_I;
247 if( mode == MODE_FIQ )
249 armr.r[15] = arm_exceptions[exception][1];
252 void arm_restore_cpsr( void )
254 int spsr = armr.spsr;
255 int mode = spsr & CPSR_MODE;
256 arm_set_mode( mode );
258 armr.n = ( spsr & CPSR_N );
259 armr.z = ( spsr & CPSR_Z );
260 armr.c = ( spsr & CPSR_C );
261 armr.v = ( spsr & CPSR_V );
262 armr.t = ( spsr & CPSR_T );
268 * Change the current executing ARM mode to the requested mode.
269 * Saves any required registers to banks and restores those for the
270 * correct mode. (Note does not actually update CPSR at the moment).
272 void arm_set_mode( int targetMode )
274 int currentMode = armr.cpsr & CPSR_MODE;
275 if( currentMode == targetMode )
278 switch( currentMode ) {
281 armr.user_r[5] = armr.r[13];
282 armr.user_r[6] = armr.r[14];
285 armr.svc_r[0] = armr.r[13];
286 armr.svc_r[1] = armr.r[14];
287 armr.svc_r[2] = armr.spsr;
290 armr.abt_r[0] = armr.r[13];
291 armr.abt_r[1] = armr.r[14];
292 armr.abt_r[2] = armr.spsr;
295 armr.und_r[0] = armr.r[13];
296 armr.und_r[1] = armr.r[14];
297 armr.und_r[2] = armr.spsr;
300 armr.irq_r[0] = armr.r[13];
301 armr.irq_r[1] = armr.r[14];
302 armr.irq_r[2] = armr.spsr;
305 armr.fiq_r[0] = armr.r[8];
306 armr.fiq_r[1] = armr.r[9];
307 armr.fiq_r[2] = armr.r[10];
308 armr.fiq_r[3] = armr.r[11];
309 armr.fiq_r[4] = armr.r[12];
310 armr.fiq_r[5] = armr.r[13];
311 armr.fiq_r[6] = armr.r[14];
312 armr.fiq_r[7] = armr.spsr;
313 armr.r[8] = armr.user_r[0];
314 armr.r[9] = armr.user_r[1];
315 armr.r[10] = armr.user_r[2];
316 armr.r[11] = armr.user_r[3];
317 armr.r[12] = armr.user_r[4];
321 switch( targetMode ) {
324 armr.r[13] = armr.user_r[5];
325 armr.r[14] = armr.user_r[6];
328 armr.r[13] = armr.svc_r[0];
329 armr.r[14] = armr.svc_r[1];
330 armr.spsr = armr.svc_r[2];
333 armr.r[13] = armr.abt_r[0];
334 armr.r[14] = armr.abt_r[1];
335 armr.spsr = armr.abt_r[2];
338 armr.r[13] = armr.und_r[0];
339 armr.r[14] = armr.und_r[1];
340 armr.spsr = armr.und_r[2];
343 armr.r[13] = armr.irq_r[0];
344 armr.r[14] = armr.irq_r[1];
345 armr.spsr = armr.irq_r[2];
348 armr.user_r[0] = armr.r[8];
349 armr.user_r[1] = armr.r[9];
350 armr.user_r[2] = armr.r[10];
351 armr.user_r[3] = armr.r[11];
352 armr.user_r[4] = armr.r[12];
353 armr.r[8] = armr.fiq_r[0];
354 armr.r[9] = armr.fiq_r[1];
355 armr.r[10] = armr.fiq_r[2];
356 armr.r[11] = armr.fiq_r[3];
357 armr.r[12] = armr.fiq_r[4];
358 armr.r[13] = armr.fiq_r[5];
359 armr.r[14] = armr.fiq_r[6];
360 armr.spsr = armr.fiq_r[7];
365 /* Page references are as per ARM DDI 0100E (June 2000) */
367 #define MEM_READ_BYTE( addr ) arm_read_byte(addr)
368 #define MEM_READ_WORD( addr ) arm_read_word(addr)
369 #define MEM_READ_LONG( addr ) arm_read_long(addr)
370 #define MEM_WRITE_BYTE( addr, val ) arm_write_byte(addr, val)
371 #define MEM_WRITE_WORD( addr, val ) arm_write_word(addr, val)
372 #define MEM_WRITE_LONG( addr, val ) arm_write_long(addr, val)
375 #define IS_NOTBORROW( result, op1, op2 ) (op2 > op1 ? 0 : 1)
376 #define IS_CARRY( result, op1, op2 ) (result < op1 ? 1 : 0)
377 #define IS_SUBOVERFLOW( result, op1, op2 ) (((op1^op2) & (result^op1)) >> 31)
378 #define IS_ADDOVERFLOW( result, op1, op2 ) (((op1&op2) & (result^op1)) >> 31)
380 #define PC armr.r[15]
382 /* Instruction fields */
383 #define COND(ir) (ir>>28)
384 #define GRP(ir) ((ir>>26)&0x03)
385 #define OPCODE(ir) ((ir>>20)&0x1F)
386 #define IFLAG(ir) (ir&0x02000000)
387 #define SFLAG(ir) (ir&0x00100000)
388 #define PFLAG(ir) (ir&0x01000000)
389 #define UFLAG(ir) (ir&0x00800000)
390 #define BFLAG(ir) (ir&0x00400000)
391 #define WFLAG(ir) (ir&0x00200000)
392 #define LFLAG(ir) SFLAG(ir)
393 #define RN(ir) (armr.r[((ir>>16)&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0))
394 #define RD(ir) (armr.r[((ir>>12)&0x0F)] + (((ir>>12)&0x0F) == 0x0F ? 4 : 0))
395 #define RDn(ir) ((ir>>12)&0x0F)
396 #define RS(ir) (armr.r[((ir>>8)&0x0F)] + (((ir>>8)&0x0F) == 0x0F ? 4 : 0))
397 #define RM(ir) (armr.r[(ir&0x0F)] + (((ir&0x0F) == 0x0F ? 4 : 0)) )
398 #define LRN(ir) armr.r[((ir>>16)&0x0F)]
399 #define LRD(ir) armr.r[((ir>>12)&0x0F)]
400 #define LRS(ir) armr.r[((ir>>8)&0x0F)]
401 #define LRM(ir) armr.r[(ir&0x0F)]
403 #define IMM8(ir) (ir&0xFF)
404 #define IMM12(ir) (ir&0xFFF)
405 #define SHIFTIMM(ir) ((ir>>7)&0x1F)
406 #define IMMROT(ir) ((ir>>7)&0x1E)
407 #define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
408 #define SIGNEXT24(n) ((n&0x00800000) ? (n|0xFF000000) : (n&0x00FFFFFF))
409 #define SHIFT(ir) ((ir>>4)&0x07)
410 #define DISP24(ir) ((ir&0x00FFFFFF))
411 #define UNDEF(ir) do{ arm_raise_exception( EXC_UNDEFINED ); return TRUE; } while(0)
412 #define UNIMP(ir) do{ PC-=4; ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); dreamcast_stop(); return FALSE; }while(0)
415 * Determine the value of the shift-operand for a data processing instruction,
416 * without determing a value for shift_C (optimized form for instructions that
417 * don't require shift_C ).
418 * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
420 static uint32_t arm_get_shift_operand( uint32_t ir )
422 uint32_t operand, tmp;
423 if( IFLAG(ir) == 0 ) {
426 case 0: /* (Rm << imm) */
427 operand = operand << SHIFTIMM(ir);
429 case 1: /* (Rm << Rs) */
431 if( tmp > 31 ) operand = 0;
432 else operand = operand << tmp;
434 case 2: /* (Rm >> imm) */
435 operand = operand >> SHIFTIMM(ir);
437 case 3: /* (Rm >> Rs) */
439 if( tmp > 31 ) operand = 0;
440 else operand = operand >> ir;
442 case 4: /* (Rm >>> imm) */
444 if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
445 else operand = ((int32_t)operand) >> tmp;
447 case 5: /* (Rm >>> Rs) */
449 if( tmp > 31 ) operand = ((int32_t)operand) >> 31;
450 else operand = ((int32_t)operand) >> tmp;
454 if( tmp == 0 ) /* RRX aka rotate with carry */
455 operand = (operand >> 1) | (armr.c<<31);
457 operand = ROTATE_RIGHT_LONG(operand,tmp);
461 operand = ROTATE_RIGHT_LONG(operand,tmp);
467 operand = ROTATE_RIGHT_LONG(operand, tmp);
473 * Determine the value of the shift-operand for a data processing instruction,
474 * and set armr.shift_c accordingly.
475 * @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
477 static uint32_t arm_get_shift_operand_s( uint32_t ir )
479 uint32_t operand, tmp;
480 if( IFLAG(ir) == 0 ) {
483 case 0: /* (Rm << imm) */
485 if( tmp == 0 ) { /* Rm */
486 armr.shift_c = armr.c;
487 } else { /* Rm << imm */
488 armr.shift_c = (operand >> (32-tmp)) & 0x01;
489 operand = operand << tmp;
492 case 1: /* (Rm << Rs) */
495 armr.shift_c = armr.c;
498 armr.shift_c = (operand >> (32-tmp)) & 0x01;
499 else armr.shift_c = 0;
501 operand = operand << tmp;
505 case 2: /* (Rm >> imm) */
508 armr.shift_c = operand >> 31;
511 armr.shift_c = (operand >> (tmp-1)) & 0x01;
512 operand = RM(ir) >> tmp;
515 case 3: /* (Rm >> Rs) */
518 armr.shift_c = armr.c;
521 armr.shift_c = (operand >> (tmp-1))&0x01;
522 else armr.shift_c = 0;
524 operand = operand >> tmp;
528 case 4: /* (Rm >>> imm) */
531 armr.shift_c = operand >> 31;
532 operand = -armr.shift_c;
534 armr.shift_c = (operand >> (tmp-1)) & 0x01;
535 operand = ((int32_t)operand) >> tmp;
538 case 5: /* (Rm >>> Rs) */
541 armr.shift_c = armr.c;
544 armr.shift_c = (operand >> (tmp-1))&0x01;
545 operand = ((int32_t)operand) >> tmp;
547 armr.shift_c = operand >> 31;
548 operand = ((int32_t)operand) >> 31;
554 if( tmp == 0 ) { /* RRX aka rotate with carry */
555 armr.shift_c = operand&0x01;
556 operand = (operand >> 1) | (armr.c<<31);
558 armr.shift_c = operand>>(tmp-1);
559 operand = ROTATE_RIGHT_LONG(operand,tmp);
565 armr.shift_c = armr.c;
569 armr.shift_c = operand>>31;
571 armr.shift_c = (operand>>(tmp-1))&0x1;
572 operand = ROTATE_RIGHT_LONG(operand,tmp);
581 armr.shift_c = armr.c;
583 operand = ROTATE_RIGHT_LONG(operand, tmp);
584 armr.shift_c = operand>>31;
591 * Another variant of the shifter code for index-based memory addressing.
592 * Distinguished by the fact that it doesn't support register shifts, and
593 * ignores the I flag (WTF do the load/store instructions use the I flag to
594 * mean the _exact opposite_ of what it means for the data processing
597 static uint32_t arm_get_address_index( uint32_t ir )
599 uint32_t operand = RM(ir);
603 case 0: /* (Rm << imm) */
604 operand = operand << SHIFTIMM(ir);
606 case 2: /* (Rm >> imm) */
607 operand = operand >> SHIFTIMM(ir);
609 case 4: /* (Rm >>> imm) */
611 if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
612 else operand = ((int32_t)operand) >> tmp;
616 if( tmp == 0 ) /* RRX aka rotate with carry */
617 operand = (operand >> 1) | (armr.c<<31);
619 operand = ROTATE_RIGHT_LONG(operand,tmp);
627 * Determine the address operand of a load/store instruction, including
628 * applying any pre/post adjustments to the address registers.
629 * @see s5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte
630 * @param The instruction word.
631 * @return The calculated address
633 static uint32_t arm_get_address_operand( uint32_t ir )
638 switch( (ir>>21)&0x1D ) {
639 case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
642 LRN(ir) = addr - IMM12(ir);
644 case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */
647 LRN(ir) = addr + IMM12(ir);
649 case 8: /* Rn - imm offset [5.2.2 A5-20] */
650 addr = RN(ir) - IMM12(ir);
652 case 9: /* Rn -= imm offset (pre-indexed) [5.2.5 A5-24] */
653 addr = RN(ir) - IMM12(ir);
656 case 12: /* Rn + imm offset [5.2.2 A5-20] */
657 addr = RN(ir) + IMM12(ir);
659 case 13: /* Rn += imm offset [5.2.5 A5-24 ] */
660 addr = RN(ir) + IMM12(ir);
663 case 16: /* Rn -= Rm (post-indexed) [5.2.10 A5-32 ] */
666 LRN(ir) = addr - arm_get_address_index(ir);
668 case 20: /* Rn += Rm (post-indexed) [5.2.10 A5-32 ] */
671 LRN(ir) = addr - arm_get_address_index(ir);
673 case 24: /* Rn - Rm [5.2.4 A5-23] */
674 addr = RN(ir) - arm_get_address_index(ir);
676 case 25: /* RN -= Rm (pre-indexed) [5.2.7 A5-26] */
677 addr = RN(ir) - arm_get_address_index(ir);
680 case 28: /* Rn + Rm [5.2.4 A5-23] */
681 addr = RN(ir) + arm_get_address_index(ir);
683 case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */
684 addr = RN(ir) + arm_get_address_index(ir);
691 gboolean arm_execute_instruction( void )
695 uint32_t operand, operand2, tmp, tmp2, cond;
698 tmp = armr.int_pending & (~armr.cpsr);
701 arm_raise_exception( EXC_FAST_IRQ );
703 arm_raise_exception( EXC_IRQ );
707 ir = MEM_READ_LONG(PC);
712 * Check the condition bits first - if the condition fails return
713 * immediately without actually looking at the rest of the instruction.
741 cond = armr.c && !armr.z;
744 cond = (!armr.c) || armr.z;
747 cond = (armr.n == armr.v);
750 cond = (armr.n != armr.v);
753 cond = (!armr.z) && (armr.n == armr.v);
756 cond = armr.z || (armr.n != armr.v);
768 * Condition passed, now for the actual instructions...
772 if( (ir & 0x0D900000) == 0x01000000 ) {
773 /* Instructions that aren't actual data processing even though
774 * they sit in the DP instruction block.
776 switch( ir & 0x0FF000F0 ) {
777 case 0x01200010: /* BX Rd */
779 armr.r[15] = RM(ir) & 0xFFFFFFFE;
781 case 0x01000000: /* MRS Rd, CPSR */
782 LRD(ir) = arm_get_cpsr();
784 case 0x01400000: /* MRS Rd, SPSR */
787 case 0x01200000: /* MSR CPSR, Rd */
788 arm_set_cpsr( RM(ir), ir );
790 case 0x01600000: /* MSR SPSR, Rd */
791 arm_set_spsr( RM(ir), ir );
793 case 0x03200000: /* MSR CPSR, imm */
794 arm_set_cpsr( ROTIMM12(ir), ir );
796 case 0x03600000: /* MSR SPSR, imm */
797 arm_set_spsr( ROTIMM12(ir), ir );
802 } else if( (ir & 0x0E000090) == 0x00000090 ) {
803 /* Neither are these */
804 switch( (ir>>5)&0x03 ) {
806 /* Arithmetic extension area */
809 LRN(ir) = RM(ir) * RS(ir);
812 tmp = RM(ir) * RS(ir);
818 LRN(ir) = RM(ir) * RS(ir) + RD(ir);
821 tmp = RM(ir) * RS(ir) + RD(ir);
829 case 11: /* UMLALS */
831 case 13: /* SMULLS */
833 case 15: /* SMLALS */
837 tmp = arm_read_long( RN(ir) );
838 switch( RN(ir) & 0x03 ) {
840 tmp = ROTATE_RIGHT_LONG(tmp, 8);
843 tmp = ROTATE_RIGHT_LONG(tmp, 16);
846 tmp = ROTATE_RIGHT_LONG(tmp, 24);
849 arm_write_long( RN(ir), RM(ir) );
853 tmp = arm_read_byte( RN(ir) );
854 arm_write_byte( RN(ir), RM(ir) );
885 /* Data processing */
888 case 0: /* AND Rd, Rn, operand */
889 LRD(ir) = RN(ir) & arm_get_shift_operand(ir);
891 case 1: /* ANDS Rd, Rn, operand */
892 operand = arm_get_shift_operand_s(ir) & RN(ir);
894 if( RDn(ir) == 15 ) {
897 armr.n = operand>>31;
898 armr.z = (operand == 0);
899 armr.c = armr.shift_c;
902 case 2: /* EOR Rd, Rn, operand */
903 LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
905 case 3: /* EORS Rd, Rn, operand */
906 operand = arm_get_shift_operand_s(ir) ^ RN(ir);
908 if( RDn(ir) == 15 ) {
911 armr.n = operand>>31;
912 armr.z = (operand == 0);
913 armr.c = armr.shift_c;
916 case 4: /* SUB Rd, Rn, operand */
917 LRD(ir) = RN(ir) - arm_get_shift_operand(ir);
919 case 5: /* SUBS Rd, Rn, operand */
921 operand2 = arm_get_shift_operand(ir);
922 tmp = operand - operand2;
924 if( RDn(ir) == 15 ) {
929 armr.c = IS_NOTBORROW(tmp,operand,operand2);
930 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
933 case 6: /* RSB Rd, operand, Rn */
934 LRD(ir) = arm_get_shift_operand(ir) - RN(ir);
936 case 7: /* RSBS Rd, operand, Rn */
937 operand = arm_get_shift_operand(ir);
939 tmp = operand - operand2;
941 if( RDn(ir) == 15 ) {
946 armr.c = IS_NOTBORROW(tmp,operand,operand2);
947 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
950 case 8: /* ADD Rd, Rn, operand */
951 LRD(ir) = RN(ir) + arm_get_shift_operand(ir);
953 case 9: /* ADDS Rd, Rn, operand */
954 operand = arm_get_shift_operand(ir);
956 tmp = operand + operand2;
958 if( RDn(ir) == 15 ) {
963 armr.c = IS_CARRY(tmp,operand,operand2);
964 armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
968 LRD(ir) = RN(ir) + arm_get_shift_operand(ir) +
972 operand = arm_get_shift_operand(ir);
974 tmp = operand + operand2;
975 tmp2 = tmp + armr.c ? 1 : 0;
977 if( RDn(ir) == 15 ) {
981 armr.z = (tmp == 0 );
982 armr.c = IS_CARRY(tmp,operand,operand2) ||
984 armr.v = IS_ADDOVERFLOW(tmp,operand, operand2) ||
985 ((tmp&0x80000000) != (tmp2&0x80000000));
989 LRD(ir) = RN(ir) - arm_get_shift_operand(ir) -
994 operand2 = arm_get_shift_operand(ir);
995 tmp = operand - operand2;
996 tmp2 = tmp - (armr.c ? 0 : 1);
997 if( RDn(ir) == 15 ) {
1001 armr.z = (tmp == 0 );
1002 armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
1004 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
1005 ((tmp&0x80000000) != (tmp2&0x80000000));
1009 LRD(ir) = arm_get_shift_operand(ir) - RN(ir) -
1013 operand = arm_get_shift_operand(ir);
1015 tmp = operand - operand2;
1016 tmp2 = tmp - (armr.c ? 0 : 1);
1017 if( RDn(ir) == 15 ) {
1021 armr.z = (tmp == 0 );
1022 armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
1024 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
1025 ((tmp&0x80000000) != (tmp2&0x80000000));
1028 case 17: /* TST Rn, operand */
1029 operand = arm_get_shift_operand_s(ir) & RN(ir);
1030 armr.n = operand>>31;
1031 armr.z = (operand == 0);
1032 armr.c = armr.shift_c;
1034 case 19: /* TEQ Rn, operand */
1035 operand = arm_get_shift_operand_s(ir) ^ RN(ir);
1036 armr.n = operand>>31;
1037 armr.z = (operand == 0);
1038 armr.c = armr.shift_c;
1040 case 21: /* CMP Rn, operand */
1042 operand2 = arm_get_shift_operand(ir);
1043 tmp = operand - operand2;
1045 armr.z = (tmp == 0);
1046 armr.c = IS_NOTBORROW(tmp,operand,operand2);
1047 armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
1049 case 23: /* CMN Rn, operand */
1051 operand2 = arm_get_shift_operand(ir);
1052 tmp = operand + operand2;
1054 armr.z = (tmp == 0);
1055 armr.c = IS_CARRY(tmp,operand,operand2);
1056 armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
1058 case 24: /* ORR Rd, Rn, operand */
1059 LRD(ir) = RN(ir) | arm_get_shift_operand(ir);
1061 case 25: /* ORRS Rd, Rn, operand */
1062 operand = arm_get_shift_operand_s(ir) | RN(ir);
1064 if( RDn(ir) == 15 ) {
1067 armr.n = operand>>31;
1068 armr.z = (operand == 0);
1069 armr.c = armr.shift_c;
1072 case 26: /* MOV Rd, operand */
1073 LRD(ir) = arm_get_shift_operand(ir);
1075 case 27: /* MOVS Rd, operand */
1076 operand = arm_get_shift_operand_s(ir);
1078 if( RDn(ir) == 15 ) {
1081 armr.n = operand>>31;
1082 armr.z = (operand == 0);
1083 armr.c = armr.shift_c;
1086 case 28: /* BIC Rd, Rn, operand */
1087 LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
1089 case 29: /* BICS Rd, Rn, operand */
1090 operand = RN(ir) & (~arm_get_shift_operand_s(ir));
1092 if( RDn(ir) == 15 ) {
1095 armr.n = operand>>31;
1096 armr.z = (operand == 0);
1097 armr.c = armr.shift_c;
1100 case 30: /* MVN Rd, operand */
1101 LRD(ir) = ~arm_get_shift_operand(ir);
1103 case 31: /* MVNS Rd, operand */
1104 operand = ~arm_get_shift_operand_s(ir);
1106 if( RDn(ir) == 15 ) {
1109 armr.n = operand>>31;
1110 armr.z = (operand == 0);
1111 armr.c = armr.shift_c;
1119 case 1: /* Load/store */
1120 operand = arm_get_address_operand(ir);
1121 switch( (ir>>20)&0x17 ) {
1122 case 0: case 16: case 18: /* STR Rd, address */
1123 arm_write_long( operand, RD(ir) );
1125 case 1: case 17: case 19: /* LDR Rd, address */
1126 LRD(ir) = arm_read_long(operand);
1128 case 2: /* STRT Rd, address */
1129 arm_write_long_user( operand, RD(ir) );
1131 case 3: /* LDRT Rd, address */
1132 LRD(ir) = arm_read_long_user( operand );
1134 case 4: case 20: case 22: /* STRB Rd, address */
1135 arm_write_byte( operand, RD(ir) );
1137 case 5: case 21: case 23: /* LDRB Rd, address */
1138 LRD(ir) = arm_read_byte( operand );
1140 case 6: /* STRBT Rd, address */
1141 arm_write_byte_user( operand, RD(ir) );
1143 case 7: /* LDRBT Rd, address */
1144 LRD(ir) = arm_read_byte_user( operand );
1148 case 2: /* Load/store multiple, branch*/
1149 if( (ir & 0x02000000) == 0x02000000 ) { /* B[L] imm24 */
1150 operand = (SIGNEXT24(ir&0x00FFFFFF) << 2);
1151 if( (ir & 0x01000000) == 0x01000000 ) {
1152 armr.r[14] = pc; /* BL */
1154 armr.r[15] = pc + 4 + operand;
1155 } else { /* Load/store multiple */
1156 gboolean needRestore = FALSE;
1159 switch( (ir & 0x01D00000) >> 20 ) {
1162 arm_write_long( operand, armr.r[15]+4 );
1165 for( i=14; i>= 0; i-- ) {
1166 if( (ir & (1<<i)) ) {
1167 arm_write_long( operand, armr.r[i] );
1173 for( i=15; i>= 0; i-- ) {
1174 if( (ir & (1<<i)) ) {
1175 armr.r[i] = arm_read_long( operand );
1180 case 4: /* STMDA (S) */
1182 arm_write_long( operand, armr.r[15]+4 );
1185 for( i=14; i>= 0; i-- ) {
1186 if( (ir & (1<<i)) ) {
1187 arm_write_long( operand, USER_R(i) );
1192 case 5: /* LDMDA (S) */
1193 if( (ir&0x00008000) ) { /* Load PC */
1194 for( i=15; i>= 0; i-- ) {
1195 if( (ir & (1<<i)) ) {
1196 armr.r[i] = arm_read_long( operand );
1202 for( i=15; i>= 0; i-- ) {
1203 if( (ir & (1<<i)) ) {
1204 USER_R(i) = arm_read_long( operand );
1211 for( i=0; i< 15; i++ ) {
1212 if( (ir & (1<<i)) ) {
1213 arm_write_long( operand, armr.r[i] );
1218 arm_write_long( operand, armr.r[15]+4 );
1223 for( i=0; i< 16; i++ ) {
1224 if( (ir & (1<<i)) ) {
1225 armr.r[i] = arm_read_long( operand );
1230 case 12: /* STMIA (S) */
1231 for( i=0; i< 15; i++ ) {
1232 if( (ir & (1<<i)) ) {
1233 arm_write_long( operand, USER_R(i) );
1238 arm_write_long( operand, armr.r[15]+4 );
1242 case 13: /* LDMIA (S) */
1243 if( (ir&0x00008000) ) { /* Load PC */
1244 for( i=0; i < 16; i++ ) {
1245 if( (ir & (1<<i)) ) {
1246 armr.r[i] = arm_read_long( operand );
1252 for( i=0; i < 16; i++ ) {
1253 if( (ir & (1<<i)) ) {
1254 USER_R(i) = arm_read_long( operand );
1260 case 16: /* STMDB */
1263 arm_write_long( operand, armr.r[15]+4 );
1265 for( i=14; i>= 0; i-- ) {
1266 if( (ir & (1<<i)) ) {
1268 arm_write_long( operand, armr.r[i] );
1272 case 17: /* LDMDB */
1273 for( i=15; i>= 0; i-- ) {
1274 if( (ir & (1<<i)) ) {
1276 armr.r[i] = arm_read_long( operand );
1280 case 20: /* STMDB (S) */
1283 arm_write_long( operand, armr.r[15]+4 );
1285 for( i=14; i>= 0; i-- ) {
1286 if( (ir & (1<<i)) ) {
1288 arm_write_long( operand, USER_R(i) );
1292 case 21: /* LDMDB (S) */
1293 if( (ir&0x00008000) ) { /* Load PC */
1294 for( i=15; i>= 0; i-- ) {
1295 if( (ir & (1<<i)) ) {
1297 armr.r[i] = arm_read_long( operand );
1302 for( i=15; i>= 0; i-- ) {
1303 if( (ir & (1<<i)) ) {
1305 USER_R(i) = arm_read_long( operand );
1310 case 24: /* STMIB */
1311 for( i=0; i< 15; i++ ) {
1312 if( (ir & (1<<i)) ) {
1314 arm_write_long( operand, armr.r[i] );
1319 arm_write_long( operand, armr.r[15]+4 );
1322 case 25: /* LDMIB */
1323 for( i=0; i< 16; i++ ) {
1324 if( (ir & (1<<i)) ) {
1326 armr.r[i] = arm_read_long( operand );
1330 case 28: /* STMIB (S) */
1331 for( i=0; i< 15; i++ ) {
1332 if( (ir & (1<<i)) ) {
1334 arm_write_long( operand, USER_R(i) );
1339 arm_write_long( operand, armr.r[15]+4 );
1342 case 29: /* LDMIB (S) */
1343 if( (ir&0x00008000) ) { /* Load PC */
1344 for( i=0; i < 16; i++ ) {
1345 if( (ir & (1<<i)) ) {
1347 armr.r[i] = arm_read_long( operand );
1352 for( i=0; i < 16; i++ ) {
1353 if( (ir & (1<<i)) ) {
1355 USER_R(i) = arm_read_long( operand );
1369 if( (ir & 0x0F000000) == 0x0F000000 ) { /* SWI */
1370 arm_raise_exception( EXC_SOFTWARE );
1379 if( armr.r[15] >= 0x00200000 ) {
1380 armr.running = FALSE;
1381 ERROR( "ARM Halted: BRANCH to invalid address %08X at %08X", armr.r[15], pc );
.