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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 1291:8884bf45f010
prev1282:9f445c5e252b
author nkeynes
date Sat Aug 04 08:46:28 2012 +1000 (10 years ago)
permissions -rw-r--r--
last change Handle corner case in pvr2_run_slice when we've previously slightly overrun
the end of the time slice
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     1 /**
     2  * $Id$
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include <assert.h>
    21 #include "dream.h"
    22 #include "eventq.h"
    23 #include "display.h"
    24 #include "mem.h"
    25 #include "asic.h"
    26 #include "clock.h"
    27 #include "pvr2/pvr2.h"
    28 #include "pvr2/pvr2mmio.h"
    29 #include "pvr2/scene.h"
    30 #include "sh4/sh4.h"
    31 #define MMIO_IMPL
    32 #include "pvr2/pvr2mmio.h"
    34 #define MAX_RENDER_BUFFERS 4
    36 #define HPOS_PER_FRAME 0
    37 #define HPOS_PER_LINECOUNT 1
    39 static void pvr2_init( void );
    40 static void pvr2_reset( void );
    41 static uint32_t pvr2_run_slice( uint32_t );
    42 static void pvr2_save_state( FILE *f );
    43 static int pvr2_load_state( FILE *f );
    44 static void pvr2_update_raster_posn( uint32_t nanosecs );
    45 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
    46 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
    47 static render_buffer_t pvr2_next_render_buffer( );
    48 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
    49 static frame_buffer_t pvr2_render_buffer_to_frame_buffer( render_buffer_t frame );
    50 uint32_t pvr2_get_sync_status();
    51 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
    52 static int render_colour_formats[8] = {
    53         COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
    54         COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
    57 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    58         pvr2_run_slice, NULL,
    59         pvr2_save_state, pvr2_load_state };
    62 display_driver_t display_driver = NULL;
    64 struct pvr2_state {
    65     uint32_t frame_count;
    66     uint32_t line_count;
    67     uint32_t line_remainder;
    68     uint32_t cycles_run; /* Cycles already executed prior to main time slice */
    69     uint32_t irq_hpos_line;
    70     uint32_t irq_hpos_line_count;
    71     uint32_t irq_hpos_mode;
    72     uint32_t irq_hpos_time_ns; /* Time within the line */
    73     uint32_t irq_vpos1;
    74     uint32_t irq_vpos2;
    75     uint32_t odd_even_field; /* 1 = odd, 0 = even */
    76     int32_t palette_changed; /* TRUE if palette has changed since last render */
    77     /* timing */
    78     uint32_t dot_clock;
    79     uint32_t total_lines;
    80     uint32_t line_size;
    81     uint32_t line_time_ns;
    82     uint32_t vsync_lines;
    83     uint32_t hsync_width_ns;
    84     uint32_t front_porch_ns;
    85     uint32_t back_porch_ns;
    86     uint32_t retrace_start_line;
    87     uint32_t retrace_end_line;
    88     int32_t interlaced;
    89 } pvr2_state;
    91 static gchar *save_next_render_filename;
    92 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
    93 static uint32_t render_buffer_count = 0;
    94 static render_buffer_t displayed_render_buffer = NULL;
    95 static uint32_t displayed_border_colour = 0;
    97 /**
    98  * Event handler for the hpos callback
    99  */
   100 static void pvr2_hpos_callback( int eventid ) {
   101     asic_event( eventid );
   102     pvr2_update_raster_posn(sh4r.slice_cycle);
   103     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
   104         pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
   105         while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   106             pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   107         }
   108     }
   109     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
   110                                   pvr2_state.irq_hpos_time_ns );
   111 }
   113 /**
   114  * Event handler for the scanline callbacks. Fires the corresponding
   115  * ASIC event, and resets the timer for the next field.
   116  */
   117 static void pvr2_scanline_callback( int eventid ) 
   118 {
   119     asic_event( eventid );
   120     pvr2_update_raster_posn(sh4r.slice_cycle);
   121     if( eventid == EVENT_SCANLINE1 ) {
   122         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
   123     } else {
   124         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
   125     }
   126 }
   128 static void pvr2_gunpos_callback( int eventid ) 
   129 {
   130     pvr2_update_raster_posn(sh4r.slice_cycle);
   131     int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
   132     MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
   133     asic_event( EVENT_MAPLE_DMA );
   134 }
   136 static void pvr2_init( void )
   137 {
   138     int i;
   139     register_io_region( &mmio_region_PVR2 );
   140     register_io_region( &mmio_region_PVR2PAL );
   141     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
   142     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   143     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   144     register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
   145     texcache_init();
   146     pvr2_reset();
   147     pvr2_ta_reset();
   148     save_next_render_filename = NULL;
   149     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
   150         render_buffers[i] = NULL;
   151     }
   152     render_buffer_count = 0;
   153     displayed_render_buffer = NULL;
   154     displayed_border_colour = 0;
   155 }
   157 static void pvr2_reset( void )
   158 {
   159     int i;
   160     pvr2_state.line_count = 0;
   161     pvr2_state.line_remainder = 0;
   162     pvr2_state.cycles_run = 0;
   163     pvr2_state.irq_vpos1 = 0;
   164     pvr2_state.irq_vpos2 = 0;
   165     pvr2_state.dot_clock = PVR2_DOT_CLOCK;
   166     pvr2_state.back_porch_ns = 4000;
   167     pvr2_state.palette_changed = FALSE;
   168     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
   169     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
   170     mmio_region_PVR2_write( YUV_ADDR, 0 );
   171     mmio_region_PVR2_write( YUV_CFG, 0 );
   173     pvr2_ta_init();
   174     texcache_flush();
   175     if( display_driver ) {
   176         display_driver->display_blank(0);
   177         for( i=0; i<render_buffer_count; i++ ) {
   178             display_driver->destroy_render_buffer(render_buffers[i]);
   179             render_buffers[i] = NULL;
   180         }
   181         render_buffer_count = 0;
   182     }
   183 }
   185 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
   186 {
   187     struct frame_buffer fbuf;
   189     fbuf.width = buffer->width;
   190     fbuf.height = buffer->height;
   191     fbuf.rowstride = fbuf.width*3;
   192     fbuf.colour_format = COLFMT_BGR888;
   193     fbuf.inverted = buffer->inverted;
   194     fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
   196     display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
   197     write_png_to_stream( f, &fbuf );
   198     g_free( fbuf.data );
   200     fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   201     fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   202     fwrite( &buffer->address, sizeof(buffer->address), 1, f );
   203     fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
   204     int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
   205     fwrite( &flushed, sizeof(flushed), 1, f );
   206 }
   208 render_buffer_t pvr2_load_render_buffer( FILE *f, gboolean *status )
   209 {
   210     frame_buffer_t frame = read_png_from_stream( f );
   211     if( frame == NULL ) {
   212         *status = FALSE;
   213         return NULL;
   214     }
   215     *status = TRUE;
   217     render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
   218     if( buffer != NULL ) {
   219         int32_t flushed;
   220         fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   221         fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   222         fread( &buffer->address, sizeof(buffer->address), 1, f );
   223         fread( &buffer->scale, sizeof(buffer->scale), 1, f );
   224         fread( &flushed, sizeof(flushed), 1, f );
   225         buffer->flushed = (gboolean)flushed;
   226     } else {
   227         fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
   228                 sizeof(buffer->address)+sizeof(buffer->scale)+
   229                 sizeof(int32_t), SEEK_CUR );
   230     }
   231     return buffer;
   232 }
   237 void pvr2_save_render_buffers( FILE *f )
   238 {
   239     int i;
   240     uint32_t has_frontbuffer;
   241     fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
   242     if( displayed_render_buffer != NULL ) {
   243         has_frontbuffer = 1;
   244         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   245         pvr2_save_render_buffer( f, displayed_render_buffer );
   246     } else {
   247         has_frontbuffer = 0;
   248         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   249     }
   251     for( i=0; i<render_buffer_count; i++ ) {
   252         if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
   253             pvr2_save_render_buffer( f, render_buffers[i] );
   254         }
   255     }
   256 }
   258 gboolean pvr2_load_render_buffers( FILE *f )
   259 {
   260     uint32_t count, has_frontbuffer;
   261     gboolean loadok;
   262     int i;
   264     fread( &count, sizeof(count), 1, f );
   265     if( count > MAX_RENDER_BUFFERS ) {
   266         return FALSE;
   267     }
   268     fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   269     for( i=0; i<render_buffer_count; i++ ) {
   270         display_driver->destroy_render_buffer(render_buffers[i]);
   271         render_buffers[i] = NULL;
   272     }
   273     render_buffer_count = 0;
   275     if( has_frontbuffer ) {
   276         displayed_render_buffer = pvr2_load_render_buffer(f, &loadok);
   277         if( displayed_render_buffer != NULL )
   278             display_driver->display_render_buffer( displayed_render_buffer );
   279         else if( !loadok )
   280             return FALSE;
   281         count--;
   282     }
   284     for( i=0; i<count; i++ ) {
   285         pvr2_load_render_buffer( f, &loadok );
   286         if( !loadok )
   287         	return FALSE;
   288     }
   289     return TRUE;
   290 }
   293 static void pvr2_save_state( FILE *f )
   294 {
   295     pvr2_save_render_buffers( f );
   296     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   297     pvr2_ta_save_state( f );
   298     pvr2_yuv_save_state( f );
   299 }
   301 static int pvr2_load_state( FILE *f )
   302 {
   303     if( !pvr2_load_render_buffers(f) )
   304         return 1;
   305     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   306         return 1;
   307     if( pvr2_ta_load_state(f) ) {
   308         return 1;
   309     }
   310     return pvr2_yuv_load_state(f);
   311 }
   313 /**
   314  * Update the current raster position to the given number of nanoseconds,
   315  * relative to the last time slice. (ie the raster will be adjusted forward
   316  * by nanosecs - nanosecs_already_run_this_timeslice)
   317  */
   318 static void pvr2_update_raster_posn( uint32_t nanosecs )
   319 {
   320     uint32_t old_line_count = pvr2_state.line_count;
   321     if( pvr2_state.line_time_ns == 0 ) {
   322         return; /* do nothing */
   323     }
   324     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
   325     pvr2_state.cycles_run = nanosecs;
   326     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
   327         pvr2_state.line_count ++;
   328         pvr2_state.line_remainder -= pvr2_state.line_time_ns;
   329     }
   331     if( pvr2_state.line_count >= pvr2_state.total_lines ) {
   332         pvr2_state.line_count -= pvr2_state.total_lines;
   333         if( pvr2_state.interlaced ) {
   334             pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
   335         }
   336     }
   337     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
   338             (old_line_count < pvr2_state.retrace_end_line ||
   339                     old_line_count > pvr2_state.line_count) ) {
   340         pvr2_state.frame_count++;
   341         pvr2_next_frame();
   342         pvr2_draw_frame();
   343     }
   344 }
   346 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   347 {
   348     if( nanosecs <= pvr2_state.cycles_run ) {
   349         pvr2_state.cycles_run -= nanosecs;
   350     } else {
   351         pvr2_update_raster_posn( nanosecs );
   352         pvr2_state.cycles_run = 0;
   353     }
   354     return nanosecs;
   355 }
   357 int pvr2_get_frame_count() 
   358 {
   359     return pvr2_state.frame_count;
   360 }
   362 void pvr2_draw_frame()
   363 {
   364     if( display_driver != NULL && display_driver != &display_null_driver ) {
   365         if( displayed_render_buffer == NULL ) {
   366             display_driver->display_blank(displayed_border_colour);
   367         } else {
   368             display_driver->display_render_buffer(displayed_render_buffer);
   369         }
   370     }
   371 }
   373 gboolean pvr2_save_next_scene( const gchar *filename )
   374 {
   375     if( save_next_render_filename != NULL ) {
   376         g_free( save_next_render_filename );
   377     } 
   378     save_next_render_filename = g_strdup(filename);
   379     return TRUE;
   380 }
   384 /**
   385  * Advance to the next frame, copying the current contents of video ram to
   386  * the window. If the video configuration has changed, first recompute the
   387  * new frame size/depth.
   388  */
   389 void pvr2_next_frame( void )
   390 {
   391     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   392     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
   393     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   395     if( !bEnabled ) {
   396         /* Output disabled == black */
   397         displayed_render_buffer = NULL;
   398         displayed_border_colour = 0;
   399     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
   400         /* Enabled but blanked - border colour */
   401         displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
   402         displayed_render_buffer = NULL;
   403     } else {
   404         /* Real output - determine dimensions etc */
   405         struct frame_buffer fbuf;
   406         uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
   407         int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
   408         int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   410         fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
   411         fbuf.width = (vid_ppl << 2) / colour_formats[fbuf.colour_format].bpp;
   412         fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   413         fbuf.size = (vid_ppl << 2) * fbuf.height;
   414         fbuf.rowstride = (vid_ppl + vid_stride) << 2;
   416         /* Determine the field to display, and deinterlace if possible */
   417         if( pvr2_state.interlaced ) {
   418             if( vid_ppl == vid_stride ) { /* Magic deinterlace */
   419                 fbuf.height = fbuf.height << 1;
   420                 fbuf.rowstride = vid_ppl << 2;
   421                 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   422             } else { 
   423                 /* Just display the field as is, folks. This is slightly tricky -
   424                  * we pick the field based on which frame is about to come through,
   425                  * which may not be the same as the odd_even_field.
   426                  */
   427                 gboolean oddfield = pvr2_state.odd_even_field;
   428                 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
   429                     oddfield = !oddfield;
   430                 }
   431                 if( oddfield ) {
   432                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   433                 } else {
   434                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
   435                 }
   436             }
   437         } else {
   438             fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   439         }
   440         fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
   441         fbuf.inverted = FALSE;
   442         fbuf.data = pvr2_main_ram + (fbuf.address&0x00FFFFFF);
   444         render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
   445         if( rbuf == NULL ) {
   446             rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
   447         }
   448         displayed_render_buffer = rbuf;
   449     }
   450 }
   452 /**
   453  * This has to handle every single register individually as they all get masked 
   454  * off differently (and its easier to do it at write time)
   455  */
   456 MMIO_REGION_WRITE_FN( PVR2, reg, val )
   457 {
   458     reg &= 0xFFF;
   459     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   460         MMIO_WRITE( PVR2, reg, val );
   461         return;
   462     }
   464     switch(reg) {
   465     case PVRID:
   466     case PVRVER:
   467     case GUNPOS: /* Read only registers */
   468         break;
   469     case PVRRESET:
   470         val &= 0x00000007; /* Do stuff? */
   471         MMIO_WRITE( PVR2, reg, val );
   472         break;
   473     case RENDER_START: /* Don't really care what value */
   474         if( save_next_render_filename != NULL ) {
   475             if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
   476                 INFO( "Saved scene to %s", save_next_render_filename);
   477             }
   478             g_free( save_next_render_filename );
   479             save_next_render_filename = NULL;
   480         }
   481         pvr2_scene_read();
   482         render_buffer_t buffer = pvr2_next_render_buffer();
   483         if( buffer != NULL ) {
   484             pvr2_scene_render( buffer );
   485             if( buffer->address < PVR2_RAM_BASE ) {
   486                 // Flush immediately - optimize this later. Otherwise this gets
   487                 // complicated very quickly trying to second-guess how it's
   488                 // going to be used as a texture.
   489                 pvr2_finish_render_buffer( buffer );
   490                 pvr2_render_buffer_copy_to_sh4( buffer );
   491             }
   492         }
   493         asic_event( EVENT_PVR_RENDER_DONE );
   494         break;
   495     case RENDER_POLYBASE:
   496         MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   497         break;
   498     case RENDER_TSPCFG:
   499         MMIO_WRITE( PVR2, reg, val&0x00010101 );
   500         break;
   501     case DISP_BORDER:
   502         MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   503         break;
   504     case DISP_MODE:
   505         MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   506         break;
   507     case RENDER_MODE:
   508         MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   509         break;
   510     case RENDER_SIZE:
   511         MMIO_WRITE( PVR2, reg, val&0x000001FF );
   512         break;
   513     case DISP_ADDR1:
   514         val &= 0x00FFFFFC;
   515         MMIO_WRITE( PVR2, reg, val );
   516         pvr2_update_raster_posn(sh4r.slice_cycle);
   517         break;
   518     case DISP_ADDR2:
   519         MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   520         pvr2_update_raster_posn(sh4r.slice_cycle);
   521         break;
   522     case DISP_SIZE:
   523         MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   524         break;
   525     case RENDER_ADDR1:
   526     case RENDER_ADDR2:
   527         MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   528         break;
   529     case RENDER_HCLIP:
   530         MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   531         break;
   532     case RENDER_VCLIP:
   533         MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   534         break;
   535     case DISP_HPOSIRQ:
   536         MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   537         pvr2_state.irq_hpos_line = val & 0x03FF;
   538         pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
   539         pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
   540         switch( pvr2_state.irq_hpos_mode ) {
   541         case 3: /* Reserved - treat as 0 */
   542         case 0: /* Once per frame at specified line */
   543             pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
   544             break;
   545         case 2: /* Once per line - as per-line-count */
   546             pvr2_state.irq_hpos_line = 1;
   547             pvr2_state.irq_hpos_mode = 1;
   548         case 1: /* Once per N lines */
   549             pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
   550             pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
   551             pvr2_state.irq_hpos_line_count;
   552             while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   553                 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   554             }
   555             pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
   556         }
   557         pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
   558                                       pvr2_state.irq_hpos_time_ns );
   559         break;
   560         case DISP_VPOSIRQ:
   561             val = val & 0x03FF03FF;
   562             pvr2_state.irq_vpos1 = (val >> 16);
   563             pvr2_state.irq_vpos2 = val & 0x03FF;
   564             pvr2_update_raster_posn(sh4r.slice_cycle);
   565             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   566             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   567             MMIO_WRITE( PVR2, reg, val );
   568             break;
   569         case RENDER_NEARCLIP:
   570             MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   571             break;
   572         case RENDER_SHADOW:
   573             MMIO_WRITE( PVR2, reg, val&0x000001FF );
   574             break;
   575         case RENDER_OBJCFG:
   576             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   577             break;
   578         case RENDER_TSPCLIP:
   579             MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   580             break;
   581         case RENDER_FARCLIP:
   582             MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   583             break;
   584         case RENDER_BGPLANE:
   585             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   586             break;
   587         case RENDER_ISPCFG:
   588             MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   589             break;
   590         case VRAM_CFG1:
   591             MMIO_WRITE( PVR2, reg, val&0x000000FF );
   592             break;
   593         case VRAM_CFG2:
   594             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   595             break;
   596         case VRAM_CFG3:
   597             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   598             break;
   599         case RENDER_FOGTBLCOL:
   600         case RENDER_FOGVRTCOL:
   601             MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   602             break;
   603         case RENDER_FOGCOEFF:
   604             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   605             break;
   606         case RENDER_CLAMPHI:
   607         case RENDER_CLAMPLO:
   608             MMIO_WRITE( PVR2, reg, val );
   609             break;
   610         case RENDER_TEXSIZE:
   611             MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   612             break;
   613         case RENDER_PALETTE:
   614             MMIO_WRITE( PVR2, reg, val&0x00000003 );
   615             break;
   616         case RENDER_ALPHA_REF:
   617             MMIO_WRITE( PVR2, reg, val&0x000000FF );
   618             break;
   619             /********** CRTC registers *************/
   620         case DISP_HBORDER:
   621         case DISP_VBORDER:
   622             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   623             break;
   624         case DISP_TOTAL:
   625             val = val & 0x03FF03FF;
   626             MMIO_WRITE( PVR2, reg, val );
   627             pvr2_update_raster_posn(sh4r.slice_cycle);
   628             pvr2_state.total_lines = (val >> 16) + 1;
   629             pvr2_state.line_size = (val & 0x03FF) + 1;
   630             pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
   631             pvr2_state.retrace_end_line = 0x2A;
   632             pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
   633             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   634             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   635             pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
   636                                           pvr2_state.irq_hpos_time_ns );
   637             break;
   638         case DISP_SYNCCFG:
   639             MMIO_WRITE( PVR2, reg, val&0x000003FF );
   640             pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
   641             break;
   642         case DISP_SYNCTIME:
   643             pvr2_state.vsync_lines = (val >> 8) & 0x0F;
   644             pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
   645             MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   646             break;
   647         case DISP_CFG2:
   648             MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   649             break;
   650         case DISP_HPOS:
   651             val = val & 0x03FF;
   652             pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
   653             MMIO_WRITE( PVR2, reg, val );
   654             break;
   655         case DISP_VPOS:
   656             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   657             break;
   659             /*********** Tile accelerator registers ***********/
   660         case TA_POLYPOS:
   661         case TA_LISTPOS:
   662             /* Readonly registers */
   663             break;
   664         case TA_TILEBASE:
   665         case TA_LISTEND:
   666         case TA_LISTBASE:
   667             MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   668             break;
   669         case RENDER_TILEBASE:
   670         case TA_POLYBASE:
   671         case TA_POLYEND:
   672             MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   673             break;
   674         case TA_TILESIZE:
   675             MMIO_WRITE( PVR2, reg, val&0x000F003F );
   676             break;
   677         case TA_TILECFG:
   678             MMIO_WRITE( PVR2, reg, val&0x00133333 );
   679             break;
   680         case TA_INIT:
   681             if( val & 0x80000000 )
   682                 pvr2_ta_init();
   683             break;
   684         case TA_REINIT:
   685             break;
   686             /**************** Scaler registers? ****************/
   687         case RENDER_SCALER:
   688             MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   689             break;
   691         case YUV_ADDR:
   692             val = val & 0x00FFFFF8;
   693             MMIO_WRITE( PVR2, reg, val );
   694             pvr2_yuv_init( val );
   695             break;
   696         case YUV_CFG:
   697             MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   698             pvr2_yuv_set_config(val);
   699             break;
   701             /**************** Unknowns ***************/
   702         case PVRUNK1:
   703             MMIO_WRITE( PVR2, reg, val&0x000007FF );
   704             break;
   705         case PVRUNK2:
   706             MMIO_WRITE( PVR2, reg, val&0x00000007 );
   707             break;
   708         case PVRUNK3:
   709             MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   710             break;
   711         case PVRUNK5:
   712             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   713             break;
   714         case PVRUNK7:
   715             MMIO_WRITE( PVR2, reg, val&0x00000001 );
   716             break;
   717         case PVRUNK8:
   718             MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
   719             break;
   720     }
   721 }
   723 /**
   724  * Calculate the current read value of the syncstat register, using
   725  * the current SH4 clock time as an offset from the last timeslice.
   726  * The register reads (LSB to MSB) as:
   727  *     0..9  Current scan line
   728  *     10    Odd/even field (1 = odd, 0 = even)
   729  *     11    Display active (including border and overscan)
   730  *     12    Horizontal sync off
   731  *     13    Vertical sync off
   732  * Note this method is probably incorrect for anything other than straight
   733  * interlaced PAL/NTSC, and needs further testing. 
   734  */
   735 uint32_t pvr2_get_sync_status()
   736 {
   737     pvr2_update_raster_posn(sh4r.slice_cycle);
   738     uint32_t result = pvr2_state.line_count;
   740     if( pvr2_state.odd_even_field ) {
   741         result |= 0x0400;
   742     }
   743     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
   744         if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
   745             result |= 0x1000; /* !HSYNC */
   746         }
   747         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   748             if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
   749                 result |= 0x2800; /* Display active */
   750             } else {
   751                 result |= 0x2000; /* Front porch */
   752             }
   753         }
   754     } else {
   755         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   756             if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
   757                 result |= 0x3800; /* Display active */
   758             } else {
   759                 result |= 0x3000;
   760             }
   761         } else {
   762             result |= 0x1000; /* Back porch */
   763         }
   764     }
   765     return result;
   766 }
   768 /**
   769  * Schedule a "scanline" event. This actually goes off at
   770  * 2 * line in even fields and 2 * line + 1 in odd fields.
   771  * Otherwise this behaves as per pvr2_schedule_line_event().
   772  * The raster position should be updated before calling this
   773  * method.
   774  * @param eventid Event to fire at the specified time
   775  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
   776  *  displays). 
   777  * @param hpos_ns Nanoseconds into the line at which to fire.
   778  */
   779 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
   780 {
   781     uint32_t field = pvr2_state.odd_even_field;
   782     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
   783         field = !field;
   784     }
   785     if( hpos_ns > pvr2_state.line_time_ns ) {
   786         hpos_ns = pvr2_state.line_time_ns;
   787     }
   789     line <<= 1;
   790     if( field ) {
   791         line += 1;
   792     }
   794     if( line < pvr2_state.total_lines ) {
   795         uint32_t lines;
   796         uint32_t time;
   797         if( line <= pvr2_state.line_count ) {
   798             lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
   799         } else {
   800             lines = (line - pvr2_state.line_count);
   801         }
   802         if( lines <= minimum_lines ) {
   803             lines += pvr2_state.total_lines;
   804         }
   805         time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
   806         event_schedule( eventid, time );
   807     } else {
   808         event_cancel( eventid );
   809     }
   810 }
   812 void pvr2_queue_gun_event( int xpos, int ypos )
   813 {
   814     pvr2_update_raster_posn(sh4r.slice_cycle);
   815     pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,  
   816             (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns ); 
   817 }
   819 MMIO_REGION_READ_FN( PVR2, reg )
   820 {
   821     reg &= 0xFFF;
   822     switch( reg ) {
   823     case DISP_SYNCSTAT:
   824         return pvr2_get_sync_status();
   825     default:
   826         return MMIO_READ( PVR2, reg );
   827     }
   828 }
   829 MMIO_REGION_READ_DEFSUBFNS(PVR2)
   830 MMIO_REGION_READ_DEFSUBFNS(PVR2PAL)
   832 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
   833 {
   834     reg &= 0xFFF;
   835     MMIO_WRITE( PVR2PAL, reg, val );
   836     pvr2_state.palette_changed = TRUE;
   837 }
   839 void pvr2_check_palette_changed()
   840 {
   841     if( pvr2_state.palette_changed ) {
   842         texcache_invalidate_palette();
   843         pvr2_state.palette_changed = FALSE;
   844     }
   845 }
   847 MMIO_REGION_READ_DEFFN( PVR2PAL );
   849 void pvr2_set_base_address( uint32_t base ) 
   850 {
   851     mmio_region_PVR2_write( DISP_ADDR1, base );
   852 }
   854 render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
   855 {
   856     if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
   857         render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
   858         buffer->address = addr;
   859         return buffer;
   860     }
   861     return NULL;
   862 }
   864 void pvr2_destroy_render_buffer( render_buffer_t buffer )
   865 {
   866     if( !buffer->flushed )
   867         pvr2_render_buffer_copy_to_sh4( buffer );
   868      display_driver->destroy_render_buffer( buffer );
   869 }
   871 void pvr2_destroy_render_buffers( void )
   872 {
   873     if( display_driver ) {
   874         int i;
   875         for( i=0; i<render_buffer_count; i++ ) {
   876             if( render_buffers[i] != NULL ) {
   877                 pvr2_destroy_render_buffer(render_buffers[i]);
   878                 render_buffers[i] = NULL;
   879             }
   880         }
   881         render_buffer_count = 0;
   882     }
   883 }    
   885 static frame_buffer_t saved_render_buffers[MAX_RENDER_BUFFERS];
   886 static frame_buffer_t saved_displayed_render_buffer = NULL;
   887 static int saved_render_buffer_count = 0;
   889 /*
   890  * Copy all render buffers to main RAM to preserve across GL shutdown
   891  */
   892 void pvr2_preserve_render_buffers( void )
   893 {
   894      int i, j;
   895      /* If we had previous preserved buffers, blow them away now. */
   896      for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
   897          if( saved_render_buffers[i] != NULL ) {
   898              g_free(saved_render_buffers[i]);
   899              saved_render_buffers[i] = NULL;
   900          }
   901      }
   902      saved_displayed_render_buffer = NULL;
   904      for( i=0, j=0; i<render_buffer_count; i++ ) {
   905          if( render_buffers[i]->address != -1 ) {
   906              saved_render_buffers[j] = pvr2_render_buffer_to_frame_buffer(render_buffers[i]);
   907              if( render_buffers[i] == displayed_render_buffer )
   908                  saved_displayed_render_buffer = saved_render_buffers[j];
   909              j++;
   910          }
   911      }
   912      saved_render_buffer_count = j;
   913 }
   915 /**
   916  * Restore render buffers that were preserved by a previous call to
   917  * pvr2_preserve_render_buffers().
   918  */
   919 void pvr2_restore_render_buffers( void )
   920 {
   921     int i;
   922     for( i=0; i<saved_render_buffer_count; i++ ) {
   923         if( saved_render_buffers[i] != NULL ) {
   924             render_buffers[i] = pvr2_frame_buffer_to_render_buffer(saved_render_buffers[i]);
   925             if( saved_render_buffers[i] == saved_displayed_render_buffer )
   926                 displayed_render_buffer = render_buffers[i];
   927             g_free(saved_render_buffers[i]);
   928             saved_render_buffers[i] = NULL;
   929         }
   930     }
   931     render_buffer_count = saved_render_buffer_count;
   932     saved_render_buffer_count = 0;
   933     saved_displayed_render_buffer = NULL;
   934 }
   937 void pvr2_finish_render_buffer( render_buffer_t buffer )
   938 {
   939     display_driver->finish_render( buffer );
   940 }
   942 /**
   943  * Find the render buffer corresponding to the requested output frame
   944  * (does not consider texture renders). 
   945  * @return the render_buffer if found, or null if no such buffer.
   946  *
   947  * Note: Currently does not consider "partial matches", ie partial
   948  * frame overlap - it probably needs to do this.
   949  */
   950 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
   951 {
   952     int i;
   953     for( i=0; i<render_buffer_count; i++ ) {
   954         if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
   955             return render_buffers[i];
   956         }
   957     }
   958     return NULL;
   959 }
   961 /**
   962  * Allocate a render buffer with the requested parameters.
   963  * The order of preference is:
   964  *   1. An existing buffer with the same address. (not flushed unless the new
   965  * size is smaller than the old one).
   966  *   2. An existing buffer with the same size chosen by LRU order. Old buffer
   967  *       is flushed to vram.
   968  *   3. A new buffer if one can be created.
   969  *   4. The current display buff
   970  * Note: The current display field(s) will never be overwritten except as a last
   971  * resort.
   972  */
   973 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
   974 {
   975     int i;
   976     render_buffer_t result = NULL;
   978     /* Check existing buffers for an available buffer */
   979     for( i=0; i<render_buffer_count; i++ ) {
   980         if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
   981             /* needs to be the right dimensions */
   982             if( render_buffers[i]->address == render_addr ) {
   983                 if( displayed_render_buffer == render_buffers[i] ) {
   984                     /* Same address, but we can't use it because the
   985                      * display has it. Mark it as unaddressed for later.
   986                      */
   987                     render_buffers[i]->address = -1;
   988                     render_buffers[i]->flushed = TRUE;
   989                 } else {
   990                     /* perfect */
   991                     result = render_buffers[i];
   992                     break;
   993                 }
   994             } else if( render_buffers[i]->address == -1 && result == NULL && 
   995                     displayed_render_buffer != render_buffers[i] ) {
   996                 result = render_buffers[i];
   997             }
   999         } else if( render_buffers[i]->address == render_addr ) {
  1000             /* right address, wrong size - if it's larger, flush it, otherwise 
  1001              * nuke it quietly */
  1002             if( render_buffers[i]->width * render_buffers[i]->height >
  1003             width*height ) {
  1004                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
  1006             render_buffers[i]->address = -1;
  1007             render_buffers[i]->flushed = TRUE;
  1011     /* Nothing available - make one */
  1012     if( result == NULL ) {
  1013         if( render_buffer_count == MAX_RENDER_BUFFERS ) {
  1014             /* maximum buffers reached - need to throw one away */
  1015             uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
  1016             uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
  1017             for( i=0; i<render_buffer_count; i++ ) {
  1018                 if( render_buffers[i]->address != field1_addr &&
  1019                         render_buffers[i]->address != field2_addr &&
  1020                         render_buffers[i] != displayed_render_buffer ) {
  1021                     /* Never throw away the current "front buffer(s)" */
  1022                     result = render_buffers[i];
  1023                     if( !result->flushed && result->address != -1 ) {
  1024                         pvr2_render_buffer_copy_to_sh4( result );
  1026                     if( result->width != width || result->height != height ) {
  1027                         display_driver->destroy_render_buffer(render_buffers[i]);
  1028                         result = display_driver->create_render_buffer(width,height,0);
  1029                         render_buffers[i] = result;
  1031                     break;
  1034         } else {
  1035             result = display_driver->create_render_buffer(width,height,0);
  1036             if( result != NULL ) { 
  1037                 render_buffers[render_buffer_count++] = result;
  1042     if( result != NULL ) {
  1043         result->address = render_addr;
  1045     return result;
  1048 /**
  1049  * Allocate a render buffer based on the current rendering settings
  1050  */
  1051 render_buffer_t pvr2_next_render_buffer()
  1053     render_buffer_t result = NULL;
  1054     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
  1055     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
  1056     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
  1057     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
  1059     int width = pvr2_scene_buffer_width();
  1060     int height = pvr2_scene_buffer_height();
  1061     int colour_format = render_colour_formats[render_mode&0x07];
  1063     if( render_addr & 0x01000000 ) { /* vram64 */
  1064         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
  1065     } else { /* vram32 */
  1066         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
  1068     result = pvr2_alloc_render_buffer( render_addr, width, height );
  1070     /* Setup the buffer */
  1071     if( result != NULL ) {
  1072         result->rowstride = render_stride;
  1073         result->colour_format = colour_format;
  1074         result->scale = render_scale;
  1075         result->size = width * height * colour_formats[colour_format].bpp;
  1076         result->flushed = FALSE;
  1077         result->inverted = TRUE; // render buffers are inverted normally
  1079     return result;
  1082 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
  1084     render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
  1085     if( result != NULL ) {
  1086         int bpp = colour_formats[frame->colour_format].bpp;
  1087         result->rowstride = frame->rowstride;
  1088         result->colour_format = frame->colour_format;
  1089         result->scale = 0x400;
  1090         result->size = frame->width * frame->height * bpp;
  1091         result->flushed = TRUE;
  1092         result->inverted = frame->inverted;
  1093         display_driver->load_frame_buffer( frame, result );
  1095     return result;
  1098 static frame_buffer_t pvr2_render_buffer_to_frame_buffer( render_buffer_t buffer )
  1100     int bpp = colour_formats[buffer->colour_format].bpp;
  1101     size_t size = buffer->width * buffer->height * bpp;
  1102     frame_buffer_t result = g_malloc0( sizeof(struct frame_buffer) + size );
  1103     result->data = (unsigned char *)(result+1);
  1104     result->width = buffer->width;
  1105     result->height = buffer->height;
  1106     result->rowstride = buffer->rowstride;
  1107     result->colour_format = buffer->colour_format;
  1108     result->address = buffer->address;
  1109     result->size = buffer->size;
  1110     result->inverted = buffer->inverted;
  1111     display_driver->read_render_buffer( result->data, buffer, buffer->width * bpp, buffer->colour_format );
  1112     return result;
  1116 /**
  1117  * Invalidate any caching on the supplied address. Specifically, if it falls
  1118  * within any of the render buffers, flush the buffer back to PVR2 ram.
  1119  */
  1120 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
  1122     int i;
  1123     address = address & 0x1FFFFFFF;
  1124     for( i=0; i<render_buffer_count; i++ ) {
  1125         uint32_t bufaddr = render_buffers[i]->address;
  1126         if( bufaddr != -1 && bufaddr <= address && 
  1127                 (bufaddr + render_buffers[i]->size) > address ) {
  1128             if( !render_buffers[i]->flushed ) {
  1129                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
  1131             if( isWrite ) {
  1132                 render_buffers[i]->address = -1; /* Invalid */
  1133                 render_buffers[i]->flushed = TRUE;
  1135             return TRUE; /* should never have overlapping buffers */
  1138     return FALSE;
.