lxdream 0.9.1| filename | src/aica/armcore.h |
| changeset | 30:89b30313d757 |
| prev | 14:fc481a638848 |
| next | 35:21a4be098304 |
| author | nkeynes |
| date | Sun Dec 25 05:57:00 2005 +0000 (18 years ago) |
| permissions | -rw-r--r-- |
| last change | Change timeslice to nanoseconds (was microseconds) Generize single step (now steps through active CPU) Add lots of header blocks |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: armcore.h,v 1.6 2005-12-25 05:57:00 nkeynes Exp $
3 *
4 * Interface definitions for the ARM CPU emulation core proper.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #ifndef dream_armcore_H
20 #define dream_armcore_H 1
22 #include "dream.h"
23 #include <stdint.h>
25 #define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) )
27 struct arm_registers {
28 uint32_t r[16]; /* Current register bank */
30 uint32_t cpsr;
31 uint32_t spsr;
33 /* Various banked versions of the registers. */
34 uint32_t fiq_r[7]; /* FIQ bank 8..14 */
35 uint32_t irq_r[2]; /* IRQ bank 13..14 */
36 uint32_t und_r[2]; /* UND bank 13..14 */
37 uint32_t abt_r[2]; /* ABT bank 13..14 */
38 uint32_t svc_r[2]; /* SVC bank 13..14 */
39 uint32_t user_r[7]; /* User/System bank 8..14 */
41 uint32_t c,n,z,v,t;
43 /* "fake" registers */
44 uint32_t shift_c; /* used for temporary storage of shifter results */
45 uint32_t icount; /* Instruction counter */
46 };
48 #define CPSR_N 0x80000000 /* Negative flag */
49 #define CPSR_Z 0x40000000 /* Zero flag */
50 #define CPSR_C 0x20000000 /* Carry flag */
51 #define CPSR_V 0x10000000 /* Overflow flag */
52 #define CPSR_I 0x00000080 /* Interrupt disable bit */
53 #define CPSR_F 0x00000040 /* Fast interrupt disable bit */
54 #define CPSR_T 0x00000020 /* Thumb mode */
55 #define CPSR_MODE 0x0000001F /* Current execution mode */
57 #define MODE_USER 0x00 /* User mode */
58 #define MODE_FIQ 0x01 /* Fast IRQ mode */
59 #define MODE_IRQ 0x02 /* IRQ mode */
60 #define MODE_SV 0x03 /* Supervisor mode */
61 #define MODE_ABT 0x07 /* Abort mode */
62 #define MODE_UND 0x0B /* Undefined mode */
63 #define MODE_SYS 0x0F /* System mode */
65 extern struct arm_registers armr;
67 #define CARRY_FLAG (armr.cpsr&CPSR_C)
69 /* ARM Memory */
70 int32_t arm_read_long( uint32_t addr );
71 int32_t arm_read_word( uint32_t addr );
72 int32_t arm_read_byte( uint32_t addr );
73 void arm_write_long( uint32_t addr, uint32_t val );
74 void arm_write_word( uint32_t addr, uint32_t val );
75 void arm_write_byte( uint32_t addr, uint32_t val );
76 int32_t arm_read_phys_word( uint32_t addr );
77 int arm_has_page( uint32_t addr );
78 gboolean arm_execute_instruction( void );
80 #endif /* !dream_armcore_H */
.