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lxdream.org :: lxdream/src/sh4/sh4mmio.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.c
changeset 30:89b30313d757
prev23:1ec3acd0594d
next35:21a4be098304
author nkeynes
date Sun Dec 25 05:57:00 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Change timeslice to nanoseconds (was microseconds)
Generize single step (now steps through active CPU)
Add lots of header blocks
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     1 /**
     2  * $Id: sh4mmio.c,v 1.5 2005-12-25 05:57:00 nkeynes Exp $
     3  * 
     4  * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
     5  * responsible for including the IMPL side of the SH4 MMIO pages.
     6  * Most of these will eventually be split off into their own files.
     7  *
     8  * Copyright (c) 2005 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include "dream.h"
    22 #include "mem.h"
    23 #include "clock.h"
    24 #include "sh4core.h"
    25 #include "sh4mmio.h"
    26 #define MMIO_IMPL
    27 #include "sh4mmio.h"
    29 /********************************* MMU *************************************/
    31 MMIO_REGION_READ_STUBFN( MMU )
    33 #define OCRAM_START (0x1C000000>>PAGE_BITS)
    34 #define OCRAM_END   (0x20000000>>PAGE_BITS)
    36 static char *cache = NULL;
    38 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
    39 {
    40     switch(reg) {
    41         case CCR:
    42             mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
    43             INFO( "Cache mode set to %08X", val );
    44             break;
    45         default:
    46             break;
    47     }
    48     MMIO_WRITE( MMU, reg, val );
    49 }
    52 void mmu_init() 
    53 {
    54     cache = mem_alloc_pages(2);
    55 }
    57 void mmu_set_cache_mode( int mode )
    58 {
    59     uint32_t i;
    60     switch( mode ) {
    61         case MEM_OC_INDEX0: /* OIX=0 */
    62             for( i=OCRAM_START; i<OCRAM_END; i++ )
    63                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
    64             break;
    65         case MEM_OC_INDEX1: /* OIX=1 */
    66             for( i=OCRAM_START; i<OCRAM_END; i++ )
    67                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
    68             break;
    69         default: /* disabled */
    70             for( i=OCRAM_START; i<OCRAM_END; i++ )
    71                 page_map[i] = NULL;
    72             break;
    73     }
    74 }
    77 /********************************* BSC *************************************/
    79 uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
    80 uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;
    81 uint32_t bsc_output = 0, bsc_input = 0x0300;
    83 void bsc_out( int output, int mask )
    84 {
    85     /* Go figure... The BIOS won't start without this mess though */
    86     if( ((output | (~mask)) & 0x03) == 3 ) {
    87         bsc_output |= 0x03;
    88     } else {
    89         bsc_output &= ~0x03;
    90     }
    91 }
    93 void mmio_region_BSC_write( uint32_t reg, uint32_t val )
    94 {
    95     int i;
    96     switch( reg ) {
    97         case PCTRA:
    98             bsc_input_mask_lo = bsc_output_mask_lo = 0;
    99             for( i=0; i<16; i++ ) {
   100                 int bits = (val >> (i<<1)) & 0x03;
   101                 if( bits == 2 ) bsc_input_mask_lo |= (1<<i);
   102                 else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);
   103             }
   104             bsc_output = (bsc_output&0x000F0000) |
   105                 (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);
   106             bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),
   107                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
   108             break;
   109         case PCTRB:
   110             bsc_input_mask_hi = bsc_output_mask_hi = 0;
   111             for( i=0; i<4; i++ ) {
   112                 int bits = (val >> (i>>1)) & 0x03;
   113                 if( bits == 2 ) bsc_input_mask_hi |= (1<<i);
   114                 else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);
   115             }
   116             bsc_output = (bsc_output&0xFFFF) |
   117                 ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);
   118             break;
   119         case PDTRA:
   120             bsc_output = (bsc_output&0x000F0000) |
   121                 (val & bsc_output_mask_lo );
   122             bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),
   123                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
   124             break;
   125         case PDTRB:
   126             bsc_output = (bsc_output&0xFFFF) |
   127                 ( (val & bsc_output_mask_hi)<<16 );
   128             break;
   129     }
   130     WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",
   131           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
   132     MMIO_WRITE( BSC, reg, val );
   133 }
   135 int32_t mmio_region_BSC_read( uint32_t reg )
   136 {
   137     int32_t val;
   138     switch( reg ) {
   139         case PDTRA:
   140             val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);
   141             break;
   142         case PDTRB:
   143             val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);
   144             break;
   145         default:
   146             val = MMIO_READ( BSC, reg );
   147     }
   148     WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",
   149           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
   150     return val;
   151 }
   153 /********************************* UBC *************************************/
   155 MMIO_REGION_STUBFNS( UBC )
   158 /********************************* DMAC *************************************/
   160 MMIO_REGION_STUBFNS( DMAC )
   164 /********************************** SCI *************************************/
   166 MMIO_REGION_STUBFNS( SCI )
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