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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 472:8a3ae91eb215
prev422:61a0598e07ff
next502:c4ecae2b1b5e
author nkeynes
date Wed Oct 31 09:02:18 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Ensure xlat cache is flushed on state load and reset
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     1 /**
     2  * $Id: sh4.c,v 1.6 2007-10-31 09:02:18 nkeynes Exp $
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4mmio.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/xltcache.h"
    28 #include "sh4/sh4stat.h"
    29 #include "mem.h"
    30 #include "clock.h"
    31 #include "syscall.h"
    33 #define EXV_EXCEPTION    0x100  /* General exception vector */
    34 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    35 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    37 void sh4_init( void );
    38 void sh4_x86_init( void );
    39 void sh4_reset( void );
    40 void sh4_start( void );
    41 void sh4_stop( void );
    42 void sh4_save_state( FILE *f );
    43 int sh4_load_state( FILE *f );
    45 uint32_t sh4_run_slice( uint32_t );
    46 uint32_t sh4_xlat_run_slice( uint32_t );
    48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    49 				       NULL, sh4_run_slice, sh4_stop,
    50 				       sh4_save_state, sh4_load_state };
    52 struct sh4_registers sh4r;
    53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    54 int sh4_breakpoint_count = 0;
    55 extern char *sh4_main_ram;
    57 void sh4_set_use_xlat( gboolean use )
    58 {
    59     if( use ) {
    60 	xlat_cache_init();
    61 	sh4_x86_init();
    62 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    63     } else {
    64 	sh4_module.run_time_slice = sh4_run_slice;
    65     }
    66 }
    68 void sh4_init(void)
    69 {
    70     register_io_regions( mmio_list_sh4mmio );
    71     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    72     MMU_init();
    73     sh4_reset();
    74 }
    76 void sh4_reset(void)
    77 {
    78     if(	sh4_module.run_time_slice == sh4_xlat_run_slice ) {
    79 	xlat_flush_cache();
    80     }
    82     /* zero everything out, for the sake of having a consistent state. */
    83     memset( &sh4r, 0, sizeof(sh4r) );
    85     /* Resume running if we were halted */
    86     sh4r.sh4_state = SH4_STATE_RUNNING;
    88     sh4r.pc    = 0xA0000000;
    89     sh4r.new_pc= 0xA0000002;
    90     sh4r.vbr   = 0x00000000;
    91     sh4r.fpscr = 0x00040001;
    92     sh4r.sr    = 0x700000F0;
    93     sh4r.fr_bank = &sh4r.fr[0][0];
    95     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    96     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    98     /* Peripheral modules */
    99     CPG_reset();
   100     INTC_reset();
   101     MMU_reset();
   102     TMU_reset();
   103     SCIF_reset();
   104     sh4_stats_reset();
   105 }
   107 void sh4_stop(void)
   108 {
   110 }
   112 void sh4_save_state( FILE *f )
   113 {
   114     if(	sh4_module.run_time_slice == sh4_xlat_run_slice ) {
   115 	/* If we were running with the translator, update new_pc and in_delay_slot */
   116 	sh4r.new_pc = sh4r.pc+2;
   117 	sh4r.in_delay_slot = FALSE;
   118     }
   120     fwrite( &sh4r, sizeof(sh4r), 1, f );
   121     MMU_save_state( f );
   122     INTC_save_state( f );
   123     TMU_save_state( f );
   124     SCIF_save_state( f );
   125 }
   127 int sh4_load_state( FILE * f )
   128 {
   129     if(	sh4_module.run_time_slice == sh4_xlat_run_slice ) {
   130 	xlat_flush_cache();
   131     }
   132     fread( &sh4r, sizeof(sh4r), 1, f );
   133     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   134     MMU_load_state( f );
   135     INTC_load_state( f );
   136     TMU_load_state( f );
   137     return SCIF_load_state( f );
   138 }
   141 void sh4_set_breakpoint( uint32_t pc, int type )
   142 {
   143     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   144     sh4_breakpoints[sh4_breakpoint_count].type = type;
   145     sh4_breakpoint_count++;
   146 }
   148 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   149 {
   150     int i;
   152     for( i=0; i<sh4_breakpoint_count; i++ ) {
   153 	if( sh4_breakpoints[i].address == pc && 
   154 	    sh4_breakpoints[i].type == type ) {
   155 	    while( ++i < sh4_breakpoint_count ) {
   156 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   157 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   158 	    }
   159 	    sh4_breakpoint_count--;
   160 	    return TRUE;
   161 	}
   162     }
   163     return FALSE;
   164 }
   166 int sh4_get_breakpoint( uint32_t pc )
   167 {
   168     int i;
   169     for( i=0; i<sh4_breakpoint_count; i++ ) {
   170 	if( sh4_breakpoints[i].address == pc )
   171 	    return sh4_breakpoints[i].type;
   172     }
   173     return 0;
   174 }
   176 void sh4_set_pc( int pc )
   177 {
   178     sh4r.pc = pc;
   179     sh4r.new_pc = pc+2;
   180 }
   183 /******************************* Support methods ***************************/
   185 static void sh4_switch_banks( )
   186 {
   187     uint32_t tmp[8];
   189     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   190     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   191     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   192 }
   194 void sh4_write_sr( uint32_t newval )
   195 {
   196     if( (newval ^ sh4r.sr) & SR_RB )
   197         sh4_switch_banks();
   198     sh4r.sr = newval;
   199     sh4r.t = (newval&SR_T) ? 1 : 0;
   200     sh4r.s = (newval&SR_S) ? 1 : 0;
   201     sh4r.m = (newval&SR_M) ? 1 : 0;
   202     sh4r.q = (newval&SR_Q) ? 1 : 0;
   203     intc_mask_changed();
   204 }
   206 uint32_t sh4_read_sr( void )
   207 {
   208     /* synchronize sh4r.sr with the various bitflags */
   209     sh4r.sr &= SR_MQSTMASK;
   210     if( sh4r.t ) sh4r.sr |= SR_T;
   211     if( sh4r.s ) sh4r.sr |= SR_S;
   212     if( sh4r.m ) sh4r.sr |= SR_M;
   213     if( sh4r.q ) sh4r.sr |= SR_Q;
   214     return sh4r.sr;
   215 }
   219 #define RAISE( x, v ) do{			\
   220     if( sh4r.vbr == 0 ) { \
   221         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   222         dreamcast_stop(); return FALSE;	\
   223     } else { \
   224         sh4r.spc = sh4r.pc;	\
   225         sh4r.ssr = sh4_read_sr(); \
   226         sh4r.sgr = sh4r.r[15]; \
   227         MMIO_WRITE(MMU,EXPEVT,x); \
   228         sh4r.pc = sh4r.vbr + v; \
   229         sh4r.new_pc = sh4r.pc + 2; \
   230         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   231 	if( sh4r.in_delay_slot ) { \
   232 	    sh4r.in_delay_slot = 0; \
   233 	    sh4r.spc -= 2; \
   234 	} \
   235     } \
   236     return TRUE; } while(0)
   238 /**
   239  * Raise a general CPU exception for the specified exception code.
   240  * (NOT for TRAPA or TLB exceptions)
   241  */
   242 gboolean sh4_raise_exception( int code )
   243 {
   244     RAISE( code, EXV_EXCEPTION );
   245 }
   247 gboolean sh4_raise_trap( int trap )
   248 {
   249     MMIO_WRITE( MMU, TRA, trap<<2 );
   250     return sh4_raise_exception( EXC_TRAP );
   251 }
   253 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   254     if( sh4r.in_delay_slot ) {
   255 	return sh4_raise_exception(slot_code);
   256     } else {
   257 	return sh4_raise_exception(normal_code);
   258     }
   259 }
   261 gboolean sh4_raise_tlb_exception( int code )
   262 {
   263     RAISE( code, EXV_TLBMISS );
   264 }
   266 void sh4_accept_interrupt( void )
   267 {
   268     uint32_t code = intc_accept_interrupt();
   269     sh4r.ssr = sh4_read_sr();
   270     sh4r.spc = sh4r.pc;
   271     sh4r.sgr = sh4r.r[15];
   272     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   273     MMIO_WRITE( MMU, INTEVT, code );
   274     sh4r.pc = sh4r.vbr + 0x600;
   275     sh4r.new_pc = sh4r.pc + 2;
   276     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   277 }
   279 void signsat48( void )
   280 {
   281     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   282 	sh4r.mac = 0xFFFF800000000000LL;
   283     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   284 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   285 }
   287 void sh4_fsca( uint32_t anglei, float *fr )
   288 {
   289     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   290     *fr++ = cosf(angle);
   291     *fr = sinf(angle);
   292 }
   294 void sh4_sleep(void)
   295 {
   296     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   297 	sh4r.sh4_state = SH4_STATE_STANDBY;
   298     } else {
   299 	sh4r.sh4_state = SH4_STATE_SLEEP;
   300     }
   301 }
   303 /**
   304  * Compute the matrix tranform of fv given the matrix xf.
   305  * Both fv and xf are word-swapped as per the sh4r.fr banks
   306  */
   307 void sh4_ftrv( float *target, float *xf )
   308 {
   309     float fv[4] = { target[1], target[0], target[3], target[2] };
   310     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   311 	xf[9]*fv[2] + xf[13]*fv[3];
   312     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   313 	xf[8]*fv[2] + xf[12]*fv[3];
   314     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   315 	xf[11]*fv[2] + xf[15]*fv[3];
   316     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   317 	xf[10]*fv[2] + xf[14]*fv[3];
   318 }
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