lxdream 0.9.1| filename | src/sh4/sh4.def |
| changeset | 359:c588dce7ebde |
| author | nkeynes |
| date | Thu Dec 11 23:26:03 2008 +0000 (15 years ago) |
| permissions | -rw-r--r-- |
| last change | Disable the generational translation cache - I've got no evidence that it actually helps performance, and it simplifies things to get rid of it (in particular, translated code doesn't have to worry about being moved now). |
| view | annotate | diff | log | raw |
1 ##
2 ## Instruction file for the SH4 - from the SH4 manual.
3 ## line ::= bitpattern WHITESPACE result NEWLINE
4 ## bitpattern ::= { '0' | '1' | '(' operand ')' }
5 ## operand ::= IDENTIFIER ':' NUMBER signspec
6 ## signspec ::= 'u' | 's' |
7 ## result ::= { IDENTIFIER | NON-IDENT-CHAR }
9 registers {
10 uint32 Rm, Rn = r0..r15
11 uint32 Rm_BANK, Rn_BANK = r8_bank..r15_bank
12 float Frm, Frn = fr0..fr15
13 float XFm, XFn = xf0..xf15
14 double Drm, Drn = dr0..dr8 overlaps fr0..fr15 swapped
15 double XDm, XDn = xd0..xd8 overlaps xf0..xf15 swapped
16 float[4] FVm, FVn = fv0..fv3 overlaps fr0..fr15
17 float[16] XMTRX = xmtrx overlaps xf0..xf15
19 ## Special registers
20 uint32 GBR, SR, VBR, SSR, SGR SPC, DBR
21 uint32 FPSCR, FPUL, MACH, MACL, PR, PC
23 }
25 0011(Rn:4)(Rm:4)1100 ADD Rm, Rn
26 0111(Rn:4)(imm:8s) ADD #imm, Rn
27 0011(Rn:4)(Rm:4)1110 ADDC Rm, Rn
28 0011(Rn:4)(Rm:4)1111 ADDV Rm, Rn
29 0010(Rn:4)(Rm:4)1001 AND Rm, Rn
30 11001001(imm:8u) AND #imm, R0
31 11001101(imm:8u) AND.B #imm, @(R0, GBR)
32 10001011(disp:8s<<1) BF disp
33 10001111(disp:8s<<1) BF/S disp
34 1010(disp:12s<<1) BRA disp
35 0000(Rn:4)00100011 BRAF Rn
36 1011(disp:12s<<1) BSR disp
37 0000(Rn:4)00000011 BSRF Rn
38 10001001(disp:8s<<1) BT disp
39 10001101(disp:8s<<1) BT/S disp
40 0000000000101000 CLRMAC
41 0000000001001000 CLRS
42 0000000000001000 CLRT
43 0011(Rn:4)(Rm:4)0000 CMP/EQ Rm, Rn
44 10001000(imm:8s) CMP/EQ #imm, R0
45 0011(Rn:4)(Rm:4)0011 CMP/GE Rm, Rn
46 0011(Rn:4)(Rm:4)0111 CMP/GT Rm, Rn
47 0011(Rn:4)(Rm:4)0110 CMP/HI Rm, Rn
48 0011(Rn:4)(Rm:4)0010 CMP/HS Rm, Rn
49 0100(Rn:4)00010101 CMP/PL Rn
50 0100(Rn:4)00010001 CMP/PZ Rn
51 0010(Rn:4)(Rm:4)1100 CMP/STR Rm, Rn
52 0010(Rn:4)(Rm:4)0111 DIV0S Rm, Rn
53 0000000000011001 DIV0U
54 0011(Rn:4)(Rm:4)0100 DIV1 Rm, Rn
55 0011(Rn:4)(Rm:4)1101 DMULS.L Rm, Rn
56 0011(Rn:4)(Rm:4)0101 DMULU.L Rm, Rn
57 0100(Rn:4)00010000 DT Rn
58 0110(Rn:4)(Rm:4)1110 EXTS.B Rm, Rn
59 0110(Rn:4)(Rm:4)1111 EXTS.W Rm, Rn
60 0110(Rn:4)(Rm:4)1100 EXTU.B Rm, Rn
61 0110(Rn:4)(Rm:4)1101 EXTU.W Rm, Rn
62 1111(FRn:4)01011101 FABS FRn
63 1111(FRn:4)(FRm:4)0000 FADD FRm, FRn
64 1111(FRn:4)(FRm:4)0100 FCMP/EQ FRm, FRn
65 1111(FRn:4)(FRm:4)0101 FCMP/GT FRm, FRn
66 1111(FRm:4)10111101 FCNVDS FRm, FPUL
67 1111(FRn:4)10101101 FCNVSD FPUL, FRn
68 1111(FRn:4)(FRm:4)0011 FDIV FRm, FRn
69 1111(FVn:2)(FVm:2)11101101 FIPR FVm, FVn
70 1111(FRm:4)00011101 FLDS FRm, FPUL
71 1111(FRn:4)10001101 FLDI0 FRn
72 1111(FRn:4)10011101 FLDI1 FRn
73 1111(FRn:4)00101101 FLOAT FPUL, FRn
74 1111(FRn:4)(FRm:4)1110 FMAC FR0, FRm, FRn
75 1111(FRn:4)(FRm:4)1100 FMOV FRm, FRn
76 1111(Rn:4)(FRm:4)1010 FMOV FRm, @Rn
77 1111(Rn:4)(FRm:4)1011 FMOV FRm, @-Rn
78 1111(Rn:4)(FRm:4)0111 FMOV FRm, @(R0, Rn)
79 1111(FRn:4)(Rm:4)1000 FMOV @Rm, FRn
80 1111(FRn:4)(Rm:4)1001 FMOV @Rm+, FRn
81 1111(FRn:4)(Rm:4)0110 FMOV @(R0, Rm), FRn
82 1111(FRn:4)(FRm:4)0010 FMUL FRm, FRn
83 1111(FRn:4)01001101 FNEG FRn
84 1111101111111101 FRCHG
85 1111(FRn:3<<1)011111101 FSCA FPUL, FRn
86 1111001111111101 FSCHG
87 1111(FRn:4)01101101 FSQRT FRn
88 1111(FRn:4)01111101 FSRRA FRn
89 1111(FRn:4)00001101 FSTS FPUL, FRn
90 1111(FRn:4)(FRm:4)0001 FSUB FRm, FRn
91 1111(FRm:4)00111101 FTRC FRm, FPUL
92 1111(FVn:2)0111111101 FTRV XMTRX, FVn
93 0100(Rn:4)00101011 JMP @Rn
94 0100(Rn:4)00001011 JSR @Rn
95 0100(Rm:4)00011110 LDC Rm, GBR
96 0100(Rm:4)00001110 LDC Rm, SR
97 0100(Rm:4)00101110 LDC Rm, VBR
98 0100(Rm:4)00111110 LDC Rm, SSR
99 0100(Rm:4)00111010 LDC Rm, SGR
100 0100(Rm:4)01001110 LDC Rm, SPC
101 0100(Rm:4)11111010 LDC Rm, DBR
102 0100(Rm:4)1(Rn_BANK:3)1110 LDC Rm, Rn_BANK
103 0100(Rm:4)00010111 LDC.L @Rm+, GBR
104 0100(Rm:4)00000111 LDC.L @Rm+, SR
105 0100(Rm:4)00100111 LDC.L @Rm+, VBR
106 0100(Rm:4)00110111 LDC.L @Rm+, SSR
107 0100(Rm:4)00110110 LDC.L @Rm+, SGR
108 0100(Rm:4)01000111 LDC.L @Rm+, SPC
109 0100(Rm:4)11110110 LDC.L @Rm+, DBR
110 0100(Rm:4)1(Rn_BANK:3)0111 LDC.L @Rm+, Rn_BANK
111 0100(Rm:4)01101010 LDS Rm, FPSCR
112 0100(Rm:4)01100110 LDS.L @Rm+, FPSCR
113 0100(Rm:4)01011010 LDS Rm, FPUL
114 0100(Rm:4)01010110 LDS.L @Rm+, FPUL
115 0100(Rm:4)00001010 LDS Rm, MACH
116 0100(Rm:4)00000110 LDS.L @Rm+, MACH
117 0100(Rm:4)00011010 LDS Rm, MACL
118 0100(Rm:4)00010110 LDS.L @Rm+, MACL
119 0100(Rm:4)00101010 LDS Rm, PR
120 0100(Rm:4)00100110 LDS.L @Rm+, PR
121 0000000000111000 LDTLB
122 0000(Rn:4)(Rm:4)1111 MAC.L @Rm+, @Rn+
123 0100(Rn:4)(Rm:4)1111 MAC.W @Rm+, @Rn+
124 0110(Rn:4)(Rm:4)0011 MOV Rm, Rn
125 1110(Rn:4)(imm:8s) MOV #imm, Rn
126 0010(Rn:4)(Rm:4)0000 MOV.B Rm, @Rn
127 0010(Rn:4)(Rm:4)0100 MOV.B Rm, @-Rn
128 0000(Rn:4)(Rm:4)0100 MOV.B Rm, @(R0, Rn)
129 11000000(disp:8) MOV.B R0, @(disp, GBR)
130 10000000(Rn:4)(disp:4) MOV.B R0, @(disp, Rn)
131 0110(Rn:4)(Rm:4)0000 MOV.B @Rm, Rn
132 0110(Rn:4)(Rm:4)0100 MOV.B @Rm+, Rn
133 0000(Rn:4)(Rm:4)1100 MOV.B @(R0, Rm), Rn
134 11000100(disp:8) MOV.B @(disp, GBR), R0
135 10000100(Rm:4)(disp:4) MOV.B @(disp, Rm), R0
136 0010(Rn:4)(Rm:4)0010 MOV.L Rm, @Rn
137 0010(Rn:4)(Rm:4)0110 MOV.L Rm, @-Rn
138 0000(Rn:4)(Rm:4)0110 MOV.L Rm, @(R0, Rn)
139 11000010(disp:8<<2) MOV.L R0, @(disp, GBR)
140 0001(Rn:4)(Rm:4)(disp:4<<2) MOV.L Rm, @(disp, Rn)
141 0110(Rn:4)(Rm:4)0010 MOV.L @Rm, Rn
142 0110(Rn:4)(Rm:4)0110 MOV.L @Rm+, Rn
143 0000(Rn:4)(Rm:4)1110 MOV.L @(R0, Rm), Rn
144 11000110(disp:8<<2) MOV.L @(disp, GBR), R0
145 1101(Rn:4)(disp:8<<2) MOV.L @(disp, PC), Rn
146 0101(Rn:4)(Rm:4)(disp:4<<2) MOV.L @(disp, Rm), Rn
147 0010(Rn:4)(Rm:4)0001 MOV.W Rm, @Rn
148 0010(Rn:4)(Rm:4)0101 MOV.W Rm, @-Rn
149 0000(Rn:4)(Rm:4)0101 MOV.W Rm, @(R0, Rn)
150 11000001(disp:8<<1) MOV.W R0, @(disp, GBR)
151 10000001(Rn:4)(disp:4<<1) MOV.W R0, @(disp, Rn)
152 0110(Rn:4)(Rm:4)0001 MOV.W @Rm, Rn
153 0110(Rn:4)(Rm:4)0101 MOV.W @Rm+, Rn
154 0000(Rn:4)(Rm:4)1101 MOV.W @(R0, Rm), Rn
155 11000101(disp:8<<1) MOV.W @(disp, GBR), R0
156 1001(Rn:4)(disp:8<<1) MOV.W @(disp, PC), Rn
157 10000101(Rm:4)(disp:4<<1) MOV.W @(disp, Rm), R0
158 11000111(disp:8<<2) MOVA @(disp, PC), R0
159 0000(Rn:4)11000011 MOVCA.L R0, @Rn
160 0000(Rn:4)00101001 MOVT Rn
161 0000(Rn:4)(Rm:4)0111 MUL.L Rm, Rn
162 0010(Rn:4)(Rm:4)1111 MULS.W Rm, Rn
163 0010(Rn:4)(Rm:4)1110 MULU.W Rm, Rn
164 0110(Rn:4)(Rm:4)1011 NEG Rm, Rn
165 0110(Rn:4)(Rm:4)1010 NEGC Rm, Rn
166 0000000000001001 NOP
167 0110(Rn:4)(Rm:4)0111 NOT Rm, Rn
168 0000(Rn:4)10010011 OCBI @Rn
169 0000(Rn:4)10100011 OCBP @Rn
170 0000(Rn:4)10110011 OCBWB @Rn
171 0010(Rn:4)(Rm:4)1011 OR Rm, Rn
172 11001011(imm:8) OR #imm, R0
173 11001111(imm:8) OR.B #imm, @(R0, GBR)
174 0000(Rn:4)10000011 PREF @Rn
175 0100(Rn:4)00100100 ROTCL Rn
176 0100(Rn:4)00100101 ROTCR Rn
177 0100(Rn:4)00000100 ROTL Rn
178 0100(Rn:4)00000101 ROTR Rn
179 0000000000101011 RTE
180 0000000000001011 RTS
181 0000000001011000 SETS
182 0000000000011000 SETT
183 0100(Rn:4)(Rm:4)1100 SHAD Rm, Rn
184 0100(Rn:4)00100000 SHAL Rn
185 0100(Rn:4)00100001 SHAR Rn
186 0100(Rn:4)(Rm:4)1101 SHLD Rm, Rn
187 0100(Rn:4)00000000 SHLL Rn
188 0100(Rn:4)00001000 SHLL2 Rn
189 0100(Rn:4)00011000 SHLL8 Rn
190 0100(Rn:4)00101000 SHLL16 Rn
191 0100(Rn:4)00000001 SHLR Rn
192 0100(Rn:4)00001001 SHLR2 Rn
193 0100(Rn:4)00011001 SHLR8 Rn
194 0100(Rn:4)00101001 SHLR16 Rn
195 0000000000011011 SLEEP
196 0000(Rn:4)00000010 STC SR, Rn
197 0000(Rn:4)00010010 STC GBR, Rn
198 0000(Rn:4)00100010 STC VBR, Rn
199 0000(Rn:4)00110010 STC SSR, Rn
200 0000(Rn:4)01000010 STC SPC, Rn
201 0000(Rn:4)00111010 STC SGR, Rn
202 0000(Rn:4)11111010 STC DBR, Rn
203 0000(Rn:4)1(Rm_BANK:3)0010 STC Rm_BANK, Rn
204 0100(Rn:4)00000011 STC.L SR, @-Rn
205 0100(Rn:4)00100011 STC.L VBR, @-Rn
206 0100(Rn:4)00110011 STC.L SSR, @-Rn
207 0100(Rn:4)01000011 STC.L SPC, @-Rn
208 0100(Rn:4)00110010 STC.L SGR, @-Rn
209 0100(Rn:4)11110010 STC.L DBR, @-Rn
210 0100(Rn:4)1(Rm_BANK:3)0011 STC.L Rm_BANK, @-Rn
211 0100(Rn:4)00010011 STC.L GBR, @-Rn
212 0000(Rn:4)01101010 STS FPSCR, Rn
213 0100(Rn:4)01100010 STS.L FPSCR, @-Rn
214 0000(Rn:4)01011010 STS FPUL, Rn
215 0100(Rn:4)01010010 STS.L FPUL, @-Rn
216 0000(Rn:4)00001010 STS MACH, Rn
217 0100(Rn:4)00000010 STS.L MACH, @-Rn
218 0000(Rn:4)00011010 STS MACL, Rn
219 0100(Rn:4)00010010 STS.L MACL, @-Rn
220 0000(Rn:4)00101010 STS PR, Rn
221 0100(Rn:4)00100010 STS.L PR, @-Rn
222 0011(Rn:4)(Rm:4)1000 SUB Rm, Rn
223 0011(Rn:4)(Rm:4)1010 SUBC Rm, Rn
224 0011(Rn:4)(Rm:4)1011 SUBV Rm, Rn
225 0110(Rn:4)(Rm:4)1000 SWAP.B Rm, Rn
226 0110(Rn:4)(Rm:4)1001 SWAP.W Rm, Rn
227 0100(Rn:4)00011011 TAS.B @Rn
228 11000011(imm:8) TRAPA #imm
229 0010(Rn:4)(Rm:4)1000 TST Rm, Rn
230 11001000(imm:8) TST #imm, R0
231 11001100(imm:8) TST.B #imm, @(R0, GBR)
232 0010(Rn:4)(Rm:4)1010 XOR Rm, Rn
233 11001010(imm:8) XOR #imm, R0
234 11001110(imm:8) XOR.B #imm, @(R0, GBR)
235 0010(Rn:4)(Rm:4)1101 XTRCT Rm, Rn
236 1111111111111101 UNDEF
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