lxdream 0.9.1| filename | src/sh4/sh4mmio.h |
| changeset | 859:b941c703ccd6 |
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| author | nkeynes |
| date | Thu Dec 11 23:26:03 2008 +0000 (15 years ago) |
| permissions | -rw-r--r-- |
| last change | Disable the generational translation cache - I've got no evidence that it actually helps performance, and it simplifies things to get rid of it (in particular, translated code doesn't have to worry about being moved now). |
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1 /**
2 * $Id$
3 *
4 * MMIO region and supporting function declarations. Private to the sh4
5 * module.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #include "lxdream.h"
21 #include "mmio.h"
23 #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \
24 (!defined(MMIO_IMPL) && !defined(SH4MMIO_IFACE))
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
30 #ifdef MMIO_IMPL
31 #define SH4MMIO_IMPL
32 #else
33 #define SH4MMIO_IFACE
34 #endif
35 /* SH7750 onchip mmio devices */
37 MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
38 LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" )
39 LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" )
40 LONG_PORT( 0x008, TTB, PORT_MRW, UNDEFINED, "Translation table base" )
41 LONG_PORT( 0x00C, TEA, PORT_MRW, UNDEFINED, "TLB exception address" )
42 LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" )
43 BYTE_PORT( 0x014, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
44 BYTE_PORT( 0x018, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
45 LONG_PORT( 0x01C, CCR, PORT_MRW, 0, "Cache control register" )
46 LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" )
47 LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
48 LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" )
49 LONG_PORT( 0x02C, MMUUNK1, PORT_MRW, 0, "Unknown MMU/general register" )
50 LONG_PORT( 0x030, SH4VER, PORT_MRW, 0x040205C1, "SH4 version register (PVR)" ) /* Renamed to avoid naming conflict */
51 LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
52 LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
53 LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )
54 WORD_PORT( 0x084, PMCR1, PORT_MRW, 0, "Performance counter control 1" )
55 WORD_PORT( 0x088, PMCR2, PORT_MRW, 0, "Performance counter control 2" )
56 MMIO_REGION_END
58 /* Performance counter values (undocumented) */
59 MMIO_REGION_BEGIN( 0xFF100000, PMM, "Performance monitoring" )
60 LONG_PORT( 0x004, PMCTR1H, PORT_MR, 0, "Performance counter 1 High" )
61 LONG_PORT( 0x008, PMCTR1L, PORT_MR, 0, "Performance counter 1 Low" )
62 LONG_PORT( 0x00C, PMCTR2H, PORT_MR, 0, "Performance counter 2 High" )
63 LONG_PORT( 0x010, PMCTR2L, PORT_MR, 0, "Performance counter 2 Low" )
64 MMIO_REGION_END
66 /* User Break Controller (Page 717 [757] of sh7750h manual) */
67 MMIO_REGION_BEGIN( 0xFF200000, UBC, "User Break Controller" )
68 LONG_PORT( 0x000, BARA, PORT_MRW, UNDEFINED, "Break address A" )
69 BYTE_PORT( 0x004, BAMRA, PORT_MRW, UNDEFINED, "Break address mask A" )
70 WORD_PORT( 0x008, BBRA, PORT_MRW, 0, "Break bus cycle A" )
71 LONG_PORT( 0x00C, BARB, PORT_MRW, UNDEFINED, "Break address B" )
72 BYTE_PORT( 0x010, BAMRB, PORT_MRW, UNDEFINED, "Break address mask B" )
73 WORD_PORT( 0x014, BBRB, PORT_MRW, 0, "Break bus cycle B" )
74 LONG_PORT( 0x018, BDRB, PORT_MRW, UNDEFINED, "Break data B" )
75 LONG_PORT( 0x01C, BDMRB, PORT_MRW, UNDEFINED, "Break data mask B" )
76 WORD_PORT( 0x020, BRCR, PORT_MRW, 0, "Break control" )
77 MMIO_REGION_END
78 /* Bus State Controller (Page 293 [333] of sh7750h manual)
79 * I/O Ports */
80 MMIO_REGION_BEGIN( 0xFF800000, BSC, "Bus State Controller" )
81 LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "Bus control 1" )
82 WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "Bus control 2" )
83 LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "Wait state control 1" )
84 LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "Wait state control 2" )
85 LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "Wait state control 3" )
86 LONG_PORT( 0x014, MCR, PORT_MRW, 0, "Memory control register" )
87 WORD_PORT( 0x018, PCR, PORT_MRW, 0, "PCMCIA control register" )
88 WORD_PORT( 0x01C, RTCSR, PORT_MRW, 0, "Refresh timer control/status" )
89 WORD_PORT( 0x020, RTCNT, PORT_MRW, 0, "Refresh timer counter" )
90 WORD_PORT( 0x024, RTCOR, PORT_MRW, 0, "Refresh timer constant" )
91 WORD_PORT( 0x028, RFCR, PORT_MRW, 0, "Refresh count" )
92 LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" )
93 WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" )
94 LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" )
95 WORD_PORT( 0x044, PDTRB, PORT_RW, UNDEFINED, "Port data register B" )
96 WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
97 MMIO_REGION_END
99 /* DMA Controller (Page 457 [497] of sh7750h manual) */
100 MMIO_REGION_BEGIN( 0xFFA00000, DMAC, "DMA Controller" )
101 LONG_PORT( 0x000, SAR0, PORT_MRW, UNDEFINED, "DMA source address 0" )
102 LONG_PORT( 0x004, DAR0, PORT_MRW, UNDEFINED, "DMA destination address 0" )
103 LONG_PORT( 0x008, DMATCR0, PORT_MRW, UNDEFINED, "DMA transfer count 0" )
104 LONG_PORT( 0x00C, CHCR0, PORT_MRW, 0, "DMA channel control 0" )
105 LONG_PORT( 0x010, SAR1, PORT_MRW, UNDEFINED, "DMA source address 1" )
106 LONG_PORT( 0x014, DAR1, PORT_MRW, UNDEFINED, "DMA destination address 1" )
107 LONG_PORT( 0x018, DMATCR1, PORT_MRW, UNDEFINED, "DMA transfer count 1" )
108 LONG_PORT( 0x01C, CHCR1, PORT_MRW, 0, "DMA channel control 1" )
109 LONG_PORT( 0x020, SAR2, PORT_MRW, UNDEFINED, "DMA source address 2" )
110 LONG_PORT( 0x024, DAR2, PORT_MRW, UNDEFINED, "DMA destination address 2" )
111 LONG_PORT( 0x028, DMATCR2, PORT_MRW, UNDEFINED, "DMA transfer count 2" )
112 LONG_PORT( 0x02C, CHCR2, PORT_MRW, 0, "DMA channel control 2" )
113 LONG_PORT( 0x030, SAR3, PORT_MRW, UNDEFINED, "DMA source address 3" )
114 LONG_PORT( 0x034, DAR3, PORT_MRW, UNDEFINED, "DMA destination address 3" )
115 LONG_PORT( 0x038, DMATCR3, PORT_MRW, UNDEFINED, "DMA transfer count 3" )
116 LONG_PORT( 0x03C, CHCR3, PORT_MRW, 0, "DMA channel control 3" )
117 LONG_PORT( 0x040, DMAOR, PORT_MRW, 0, "DMA operation register" )
118 MMIO_REGION_END
120 #define FRQCR_CKOEN 0x0800
121 #define FRQCR_PLL1EN 0x0400
122 #define FRQCR_PLL2EN 0x0200
123 #define FRQCR_IFC_MASK 0x01C0
124 #define FRQCR_BFC_MASK 0x0038
125 #define FRQCR_PFC_MASK 0x0007
127 /* Clock Pulse Generator (page 233 [273] of sh7750h manual) */
128 MMIO_REGION_BEGIN( 0xFFC00000, CPG, "Clock Pulse Generator" )
129 WORD_PORT( 0x000, FRQCR, PORT_MRW, 0x0E0A, "Frequency control" )
130 BYTE_PORT( 0x004, STBCR, PORT_MRW, 0, "Standby control" )
131 BYTE_PORT( 0x008, WTCNT, PORT_MRW, 0, "Watchdog timer counter" )
132 BYTE_PORT( 0x00C, WTCSR, PORT_MRW, 0, "Watchdog timer control/status" )
133 BYTE_PORT( 0x010, STBCR2, PORT_MRW, 0, "Standby control 2" )
134 MMIO_REGION_END
136 /* Real time clock (Page 253 [293] of sh7750h manual) */
137 MMIO_REGION_BEGIN( 0xFFC80000, RTC, "Realtime Clock" )
138 BYTE_PORT( 0x000, R64CNT, PORT_R, UNDEFINED, "64 Hz counter" )
139 BYTE_PORT( 0x004, RSECCNT, PORT_MRW, UNDEFINED, "Second counter" )
140 /* ... */
141 MMIO_REGION_END
143 /* Interrupt controller (Page 699 [739] of sh7750h manual) */
144 MMIO_REGION_BEGIN( 0xFFD00000, INTC, "Interrupt Controller" )
145 WORD_PORT( 0x000, ICR, PORT_MRW, 0x0000, "Interrupt control register" )
146 WORD_PORT( 0x004, IPRA, PORT_MRW, 0x0000, "Interrupt priority register A" )
147 WORD_PORT( 0x008, IPRB, PORT_MRW, 0x0000, "Interrupt priority register B" )
148 WORD_PORT( 0x00C, IPRC, PORT_MRW, 0x0000, "Interrupt priority register C" )
149 WORD_PORT( 0x010, IPRD, PORT_MRW, 0xDA74, "Interrupt priority register D" )
150 MMIO_REGION_END
152 /* Timer unit (Page 277 [317] of sh7750h manual) */
153 MMIO_REGION_BEGIN( 0xFFD80000, TMU, "Timer Unit" )
154 BYTE_PORT( 0x000, TOCR, PORT_MRW, 0x00, "Timer output control register" )
155 BYTE_PORT( 0x004, TSTR, PORT_MRW, 0x00, "Timer start register" )
156 LONG_PORT( 0x008, TCOR0, PORT_MRW, 0xFFFFFFFF, "Timer constant 0" )
157 LONG_PORT( 0x00C, TCNT0, PORT_MRW, 0xFFFFFFFF, "Timer counter 0" )
158 WORD_PORT( 0x010, TCR0, PORT_MRW, 0x0000, "Timer control 0" )
159 LONG_PORT( 0x014, TCOR1, PORT_MRW, 0xFFFFFFFF, "Timer constant 1" )
160 LONG_PORT( 0x018, TCNT1, PORT_MRW, 0xFFFFFFFF, "Timer counter 1" )
161 WORD_PORT( 0x01C, TCR1, PORT_MRW, 0x0000, "Timer control 1" )
162 LONG_PORT( 0x020, TCOR2, PORT_MRW, 0xFFFFFFFF, "Timer constant 2" )
163 LONG_PORT( 0x024, TCNT2, PORT_MRW, 0xFFFFFFFF, "Timer counter 2" )
164 WORD_PORT( 0x028, TCR2, PORT_MRW, 0x0000, "Timer control 2" )
165 LONG_PORT( 0x02C, TCPR2, PORT_R, UNDEFINED, "Input capture register" )
166 MMIO_REGION_END
168 /* Serial channel (page 541 [581] of sh7750h manual) */
169 MMIO_REGION_BEGIN( 0xFFE00000, SCI, "Serial Communication Interface" )
170 BYTE_PORT( 0x000, SCSMR1, PORT_MRW, 0x00, "Serial mode register" )
171 BYTE_PORT( 0x004, SCBRR1, PORT_MRW, 0xFF, "Bit rate register" )
172 BYTE_PORT( 0x008, SCSCR1, PORT_MRW, 0x00, "Serial control register" )
173 BYTE_PORT( 0x00C, SCTDR1, PORT_MRW, 0xFF, "Transmit data register" )
174 BYTE_PORT( 0x010, SCSSR1, PORT_MRW, 0x84, "Serial status register" )
175 BYTE_PORT( 0x014, SCRDR1, PORT_R, 0x00, "Receive data register" )
176 BYTE_PORT( 0x01C, SCSPTR1, PORT_MRW, 0x00, "Serial port register" )
177 MMIO_REGION_END
179 MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" )
180 WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" )
181 BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" )
182 WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" )
183 BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" )
184 WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)" )
185 BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" )
186 WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" )
187 WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" )
188 WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" )
189 WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" )
190 MMIO_REGION_END
192 MMIO_REGION_LIST_BEGIN( sh4mmio )
193 MMIO_REGION( MMU )
194 MMIO_REGION( UBC )
195 MMIO_REGION( BSC )
196 MMIO_REGION( DMAC )
197 MMIO_REGION( CPG )
198 MMIO_REGION( RTC )
199 MMIO_REGION( INTC )
200 MMIO_REGION( TMU )
201 MMIO_REGION( SCI )
202 MMIO_REGION( SCIF )
203 MMIO_REGION( PMM )
204 MMIO_REGION_LIST_END
206 /* mmucr register bits */
207 #define MMUCR_AT 0x00000001 /* Address Translation enabled */
208 #define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */
209 #define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
210 #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
211 #define MMUCR_URC 0x0000FC00 /* UTLB access counter */
212 #define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */
213 #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
214 #define MMUCR_MASK 0xFCFCFF05
215 #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
217 #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
219 /* ccr register bits */
220 #define CCR_IIX 0x00008000 /* IC index enable */
221 #define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */
222 #define CCR_ICE 0x00000100 /* IC enable */
223 #define CCR_OIX 0x00000080 /* OC index enable */
224 #define CCR_ORA 0x00000020 /* OC RAM enable */
225 #define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */
226 #define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */
227 #define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */
228 #define CCR_OCE 0x00000001 /* OC enable */
229 #define CCR_MASK 0x000089AF
230 #define CCR_RMASK 0x000081A7 /* Read mask */
232 #define MEM_OC_INDEX0 (CCR_ORA|CCR_OCE)
233 #define MEM_OC_INDEX1 (CCR_ORA|CCR_OIX|CCR_OCE)
235 #define PMCR_CLKF 0x0100
236 #define PMCR_PMCLR 0x2000
237 #define PMCR_PMST 0x4000
238 #define PMCR_PMEN 0x8000
239 #define PMCR_RUNNING (PMCR_PMST|PMCR_PMEN)
241 /* MMU functions */
242 void mmu_init(void);
243 void mmu_set_cache_mode( int );
244 void mmu_ldtlb(void);
246 int32_t mmu_icache_addr_read( sh4addr_t addr );
247 int32_t mmu_icache_data_read( sh4addr_t addr );
248 int32_t mmu_itlb_addr_read( sh4addr_t addr );
249 int32_t mmu_itlb_data_read( sh4addr_t addr );
250 int32_t mmu_ocache_addr_read( sh4addr_t addr );
251 int32_t mmu_ocache_data_read( sh4addr_t addr );
252 int32_t mmu_utlb_addr_read( sh4addr_t addr );
253 int32_t mmu_utlb_data_read( sh4addr_t addr );
254 void mmu_icache_addr_write( sh4addr_t addr, uint32_t val );
255 void mmu_icache_data_write( sh4addr_t addr, uint32_t val );
256 void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val );
257 void mmu_itlb_data_write( sh4addr_t addr, uint32_t val );
258 void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val );
259 void mmu_ocache_data_write( sh4addr_t addr, uint32_t val );
260 void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val );
261 void mmu_utlb_data_write( sh4addr_t addr, uint32_t val );
264 #ifdef __cplusplus
265 }
266 #endif
268 #endif
.