2 * $Id: sh4core.in,v 1.4 2007-09-11 02:14:46 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 #define EXV_EXCEPTION 0x100 /* General exception vector */
38 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
39 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
41 /********************** SH4 Module Definition ****************************/
43 void sh4_init( void );
44 void sh4_reset( void );
45 uint32_t sh4_run_slice( uint32_t );
46 void sh4_start( void );
47 void sh4_stop( void );
48 void sh4_save_state( FILE *f );
49 int sh4_load_state( FILE *f );
50 void sh4_accept_interrupt( void );
52 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
53 NULL, sh4_run_slice, sh4_stop,
54 sh4_save_state, sh4_load_state };
56 struct sh4_registers sh4r;
60 register_io_regions( mmio_list_sh4mmio );
67 /* zero everything out, for the sake of having a consistent state. */
68 memset( &sh4r, 0, sizeof(sh4r) );
70 /* Resume running if we were halted */
71 sh4r.sh4_state = SH4_STATE_RUNNING;
74 sh4r.new_pc= 0xA0000002;
75 sh4r.vbr = 0x00000000;
76 sh4r.fpscr = 0x00040001;
78 sh4r.fr_bank = &sh4r.fr[0][0];
80 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
81 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
83 /* Peripheral modules */
91 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
92 static int sh4_breakpoint_count = 0;
93 static uint16_t *sh4_icache = NULL;
94 static uint32_t sh4_icache_addr = 0;
96 void sh4_set_breakpoint( uint32_t pc, int type )
98 sh4_breakpoints[sh4_breakpoint_count].address = pc;
99 sh4_breakpoints[sh4_breakpoint_count].type = type;
100 sh4_breakpoint_count++;
103 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
107 for( i=0; i<sh4_breakpoint_count; i++ ) {
108 if( sh4_breakpoints[i].address == pc &&
109 sh4_breakpoints[i].type == type ) {
110 while( ++i < sh4_breakpoint_count ) {
111 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
112 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
114 sh4_breakpoint_count--;
121 int sh4_get_breakpoint( uint32_t pc )
124 for( i=0; i<sh4_breakpoint_count; i++ ) {
125 if( sh4_breakpoints[i].address == pc )
126 return sh4_breakpoints[i].type;
131 uint32_t sh4_run_slice( uint32_t nanosecs )
134 sh4r.slice_cycle = 0;
136 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
137 if( sh4r.event_pending < nanosecs ) {
138 sh4r.sh4_state = SH4_STATE_RUNNING;
139 sh4r.slice_cycle = sh4r.event_pending;
143 if( sh4_breakpoint_count == 0 ) {
144 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
145 if( SH4_EVENT_PENDING() ) {
146 if( sh4r.event_types & PENDING_EVENT ) {
149 /* Eventq execute may (quite likely) deliver an immediate IRQ */
150 if( sh4r.event_types & PENDING_IRQ ) {
151 sh4_accept_interrupt();
154 if( !sh4_execute_instruction() ) {
159 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
160 if( SH4_EVENT_PENDING() ) {
161 if( sh4r.event_types & PENDING_EVENT ) {
164 /* Eventq execute may (quite likely) deliver an immediate IRQ */
165 if( sh4r.event_types & PENDING_IRQ ) {
166 sh4_accept_interrupt();
170 if( !sh4_execute_instruction() )
172 #ifdef ENABLE_DEBUG_MODE
173 for( i=0; i<sh4_breakpoint_count; i++ ) {
174 if( sh4_breakpoints[i].address == sh4r.pc ) {
178 if( i != sh4_breakpoint_count ) {
180 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
181 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
188 /* If we aborted early, but the cpu is still technically running,
189 * we're doing a hard abort - cut the timeslice back to what we
192 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
193 nanosecs = sh4r.slice_cycle;
195 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
196 TMU_run_slice( nanosecs );
197 SCIF_run_slice( nanosecs );
207 void sh4_save_state( FILE *f )
209 fwrite( &sh4r, sizeof(sh4r), 1, f );
211 INTC_save_state( f );
213 SCIF_save_state( f );
216 int sh4_load_state( FILE * f )
218 fread( &sh4r, sizeof(sh4r), 1, f );
220 INTC_load_state( f );
222 return SCIF_load_state( f );
225 /********************** SH4 emulation core ****************************/
227 void sh4_set_pc( int pc )
233 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
234 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
236 #if(SH4_CALLTRACE == 1)
237 #define MAX_CALLSTACK 32
238 static struct call_stack {
240 sh4addr_t target_addr;
241 sh4addr_t stack_pointer;
242 } call_stack[MAX_CALLSTACK];
244 static int call_stack_depth = 0;
245 int sh4_call_trace_on = 0;
247 static inline trace_call( sh4addr_t source, sh4addr_t dest )
249 if( call_stack_depth < MAX_CALLSTACK ) {
250 call_stack[call_stack_depth].call_addr = source;
251 call_stack[call_stack_depth].target_addr = dest;
252 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
257 static inline trace_return( sh4addr_t source, sh4addr_t dest )
259 if( call_stack_depth > 0 ) {
264 void fprint_stack_trace( FILE *f )
266 int i = call_stack_depth -1;
267 if( i >= MAX_CALLSTACK )
268 i = MAX_CALLSTACK - 1;
269 for( ; i >= 0; i-- ) {
270 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
271 (call_stack_depth - i), call_stack[i].call_addr,
272 call_stack[i].target_addr, call_stack[i].stack_pointer );
276 #define TRACE_CALL( source, dest ) trace_call(source, dest)
277 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
279 #define TRACE_CALL( dest, rts )
280 #define TRACE_RETURN( source, dest )
283 #define RAISE( x, v ) do{ \
284 if( sh4r.vbr == 0 ) { \
285 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
286 dreamcast_stop(); return FALSE; \
288 sh4r.spc = sh4r.pc; \
289 sh4r.ssr = sh4_read_sr(); \
290 sh4r.sgr = sh4r.r[15]; \
291 MMIO_WRITE(MMU,EXPEVT,x); \
292 sh4r.pc = sh4r.vbr + v; \
293 sh4r.new_pc = sh4r.pc + 2; \
294 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
295 if( sh4r.in_delay_slot ) { \
296 sh4r.in_delay_slot = 0; \
300 return TRUE; } while(0)
302 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
303 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
304 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
305 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
306 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
307 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
309 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
311 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
312 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
314 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
315 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
316 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
317 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
318 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
320 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
321 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
322 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
324 static void sh4_switch_banks( )
328 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
329 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
330 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
333 void sh4_write_sr( uint32_t newval )
335 if( (newval ^ sh4r.sr) & SR_RB )
338 sh4r.t = (newval&SR_T) ? 1 : 0;
339 sh4r.s = (newval&SR_S) ? 1 : 0;
340 sh4r.m = (newval&SR_M) ? 1 : 0;
341 sh4r.q = (newval&SR_Q) ? 1 : 0;
345 static void sh4_write_float( uint32_t addr, int reg )
347 if( IS_FPU_DOUBLESIZE() ) {
349 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
350 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
352 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
353 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
356 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
360 static void sh4_read_float( uint32_t addr, int reg )
362 if( IS_FPU_DOUBLESIZE() ) {
364 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
365 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
367 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
368 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
371 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
375 uint32_t sh4_read_sr( void )
377 /* synchronize sh4r.sr with the various bitflags */
378 sh4r.sr &= SR_MQSTMASK;
379 if( sh4r.t ) sh4r.sr |= SR_T;
380 if( sh4r.s ) sh4r.sr |= SR_S;
381 if( sh4r.m ) sh4r.sr |= SR_M;
382 if( sh4r.q ) sh4r.sr |= SR_Q;
387 * Raise a general CPU exception for the specified exception code.
388 * (NOT for TRAPA or TLB exceptions)
390 gboolean sh4_raise_exception( int code )
392 RAISE( code, EXV_EXCEPTION );
395 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
396 if( sh4r.in_delay_slot ) {
397 return sh4_raise_exception(slot_code);
399 return sh4_raise_exception(normal_code);
403 gboolean sh4_raise_tlb_exception( int code )
405 RAISE( code, EXV_TLBMISS );
408 void sh4_accept_interrupt( void )
410 uint32_t code = intc_accept_interrupt();
411 sh4r.ssr = sh4_read_sr();
413 sh4r.sgr = sh4r.r[15];
414 sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
415 MMIO_WRITE( MMU, INTEVT, code );
416 sh4r.pc = sh4r.vbr + 0x600;
417 sh4r.new_pc = sh4r.pc + 2;
418 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
421 gboolean sh4_execute_instruction( void )
431 if( pc > 0xFFFFFF00 ) {
433 syscall_invoke( pc );
434 sh4r.in_delay_slot = 0;
435 pc = sh4r.pc = sh4r.pr;
436 sh4r.new_pc = sh4r.pc + 2;
440 /* Read instruction */
441 uint32_t pageaddr = pc >> 12;
442 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
443 ir = sh4_icache[(pc&0xFFF)>>1];
445 sh4_icache = (uint16_t *)mem_get_page(pc);
446 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
447 /* If someone's actually been so daft as to try to execute out of an IO
448 * region, fallback on the full-blown memory read
451 ir = MEM_READ_WORD(pc);
453 sh4_icache_addr = pageaddr;
454 ir = sh4_icache[(pc&0xFFF)>>1];
458 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
459 AND #imm, R0 {: R0 &= imm; :}
460 AND.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
461 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
462 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
463 OR #imm, R0 {: R0 |= imm; :}
464 OR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
466 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
467 sh4r.t = ( tmp == 0 ? 1 : 0 );
468 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
470 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
471 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
472 TST.B #imm, @(R0, GBR) {: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); :}
473 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
474 XOR #imm, R0 {: R0 ^= imm; :}
475 XOR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
476 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
479 sh4r.t = sh4r.r[Rn] >> 31;
481 sh4r.r[Rn] |= sh4r.t;
484 sh4r.t = sh4r.r[Rn] & 0x00000001;
486 sh4r.r[Rn] |= (sh4r.t << 31);
489 tmp = sh4r.r[Rn] >> 31;
491 sh4r.r[Rn] |= sh4r.t;
495 tmp = sh4r.r[Rn] & 0x00000001;
497 sh4r.r[Rn] |= (sh4r.t << 31 );
502 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
503 else if( (tmp & 0x1F) == 0 )
504 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
506 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
510 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
511 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
512 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
515 sh4r.t = sh4r.r[Rn] >> 31;
519 sh4r.t = sh4r.r[Rn] & 0x00000001;
520 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
522 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
523 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
524 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
525 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
526 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
527 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
528 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
529 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
531 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
532 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
533 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
534 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
535 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
536 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
538 CLRT {: sh4r.t = 0; :}
539 SETT {: sh4r.t = 1; :}
540 CLRMAC {: sh4r.mac = 0; :}
541 LDTLB {: /* TODO */ :}
542 CLRS {: sh4r.s = 0; :}
543 SETS {: sh4r.s = 1; :}
544 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
549 if( (tmp & 0xFC000000) == 0xE0000000 ) {
550 sh4_flush_store_queue(tmp);
559 MEM_WRITE_LONG( tmp, R0 );
561 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
562 MOV.W Rm, @(R0, Rn) {:
563 CHECKWALIGN16( R0 + sh4r.r[Rn] );
564 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
566 MOV.L Rm, @(R0, Rn) {:
567 CHECKWALIGN32( R0 + sh4r.r[Rn] );
568 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
570 MOV.B @(R0, Rm), Rn {: sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); :}
571 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
572 sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
574 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
575 sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
577 MOV.L Rm, @(disp, Rn) {:
578 tmp = sh4r.r[Rn] + disp;
579 CHECKWALIGN32( tmp );
580 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
582 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
583 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
584 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
585 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
586 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
587 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
588 MOV.L @(disp, Rm), Rn {:
589 tmp = sh4r.r[Rm] + disp;
590 CHECKRALIGN32( tmp );
591 sh4r.r[Rn] = MEM_READ_LONG( tmp );
593 MOV.B @Rm, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); :}
594 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); :}
595 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); :}
596 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
597 MOV.B @Rm+, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; :}
598 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; :}
599 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; :}
600 MOV.L @(disp, PC), Rn {:
602 tmp = (pc&0xFFFFFFFC) + disp + 4;
603 sh4r.r[Rn] = MEM_READ_LONG( tmp );
605 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
606 MOV.W R0, @(disp, GBR) {:
607 tmp = sh4r.gbr + disp;
608 CHECKWALIGN16( tmp );
609 MEM_WRITE_WORD( tmp, R0 );
611 MOV.L R0, @(disp, GBR) {:
612 tmp = sh4r.gbr + disp;
613 CHECKWALIGN32( tmp );
614 MEM_WRITE_LONG( tmp, R0 );
616 MOV.B @(disp, GBR), R0 {: R0 = MEM_READ_BYTE( sh4r.gbr + disp ); :}
617 MOV.W @(disp, GBR), R0 {:
618 tmp = sh4r.gbr + disp;
619 CHECKRALIGN16( tmp );
620 R0 = MEM_READ_WORD( tmp );
622 MOV.L @(disp, GBR), R0 {:
623 tmp = sh4r.gbr + disp;
624 CHECKRALIGN32( tmp );
625 R0 = MEM_READ_LONG( tmp );
627 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
628 MOV.W R0, @(disp, Rn) {:
629 tmp = sh4r.r[Rn] + disp;
630 CHECKWALIGN16( tmp );
631 MEM_WRITE_WORD( tmp, R0 );
633 MOV.B @(disp, Rm), R0 {: R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); :}
634 MOV.W @(disp, Rm), R0 {:
635 tmp = sh4r.r[Rm] + disp;
636 CHECKRALIGN16( tmp );
637 R0 = MEM_READ_WORD( tmp );
639 MOV.W @(disp, PC), Rn {:
642 sh4r.r[Rn] = MEM_READ_WORD( tmp );
644 MOVA @(disp, PC), R0 {:
646 R0 = (pc&0xFFFFFFFC) + disp + 4;
648 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
650 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
651 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
652 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
653 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
654 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
655 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
656 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
657 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
659 /* set T = 1 if any byte in RM & RN is the same */
660 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
661 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
662 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
665 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
666 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
669 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
670 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
673 tmp = sh4r.r[Rn] + sh4r.r[Rm];
674 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
677 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
679 sh4r.q = sh4r.r[Rn]>>31;
680 sh4r.m = sh4r.r[Rm]>>31;
681 sh4r.t = sh4r.q ^ sh4r.m;
684 /* This is just from the sh4p manual with some
685 * simplifications (someone want to check it's correct? :)
686 * Why they couldn't just provide a real DIV instruction...
688 uint32_t tmp0, tmp1, tmp2, dir;
690 dir = sh4r.q ^ sh4r.m;
691 sh4r.q = (sh4r.r[Rn] >> 31);
693 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
697 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
700 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
702 sh4r.q ^= sh4r.m ^ tmp1;
703 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
705 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
706 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
709 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
712 CHECKRALIGN16( sh4r.r[Rn] );
713 CHECKRALIGN16( sh4r.r[Rm] );
714 int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
716 stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
719 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
720 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
721 sh4r.mac = 0x000000017FFFFFFFLL;
722 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
723 sh4r.mac = 0x0000000180000000LL;
725 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
726 ((uint32_t)(sh4r.mac + stmp));
729 sh4r.mac += SIGNEXT32(stmp);
733 CHECKRALIGN32( sh4r.r[Rm] );
734 CHECKRALIGN32( sh4r.r[Rn] );
735 int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
737 tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
740 /* 48-bit Saturation. Yuch */
741 if( tmpl < (int64_t)0xFFFF800000000000LL )
742 tmpl = 0xFFFF800000000000LL;
743 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
744 tmpl = 0x00007FFFFFFFFFFFLL;
748 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
749 (sh4r.r[Rm] * sh4r.r[Rn]); :}
751 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
752 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
755 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
756 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
759 tmp = 0 - sh4r.r[Rm];
760 sh4r.r[Rn] = tmp - sh4r.t;
761 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
763 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
764 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
767 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
768 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
773 CHECKDEST( pc + 4 + sh4r.r[Rn] );
774 sh4r.in_delay_slot = 1;
775 sh4r.pc = sh4r.new_pc;
776 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
781 CHECKDEST( pc + 4 + sh4r.r[Rn] );
782 sh4r.in_delay_slot = 1;
783 sh4r.pr = sh4r.pc + 4;
784 sh4r.pc = sh4r.new_pc;
785 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
786 TRACE_CALL( pc, sh4r.new_pc );
792 CHECKDEST( sh4r.pc + disp + 4 )
794 sh4r.new_pc = sh4r.pc + 2;
801 CHECKDEST( sh4r.pc + disp + 4 )
803 sh4r.new_pc = sh4r.pc + 2;
810 CHECKDEST( sh4r.pc + disp + 4 )
811 sh4r.in_delay_slot = 1;
812 sh4r.pc = sh4r.new_pc;
813 sh4r.new_pc = pc + disp + 4;
814 sh4r.in_delay_slot = 1;
821 CHECKDEST( sh4r.pc + disp + 4 )
822 sh4r.in_delay_slot = 1;
823 sh4r.pc = sh4r.new_pc;
824 sh4r.new_pc = pc + disp + 4;
830 CHECKDEST( sh4r.pc + disp + 4 );
831 sh4r.in_delay_slot = 1;
832 sh4r.pc = sh4r.new_pc;
833 sh4r.new_pc = pc + 4 + disp;
837 CHECKDEST( sh4r.pc + disp + 4 );
839 sh4r.in_delay_slot = 1;
841 sh4r.pc = sh4r.new_pc;
842 sh4r.new_pc = pc + 4 + disp;
843 TRACE_CALL( pc, sh4r.new_pc );
848 MMIO_WRITE( MMU, TRA, imm<<2 );
850 sh4_raise_exception( EXC_TRAP );
854 CHECKDEST( sh4r.pr );
855 sh4r.in_delay_slot = 1;
856 sh4r.pc = sh4r.new_pc;
857 sh4r.new_pc = sh4r.pr;
858 TRACE_RETURN( pc, sh4r.new_pc );
862 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
863 sh4r.sh4_state = SH4_STATE_STANDBY;
865 sh4r.sh4_state = SH4_STATE_SLEEP;
867 return FALSE; /* Halt CPU */
871 CHECKDEST( sh4r.spc );
873 sh4r.in_delay_slot = 1;
874 sh4r.pc = sh4r.new_pc;
875 sh4r.new_pc = sh4r.spc;
876 sh4_write_sr( sh4r.ssr );
880 CHECKDEST( sh4r.r[Rn] );
882 sh4r.in_delay_slot = 1;
883 sh4r.pc = sh4r.new_pc;
884 sh4r.new_pc = sh4r.r[Rn];
888 CHECKDEST( sh4r.r[Rn] );
890 sh4r.in_delay_slot = 1;
891 sh4r.pc = sh4r.new_pc;
892 sh4r.new_pc = sh4r.r[Rn];
894 TRACE_CALL( pc, sh4r.new_pc );
897 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
900 CHECKWALIGN32( sh4r.r[Rn] );
901 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
906 CHECKWALIGN32( sh4r.r[Rn] );
907 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
910 CHECKRALIGN32( sh4r.r[Rm] );
911 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
912 (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
918 CHECKWALIGN32( sh4r.r[Rm] );
919 sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );
923 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
924 (((uint64_t)sh4r.r[Rm])<<32);
929 sh4_write_sr( sh4r.r[Rm] );
933 sh4r.sgr = sh4r.r[Rm];
937 CHECKRALIGN32( sh4r.r[Rm] );
938 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
941 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
944 CHECKWALIGN32( sh4r.r[Rn] );
945 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
949 CHECKWALIGN32( sh4r.r[Rn] );
950 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
953 CHECKRALIGN32( sh4r.r[Rm] );
954 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
955 (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
959 CHECKRALIGN32( sh4r.r[Rm] );
960 sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
964 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
965 (uint64_t)((uint32_t)(sh4r.r[Rm]));
967 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
968 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
971 CHECKWALIGN32( sh4r.r[Rn] );
972 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
977 CHECKWALIGN32( sh4r.r[Rn] );
978 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
981 CHECKRALIGN32( sh4r.r[Rm] );
982 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
987 CHECKRALIGN32( sh4r.r[Rm] );
988 sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
991 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
994 sh4r.vbr = sh4r.r[Rm];
998 sh4r.r[Rn] = sh4r.sgr;
1003 CHECKWALIGN32( sh4r.r[Rn] );
1004 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
1009 CHECKWALIGN32( sh4r.r[Rn] );
1010 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
1014 CHECKRALIGN32( sh4r.r[Rm] );
1015 sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
1020 sh4r.ssr = sh4r.r[Rm];
1025 CHECKWALIGN32( sh4r.r[Rn] );
1026 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
1030 CHECKRALIGN32( sh4r.r[Rm] );
1031 sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
1036 sh4r.spc = sh4r.r[Rm];
1038 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
1041 CHECKWALIGN32( sh4r.r[Rn] );
1042 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
1045 CHECKRALIGN32( sh4r.r[Rm] );
1046 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
1049 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
1050 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
1051 STS.L FPSCR, @-Rn {:
1053 CHECKWALIGN32( sh4r.r[Rn] );
1054 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
1056 LDS.L @Rm+, FPSCR {:
1057 CHECKRALIGN32( sh4r.r[Rm] );
1058 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
1060 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1063 sh4r.fpscr = sh4r.r[Rm];
1064 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1066 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
1070 CHECKWALIGN32( sh4r.r[Rn] );
1071 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
1075 CHECKRALIGN32( sh4r.r[Rm] );
1076 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
1081 sh4r.dbr = sh4r.r[Rm];
1083 STC.L Rm_BANK, @-Rn {:
1086 CHECKWALIGN32( sh4r.r[Rn] );
1087 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
1089 LDC.L @Rm+, Rn_BANK {:
1091 CHECKRALIGN32( sh4r.r[Rm] );
1092 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
1097 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
1101 sh4r.r[Rn] = sh4_read_sr();
1105 sh4r.r[Rn] = sh4r.gbr;
1109 sh4r.r[Rn] = sh4r.vbr;
1113 sh4r.r[Rn] = sh4r.ssr;
1117 sh4r.r[Rn] = sh4r.spc;
1121 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
1126 if( IS_FPU_DOUBLEPREC() ) {
1134 if( IS_FPU_DOUBLEPREC() ) {
1143 if( IS_FPU_DOUBLEPREC() ) {
1152 if( IS_FPU_DOUBLEPREC() ) {
1161 if( IS_FPU_DOUBLEPREC() ) {
1162 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
1164 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
1170 if( IS_FPU_DOUBLEPREC() ) {
1171 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
1173 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
1177 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
1178 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
1179 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
1180 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
1181 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
1182 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
1184 if( IS_FPU_DOUBLESIZE() )
1189 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
1190 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
1193 if( IS_FPU_DOUBLEPREC() ) {
1194 if( FRn&1 ) { // No, really...
1195 dtmp = (double)FPULi;
1196 FR(FRn) = *(((float *)&dtmp)+1);
1198 DRF(FRn>>1) = (double)FPULi;
1201 FR(FRn) = (float)FPULi;
1206 if( IS_FPU_DOUBLEPREC() ) {
1209 *(((float *)&dtmp)+1) = FR(FRm);
1213 if( dtmp >= MAX_INTF )
1215 else if( dtmp <= MIN_INTF )
1218 FPULi = (int32_t)dtmp;
1221 if( ftmp >= MAX_INTF )
1223 else if( ftmp <= MIN_INTF )
1226 FPULi = (int32_t)ftmp;
1231 if( IS_FPU_DOUBLEPREC() ) {
1239 if( IS_FPU_DOUBLEPREC() ) {
1240 DR(FRn) = fabs(DR(FRn));
1242 FR(FRn) = fabsf(FR(FRn));
1247 if( IS_FPU_DOUBLEPREC() ) {
1248 DR(FRn) = sqrt(DR(FRn));
1250 FR(FRn) = sqrtf(FR(FRn));
1255 if( IS_FPU_DOUBLEPREC() ) {
1263 if( IS_FPU_DOUBLEPREC() ) {
1269 FMAC FR0, FRm, FRn {:
1271 if( IS_FPU_DOUBLEPREC() ) {
1272 DR(FRn) += DR(FRm)*DR(0);
1274 FR(FRn) += FR(FRm)*FR(0);
1279 sh4r.fpscr ^= FPSCR_FR;
1280 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1282 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1285 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1286 DR(FRn) = (double)FPULf;
1291 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1292 FPULf = (float)DR(FRm);
1298 if( !IS_FPU_DOUBLEPREC() ) {
1299 FR(FRn) = 1.0/sqrtf(FR(FRn));
1304 if( !IS_FPU_DOUBLEPREC() ) {
1307 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1308 FR(tmp+1)*FR(tmp2+1) +
1309 FR(tmp+2)*FR(tmp2+2) +
1310 FR(tmp+3)*FR(tmp2+3);
1315 if( !IS_FPU_DOUBLEPREC() ) {
1316 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1317 FR(FRn) = sinf(angle);
1318 FR((FRn)+1) = cosf(angle);
1323 if( !IS_FPU_DOUBLEPREC() ) {
1325 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
1326 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1327 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
1328 xf[9]*fv[2] + xf[13]*fv[3];
1329 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
1330 xf[8]*fv[2] + xf[12]*fv[3];
1331 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
1332 xf[11]*fv[2] + xf[15]*fv[3];
1333 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
1334 xf[10]*fv[2] + xf[14]*fv[3];
1341 sh4r.pc = sh4r.new_pc;
1343 sh4r.in_delay_slot = 0;
.