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lxdream.org :: lxdream/test/testaica.c
lxdream 0.9.1
released Jun 29
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filename test/testaica.c
changeset 812:8cc61d5ea1f8
next821:4398dafeb77d
author nkeynes
date Wed Aug 13 10:32:00 2008 +0000 (14 years ago)
permissions -rw-r--r--
last change Add ARM test harness (not quite working on DC but almost...)
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     1 /**
     2  * $Id: testdata.c 602 2008-01-15 20:50:23Z nkeynes $
     3  * 
     4  * AICA test loader
     5  *
     6  * Copyright (c) 2006 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    19 #include <stdio.h>
    21 #include "lib.h"
    23 #define AICA_RAM_BASE 0x00800000
    25 #define AICA_SYSCALL (AICA_RAM_BASE+0x30)
    26 #define AICA_SYSCALL_ARG1 (AICA_SYSCALL+4)
    27 #define AICA_SYSCALL_ARG2 (AICA_SYSCALL+8)
    28 #define AICA_SYSCALL_ARG3 (AICA_SYSCALL+12)
    29 #define AICA_SYSCALL_RETURN (AICA_SYSCALL+4)
    31 #define SYS_READ 0
    32 #define SYS_WRITE 1
    33 #define SYS_OPEN 2
    34 #define SYS_CLOSE 3
    35 #define SYS_CREAT 4
    36 #define SYS_LINK 5
    37 #define SYS_UNLINK 6
    38 #define SYS_CHDIR 7
    39 #define SYS_CHMOD 8
    40 #define SYS_LSEEK 9
    41 #define SYS_FSTAT 10
    42 #define SYS_TIME 11
    43 #define SYS_STAT 12
    44 #define SYS_UTIME 13
    45 #define SYS_ASSIGNWRKMEM 14
    46 #define SYS_EXIT 15
    47 #define SYS_OPENDIR 16
    48 #define SYS_CLOSEDIR 17
    49 #define SYS_READDIR 18
    50 #define SYS_GETHOSTINFO 19
    52 uint32_t do_syscall( uint32_t syscall, uint32_t arg1, uint32_t arg2, uint32_t arg3 )
    53 {
    54     uint32_t fd, len;
    55     char *data;
    57     switch( syscall ) {
    58     case SYS_READ:
    59         fd = arg1;
    60         data = (char *)(AICA_RAM_BASE + (arg2 & 0x001FFFFF));
    61         len = arg3;
    62         return read( fd, data, len );
    63     case SYS_WRITE:
    64         fd = arg1;
    65         data = (char *)(AICA_RAM_BASE + (arg2 & 0x001FFFFF));
    66         len = arg3;
    67         return write( fd, data, len );
    68         break;
    69     case SYS_EXIT:
    70         aica_disable();
    71         exit(arg1);
    72     default:
    73         return 0;
    74     }        
    75 }
    78 int main( int argc, char *argv[] ) 
    79 {
    80     char buf[65536] __attribute__((aligned(32)));
    81     uint32_t aica_addr = AICA_RAM_BASE;
    82     int len;
    84     aica_disable();
    85     /* Load ARM program from stdin and copy to ARM memory */
    86     while( (len = read(0, buf, sizeof(buf))) > 0 ) {
    87         aica_dma_write( aica_addr, buf, len );
    88         aica_addr += len;
    89     }
    91     /* Main loop waiting for IO commands */
    92     aica_enable();
    93     do {
    94         int syscall = long_read(AICA_SYSCALL);
    95         if( syscall != -1 ) {
    96             uint32_t result = do_syscall( syscall, long_read(AICA_SYSCALL_ARG1), 
    97                     long_read(AICA_SYSCALL_ARG2), long_read(AICA_SYSCALL_ARG3) );
    98             long_write( AICA_SYSCALL_RETURN, result );
    99             long_write( AICA_SYSCALL, -1 );
   100         }
   101     } while( 1 );
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