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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 374:8f80a795513e
prev369:4b4223e7d720
next378:f10fbdd4e24b
author nkeynes
date Tue Sep 11 02:14:46 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Cache the pointer to the last FR bank (speeds fp ops up by about 10%)
Implement experimental fix for FLOAT/FTRC
Make read/write sr functions non-static (share with translator)
Much more translator WIP
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     1 /**
     2  * $Id: sh4core.c,v 1.44 2007-09-11 02:14:46 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 #define EXV_EXCEPTION    0x100  /* General exception vector */
    38 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    39 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    41 /********************** SH4 Module Definition ****************************/
    43 void sh4_init( void );
    44 void sh4_reset( void );
    45 uint32_t sh4_run_slice( uint32_t );
    46 void sh4_start( void );
    47 void sh4_stop( void );
    48 void sh4_save_state( FILE *f );
    49 int sh4_load_state( FILE *f );
    50 void sh4_accept_interrupt( void );
    52 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    53 				       NULL, sh4_run_slice, sh4_stop,
    54 				       sh4_save_state, sh4_load_state };
    56 struct sh4_registers sh4r;
    58 void sh4_init(void)
    59 {
    60     register_io_regions( mmio_list_sh4mmio );
    61     MMU_init();
    62     sh4_reset();
    63 }
    65 void sh4_reset(void)
    66 {
    67     /* zero everything out, for the sake of having a consistent state. */
    68     memset( &sh4r, 0, sizeof(sh4r) );
    70     /* Resume running if we were halted */
    71     sh4r.sh4_state = SH4_STATE_RUNNING;
    73     sh4r.pc    = 0xA0000000;
    74     sh4r.new_pc= 0xA0000002;
    75     sh4r.vbr   = 0x00000000;
    76     sh4r.fpscr = 0x00040001;
    77     sh4r.sr    = 0x700000F0;
    78     sh4r.fr_bank = &sh4r.fr[0][0];
    80     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    81     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    83     /* Peripheral modules */
    84     CPG_reset();
    85     INTC_reset();
    86     MMU_reset();
    87     TMU_reset();
    88     SCIF_reset();
    89 }
    91 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    92 static int sh4_breakpoint_count = 0;
    93 static uint16_t *sh4_icache = NULL;
    94 static uint32_t sh4_icache_addr = 0;
    96 void sh4_set_breakpoint( uint32_t pc, int type )
    97 {
    98     sh4_breakpoints[sh4_breakpoint_count].address = pc;
    99     sh4_breakpoints[sh4_breakpoint_count].type = type;
   100     sh4_breakpoint_count++;
   101 }
   103 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   104 {
   105     int i;
   107     for( i=0; i<sh4_breakpoint_count; i++ ) {
   108 	if( sh4_breakpoints[i].address == pc && 
   109 	    sh4_breakpoints[i].type == type ) {
   110 	    while( ++i < sh4_breakpoint_count ) {
   111 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   112 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   113 	    }
   114 	    sh4_breakpoint_count--;
   115 	    return TRUE;
   116 	}
   117     }
   118     return FALSE;
   119 }
   121 int sh4_get_breakpoint( uint32_t pc )
   122 {
   123     int i;
   124     for( i=0; i<sh4_breakpoint_count; i++ ) {
   125 	if( sh4_breakpoints[i].address == pc )
   126 	    return sh4_breakpoints[i].type;
   127     }
   128     return 0;
   129 }
   131 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   132 {
   133     int i;
   134     sh4r.slice_cycle = 0;
   136     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   137 	if( sh4r.event_pending < nanosecs ) {
   138 	    sh4r.sh4_state = SH4_STATE_RUNNING;
   139 	    sh4r.slice_cycle = sh4r.event_pending;
   140 	}
   141     }
   143     if( sh4_breakpoint_count == 0 ) {
   144 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   145 	    if( SH4_EVENT_PENDING() ) {
   146 		if( sh4r.event_types & PENDING_EVENT ) {
   147 		    event_execute();
   148 		}
   149 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   150 		if( sh4r.event_types & PENDING_IRQ ) {
   151 		    sh4_accept_interrupt();
   152 		}
   153 	    }
   154 	    if( !sh4_execute_instruction() ) {
   155 		break;
   156 	    }
   157 	}
   158     } else {
   159 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   160 	    if( SH4_EVENT_PENDING() ) {
   161 		if( sh4r.event_types & PENDING_EVENT ) {
   162 		    event_execute();
   163 		}
   164 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   165 		if( sh4r.event_types & PENDING_IRQ ) {
   166 		    sh4_accept_interrupt();
   167 		}
   168 	    }
   170 	    if( !sh4_execute_instruction() )
   171 		break;
   172 #ifdef ENABLE_DEBUG_MODE
   173 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
   174 		if( sh4_breakpoints[i].address == sh4r.pc ) {
   175 		    break;
   176 		}
   177 	    }
   178 	    if( i != sh4_breakpoint_count ) {
   179 		dreamcast_stop();
   180 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   181 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   182 		break;
   183 	    }
   184 #endif	
   185 	}
   186     }
   188     /* If we aborted early, but the cpu is still technically running,
   189      * we're doing a hard abort - cut the timeslice back to what we
   190      * actually executed
   191      */
   192     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   193 	nanosecs = sh4r.slice_cycle;
   194     }
   195     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   196 	TMU_run_slice( nanosecs );
   197 	SCIF_run_slice( nanosecs );
   198     }
   199     return nanosecs;
   200 }
   202 void sh4_stop(void)
   203 {
   205 }
   207 void sh4_save_state( FILE *f )
   208 {
   209     fwrite( &sh4r, sizeof(sh4r), 1, f );
   210     MMU_save_state( f );
   211     INTC_save_state( f );
   212     TMU_save_state( f );
   213     SCIF_save_state( f );
   214 }
   216 int sh4_load_state( FILE * f )
   217 {
   218     fread( &sh4r, sizeof(sh4r), 1, f );
   219     MMU_load_state( f );
   220     INTC_load_state( f );
   221     TMU_load_state( f );
   222     return SCIF_load_state( f );
   223 }
   225 /********************** SH4 emulation core  ****************************/
   227 void sh4_set_pc( int pc )
   228 {
   229     sh4r.pc = pc;
   230     sh4r.new_pc = pc+2;
   231 }
   233 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   234 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   236 #if(SH4_CALLTRACE == 1)
   237 #define MAX_CALLSTACK 32
   238 static struct call_stack {
   239     sh4addr_t call_addr;
   240     sh4addr_t target_addr;
   241     sh4addr_t stack_pointer;
   242 } call_stack[MAX_CALLSTACK];
   244 static int call_stack_depth = 0;
   245 int sh4_call_trace_on = 0;
   247 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   248 {
   249     if( call_stack_depth < MAX_CALLSTACK ) {
   250 	call_stack[call_stack_depth].call_addr = source;
   251 	call_stack[call_stack_depth].target_addr = dest;
   252 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   253     }
   254     call_stack_depth++;
   255 }
   257 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   258 {
   259     if( call_stack_depth > 0 ) {
   260 	call_stack_depth--;
   261     }
   262 }
   264 void fprint_stack_trace( FILE *f )
   265 {
   266     int i = call_stack_depth -1;
   267     if( i >= MAX_CALLSTACK )
   268 	i = MAX_CALLSTACK - 1;
   269     for( ; i >= 0; i-- ) {
   270 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   271 		 (call_stack_depth - i), call_stack[i].call_addr,
   272 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   273     }
   274 }
   276 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   277 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   278 #else
   279 #define TRACE_CALL( dest, rts ) 
   280 #define TRACE_RETURN( source, dest )
   281 #endif
   283 #define RAISE( x, v ) do{			\
   284     if( sh4r.vbr == 0 ) { \
   285         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   286         dreamcast_stop(); return FALSE;	\
   287     } else { \
   288         sh4r.spc = sh4r.pc;	\
   289         sh4r.ssr = sh4_read_sr(); \
   290         sh4r.sgr = sh4r.r[15]; \
   291         MMIO_WRITE(MMU,EXPEVT,x); \
   292         sh4r.pc = sh4r.vbr + v; \
   293         sh4r.new_pc = sh4r.pc + 2; \
   294         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   295 	if( sh4r.in_delay_slot ) { \
   296 	    sh4r.in_delay_slot = 0; \
   297 	    sh4r.spc -= 2; \
   298 	} \
   299     } \
   300     return TRUE; } while(0)
   302 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   303 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   304 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   305 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   306 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   307 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   309 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   311 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   312 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   314 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   315 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   316 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   317 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   318 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   320 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   321 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   322 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   324 static void sh4_switch_banks( )
   325 {
   326     uint32_t tmp[8];
   328     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   329     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   330     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   331 }
   333 void sh4_write_sr( uint32_t newval )
   334 {
   335     if( (newval ^ sh4r.sr) & SR_RB )
   336         sh4_switch_banks();
   337     sh4r.sr = newval;
   338     sh4r.t = (newval&SR_T) ? 1 : 0;
   339     sh4r.s = (newval&SR_S) ? 1 : 0;
   340     sh4r.m = (newval&SR_M) ? 1 : 0;
   341     sh4r.q = (newval&SR_Q) ? 1 : 0;
   342     intc_mask_changed();
   343 }
   345 static void sh4_write_float( uint32_t addr, int reg )
   346 {
   347     if( IS_FPU_DOUBLESIZE() ) {
   348 	if( reg & 1 ) {
   349 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   350 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   351 	} else {
   352 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   353 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   354 	}
   355     } else {
   356 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   357     }
   358 }
   360 static void sh4_read_float( uint32_t addr, int reg )
   361 {
   362     if( IS_FPU_DOUBLESIZE() ) {
   363 	if( reg & 1 ) {
   364 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   365 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   366 	} else {
   367 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   368 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   369 	}
   370     } else {
   371 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   372     }
   373 }
   375 uint32_t sh4_read_sr( void )
   376 {
   377     /* synchronize sh4r.sr with the various bitflags */
   378     sh4r.sr &= SR_MQSTMASK;
   379     if( sh4r.t ) sh4r.sr |= SR_T;
   380     if( sh4r.s ) sh4r.sr |= SR_S;
   381     if( sh4r.m ) sh4r.sr |= SR_M;
   382     if( sh4r.q ) sh4r.sr |= SR_Q;
   383     return sh4r.sr;
   384 }
   386 /**
   387  * Raise a general CPU exception for the specified exception code.
   388  * (NOT for TRAPA or TLB exceptions)
   389  */
   390 gboolean sh4_raise_exception( int code )
   391 {
   392     RAISE( code, EXV_EXCEPTION );
   393 }
   395 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   396     if( sh4r.in_delay_slot ) {
   397 	return sh4_raise_exception(slot_code);
   398     } else {
   399 	return sh4_raise_exception(normal_code);
   400     }
   401 }
   403 gboolean sh4_raise_tlb_exception( int code )
   404 {
   405     RAISE( code, EXV_TLBMISS );
   406 }
   408 void sh4_accept_interrupt( void )
   409 {
   410     uint32_t code = intc_accept_interrupt();
   411     sh4r.ssr = sh4_read_sr();
   412     sh4r.spc = sh4r.pc;
   413     sh4r.sgr = sh4r.r[15];
   414     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   415     MMIO_WRITE( MMU, INTEVT, code );
   416     sh4r.pc = sh4r.vbr + 0x600;
   417     sh4r.new_pc = sh4r.pc + 2;
   418     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   419 }
   421 gboolean sh4_execute_instruction( void )
   422 {
   423     uint32_t pc;
   424     unsigned short ir;
   425     uint32_t tmp;
   426     float ftmp;
   427     double dtmp;
   429 #define R0 sh4r.r[0]
   430     pc = sh4r.pc;
   431     if( pc > 0xFFFFFF00 ) {
   432 	/* SYSCALL Magic */
   433 	syscall_invoke( pc );
   434 	sh4r.in_delay_slot = 0;
   435 	pc = sh4r.pc = sh4r.pr;
   436 	sh4r.new_pc = sh4r.pc + 2;
   437     }
   438     CHECKRALIGN16(pc);
   440     /* Read instruction */
   441     uint32_t pageaddr = pc >> 12;
   442     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   443 	ir = sh4_icache[(pc&0xFFF)>>1];
   444     } else {
   445 	sh4_icache = (uint16_t *)mem_get_page(pc);
   446 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   447 	    /* If someone's actually been so daft as to try to execute out of an IO
   448 	     * region, fallback on the full-blown memory read
   449 	     */
   450 	    sh4_icache = NULL;
   451 	    ir = MEM_READ_WORD(pc);
   452 	} else {
   453 	    sh4_icache_addr = pageaddr;
   454 	    ir = sh4_icache[(pc&0xFFF)>>1];
   455 	}
   456     }
   457         switch( (ir&0xF000) >> 12 ) {
   458             case 0x0:
   459                 switch( ir&0xF ) {
   460                     case 0x2:
   461                         switch( (ir&0x80) >> 7 ) {
   462                             case 0x0:
   463                                 switch( (ir&0x70) >> 4 ) {
   464                                     case 0x0:
   465                                         { /* STC SR, Rn */
   466                                         uint32_t Rn = ((ir>>8)&0xF); 
   467                                         CHECKPRIV();
   468                                         sh4r.r[Rn] = sh4_read_sr();
   469                                         }
   470                                         break;
   471                                     case 0x1:
   472                                         { /* STC GBR, Rn */
   473                                         uint32_t Rn = ((ir>>8)&0xF); 
   474                                         CHECKPRIV();
   475                                         sh4r.r[Rn] = sh4r.gbr;
   476                                         }
   477                                         break;
   478                                     case 0x2:
   479                                         { /* STC VBR, Rn */
   480                                         uint32_t Rn = ((ir>>8)&0xF); 
   481                                         CHECKPRIV();
   482                                         sh4r.r[Rn] = sh4r.vbr;
   483                                         }
   484                                         break;
   485                                     case 0x3:
   486                                         { /* STC SSR, Rn */
   487                                         uint32_t Rn = ((ir>>8)&0xF); 
   488                                         CHECKPRIV();
   489                                         sh4r.r[Rn] = sh4r.ssr;
   490                                         }
   491                                         break;
   492                                     case 0x4:
   493                                         { /* STC SPC, Rn */
   494                                         uint32_t Rn = ((ir>>8)&0xF); 
   495                                         CHECKPRIV();
   496                                         sh4r.r[Rn] = sh4r.spc;
   497                                         }
   498                                         break;
   499                                     default:
   500                                         UNDEF();
   501                                         break;
   502                                 }
   503                                 break;
   504                             case 0x1:
   505                                 { /* STC Rm_BANK, Rn */
   506                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   507                                 CHECKPRIV();
   508                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   509                                 }
   510                                 break;
   511                         }
   512                         break;
   513                     case 0x3:
   514                         switch( (ir&0xF0) >> 4 ) {
   515                             case 0x0:
   516                                 { /* BSRF Rn */
   517                                 uint32_t Rn = ((ir>>8)&0xF); 
   518                                 CHECKSLOTILLEGAL();
   519                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   520                                 sh4r.in_delay_slot = 1;
   521                                 sh4r.pr = sh4r.pc + 4;
   522                                 sh4r.pc = sh4r.new_pc;
   523                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   524                                 TRACE_CALL( pc, sh4r.new_pc );
   525                                 return TRUE;
   526                                 }
   527                                 break;
   528                             case 0x2:
   529                                 { /* BRAF Rn */
   530                                 uint32_t Rn = ((ir>>8)&0xF); 
   531                                 CHECKSLOTILLEGAL();
   532                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   533                                 sh4r.in_delay_slot = 1;
   534                                 sh4r.pc = sh4r.new_pc;
   535                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   536                                 return TRUE;
   537                                 }
   538                                 break;
   539                             case 0x8:
   540                                 { /* PREF @Rn */
   541                                 uint32_t Rn = ((ir>>8)&0xF); 
   542                                 tmp = sh4r.r[Rn];
   543                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {
   544                            	 sh4_flush_store_queue(tmp);
   545                                 }
   546                                 }
   547                                 break;
   548                             case 0x9:
   549                                 { /* OCBI @Rn */
   550                                 uint32_t Rn = ((ir>>8)&0xF); 
   551                                 }
   552                                 break;
   553                             case 0xA:
   554                                 { /* OCBP @Rn */
   555                                 uint32_t Rn = ((ir>>8)&0xF); 
   556                                 }
   557                                 break;
   558                             case 0xB:
   559                                 { /* OCBWB @Rn */
   560                                 uint32_t Rn = ((ir>>8)&0xF); 
   561                                 }
   562                                 break;
   563                             case 0xC:
   564                                 { /* MOVCA.L R0, @Rn */
   565                                 uint32_t Rn = ((ir>>8)&0xF); 
   566                                 tmp = sh4r.r[Rn];
   567                                 CHECKWALIGN32(tmp);
   568                                 MEM_WRITE_LONG( tmp, R0 );
   569                                 }
   570                                 break;
   571                             default:
   572                                 UNDEF();
   573                                 break;
   574                         }
   575                         break;
   576                     case 0x4:
   577                         { /* MOV.B Rm, @(R0, Rn) */
   578                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   579                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   580                         }
   581                         break;
   582                     case 0x5:
   583                         { /* MOV.W Rm, @(R0, Rn) */
   584                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   585                         CHECKWALIGN16( R0 + sh4r.r[Rn] );
   586                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   587                         }
   588                         break;
   589                     case 0x6:
   590                         { /* MOV.L Rm, @(R0, Rn) */
   591                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   592                         CHECKWALIGN32( R0 + sh4r.r[Rn] );
   593                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   594                         }
   595                         break;
   596                     case 0x7:
   597                         { /* MUL.L Rm, Rn */
   598                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   599                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   600                                                (sh4r.r[Rm] * sh4r.r[Rn]);
   601                         }
   602                         break;
   603                     case 0x8:
   604                         switch( (ir&0xFF0) >> 4 ) {
   605                             case 0x0:
   606                                 { /* CLRT */
   607                                 sh4r.t = 0;
   608                                 }
   609                                 break;
   610                             case 0x1:
   611                                 { /* SETT */
   612                                 sh4r.t = 1;
   613                                 }
   614                                 break;
   615                             case 0x2:
   616                                 { /* CLRMAC */
   617                                 sh4r.mac = 0;
   618                                 }
   619                                 break;
   620                             case 0x3:
   621                                 { /* LDTLB */
   622                                 /* TODO */
   623                                 }
   624                                 break;
   625                             case 0x4:
   626                                 { /* CLRS */
   627                                 sh4r.s = 0;
   628                                 }
   629                                 break;
   630                             case 0x5:
   631                                 { /* SETS */
   632                                 sh4r.s = 1;
   633                                 }
   634                                 break;
   635                             default:
   636                                 UNDEF();
   637                                 break;
   638                         }
   639                         break;
   640                     case 0x9:
   641                         switch( (ir&0xF0) >> 4 ) {
   642                             case 0x0:
   643                                 { /* NOP */
   644                                 /* NOP */
   645                                 }
   646                                 break;
   647                             case 0x1:
   648                                 { /* DIV0U */
   649                                 sh4r.m = sh4r.q = sh4r.t = 0;
   650                                 }
   651                                 break;
   652                             case 0x2:
   653                                 { /* MOVT Rn */
   654                                 uint32_t Rn = ((ir>>8)&0xF); 
   655                                 sh4r.r[Rn] = sh4r.t;
   656                                 }
   657                                 break;
   658                             default:
   659                                 UNDEF();
   660                                 break;
   661                         }
   662                         break;
   663                     case 0xA:
   664                         switch( (ir&0xF0) >> 4 ) {
   665                             case 0x0:
   666                                 { /* STS MACH, Rn */
   667                                 uint32_t Rn = ((ir>>8)&0xF); 
   668                                 sh4r.r[Rn] = (sh4r.mac>>32);
   669                                 }
   670                                 break;
   671                             case 0x1:
   672                                 { /* STS MACL, Rn */
   673                                 uint32_t Rn = ((ir>>8)&0xF); 
   674                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;
   675                                 }
   676                                 break;
   677                             case 0x2:
   678                                 { /* STS PR, Rn */
   679                                 uint32_t Rn = ((ir>>8)&0xF); 
   680                                 sh4r.r[Rn] = sh4r.pr;
   681                                 }
   682                                 break;
   683                             case 0x3:
   684                                 { /* STC SGR, Rn */
   685                                 uint32_t Rn = ((ir>>8)&0xF); 
   686                                 CHECKPRIV();
   687                                 sh4r.r[Rn] = sh4r.sgr;
   688                                 }
   689                                 break;
   690                             case 0x5:
   691                                 { /* STS FPUL, Rn */
   692                                 uint32_t Rn = ((ir>>8)&0xF); 
   693                                 sh4r.r[Rn] = sh4r.fpul;
   694                                 }
   695                                 break;
   696                             case 0x6:
   697                                 { /* STS FPSCR, Rn */
   698                                 uint32_t Rn = ((ir>>8)&0xF); 
   699                                 sh4r.r[Rn] = sh4r.fpscr;
   700                                 }
   701                                 break;
   702                             case 0xF:
   703                                 { /* STC DBR, Rn */
   704                                 uint32_t Rn = ((ir>>8)&0xF); 
   705                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
   706                                 }
   707                                 break;
   708                             default:
   709                                 UNDEF();
   710                                 break;
   711                         }
   712                         break;
   713                     case 0xB:
   714                         switch( (ir&0xFF0) >> 4 ) {
   715                             case 0x0:
   716                                 { /* RTS */
   717                                 CHECKSLOTILLEGAL();
   718                                 CHECKDEST( sh4r.pr );
   719                                 sh4r.in_delay_slot = 1;
   720                                 sh4r.pc = sh4r.new_pc;
   721                                 sh4r.new_pc = sh4r.pr;
   722                                 TRACE_RETURN( pc, sh4r.new_pc );
   723                                 return TRUE;
   724                                 }
   725                                 break;
   726                             case 0x1:
   727                                 { /* SLEEP */
   728                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   729                             	sh4r.sh4_state = SH4_STATE_STANDBY;
   730                                 } else {
   731                             	sh4r.sh4_state = SH4_STATE_SLEEP;
   732                                 }
   733                                 return FALSE; /* Halt CPU */
   734                                 }
   735                                 break;
   736                             case 0x2:
   737                                 { /* RTE */
   738                                 CHECKPRIV();
   739                                 CHECKDEST( sh4r.spc );
   740                                 CHECKSLOTILLEGAL();
   741                                 sh4r.in_delay_slot = 1;
   742                                 sh4r.pc = sh4r.new_pc;
   743                                 sh4r.new_pc = sh4r.spc;
   744                                 sh4_write_sr( sh4r.ssr );
   745                                 return TRUE;
   746                                 }
   747                                 break;
   748                             default:
   749                                 UNDEF();
   750                                 break;
   751                         }
   752                         break;
   753                     case 0xC:
   754                         { /* MOV.B @(R0, Rm), Rn */
   755                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   756                         sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );
   757                         }
   758                         break;
   759                     case 0xD:
   760                         { /* MOV.W @(R0, Rm), Rn */
   761                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   762                         CHECKRALIGN16( R0 + sh4r.r[Rm] );
   763                                            sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
   764                         }
   765                         break;
   766                     case 0xE:
   767                         { /* MOV.L @(R0, Rm), Rn */
   768                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   769                         CHECKRALIGN32( R0 + sh4r.r[Rm] );
   770                                            sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
   771                         }
   772                         break;
   773                     case 0xF:
   774                         { /* MAC.L @Rm+, @Rn+ */
   775                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   776                         CHECKRALIGN32( sh4r.r[Rm] );
   777                         CHECKRALIGN32( sh4r.r[Rn] );
   778                         int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
   779                         sh4r.r[Rn] += 4;
   780                         tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
   781                         sh4r.r[Rm] += 4;
   782                         if( sh4r.s ) {
   783                             /* 48-bit Saturation. Yuch */
   784                             if( tmpl < (int64_t)0xFFFF800000000000LL )
   785                                 tmpl = 0xFFFF800000000000LL;
   786                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   787                                 tmpl = 0x00007FFFFFFFFFFFLL;
   788                         }
   789                         sh4r.mac = tmpl;
   790                         }
   791                         break;
   792                     default:
   793                         UNDEF();
   794                         break;
   795                 }
   796                 break;
   797             case 0x1:
   798                 { /* MOV.L Rm, @(disp, Rn) */
   799                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   800                 tmp = sh4r.r[Rn] + disp;
   801                 CHECKWALIGN32( tmp );
   802                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   803                 }
   804                 break;
   805             case 0x2:
   806                 switch( ir&0xF ) {
   807                     case 0x0:
   808                         { /* MOV.B Rm, @Rn */
   809                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   810                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   811                         }
   812                         break;
   813                     case 0x1:
   814                         { /* MOV.W Rm, @Rn */
   815                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   816                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   817                         }
   818                         break;
   819                     case 0x2:
   820                         { /* MOV.L Rm, @Rn */
   821                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   822                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   823                         }
   824                         break;
   825                     case 0x4:
   826                         { /* MOV.B Rm, @-Rn */
   827                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   828                         sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   829                         }
   830                         break;
   831                     case 0x5:
   832                         { /* MOV.W Rm, @-Rn */
   833                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   834                         sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   835                         }
   836                         break;
   837                     case 0x6:
   838                         { /* MOV.L Rm, @-Rn */
   839                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   840                         sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   841                         }
   842                         break;
   843                     case 0x7:
   844                         { /* DIV0S Rm, Rn */
   845                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   846                         sh4r.q = sh4r.r[Rn]>>31;
   847                         sh4r.m = sh4r.r[Rm]>>31;
   848                         sh4r.t = sh4r.q ^ sh4r.m;
   849                         }
   850                         break;
   851                     case 0x8:
   852                         { /* TST Rm, Rn */
   853                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   854                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
   855                         }
   856                         break;
   857                     case 0x9:
   858                         { /* AND Rm, Rn */
   859                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   860                         sh4r.r[Rn] &= sh4r.r[Rm];
   861                         }
   862                         break;
   863                     case 0xA:
   864                         { /* XOR Rm, Rn */
   865                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   866                         sh4r.r[Rn] ^= sh4r.r[Rm];
   867                         }
   868                         break;
   869                     case 0xB:
   870                         { /* OR Rm, Rn */
   871                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   872                         sh4r.r[Rn] |= sh4r.r[Rm];
   873                         }
   874                         break;
   875                     case 0xC:
   876                         { /* CMP/STR Rm, Rn */
   877                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   878                         /* set T = 1 if any byte in RM & RN is the same */
   879                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   880                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   881                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   882                         }
   883                         break;
   884                     case 0xD:
   885                         { /* XTRCT Rm, Rn */
   886                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   887                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
   888                         }
   889                         break;
   890                     case 0xE:
   891                         { /* MULU.W Rm, Rn */
   892                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   893                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   894                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   895                         }
   896                         break;
   897                     case 0xF:
   898                         { /* MULS.W Rm, Rn */
   899                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   900                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   901                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   902                         }
   903                         break;
   904                     default:
   905                         UNDEF();
   906                         break;
   907                 }
   908                 break;
   909             case 0x3:
   910                 switch( ir&0xF ) {
   911                     case 0x0:
   912                         { /* CMP/EQ Rm, Rn */
   913                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   914                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
   915                         }
   916                         break;
   917                     case 0x2:
   918                         { /* CMP/HS Rm, Rn */
   919                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   920                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
   921                         }
   922                         break;
   923                     case 0x3:
   924                         { /* CMP/GE Rm, Rn */
   925                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   926                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   927                         }
   928                         break;
   929                     case 0x4:
   930                         { /* DIV1 Rm, Rn */
   931                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   932                         /* This is just from the sh4p manual with some
   933                          * simplifications (someone want to check it's correct? :)
   934                          * Why they couldn't just provide a real DIV instruction...
   935                          */
   936                         uint32_t tmp0, tmp1, tmp2, dir;
   938                         dir = sh4r.q ^ sh4r.m;
   939                         sh4r.q = (sh4r.r[Rn] >> 31);
   940                         tmp2 = sh4r.r[Rm];
   941                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   942                         tmp0 = sh4r.r[Rn];
   943                         if( dir ) {
   944                              sh4r.r[Rn] += tmp2;
   945                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   946                         } else {
   947                              sh4r.r[Rn] -= tmp2;
   948                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   949                         }
   950                         sh4r.q ^= sh4r.m ^ tmp1;
   951                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   952                         }
   953                         break;
   954                     case 0x5:
   955                         { /* DMULU.L Rm, Rn */
   956                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   957                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
   958                         }
   959                         break;
   960                     case 0x6:
   961                         { /* CMP/HI Rm, Rn */
   962                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   963                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
   964                         }
   965                         break;
   966                     case 0x7:
   967                         { /* CMP/GT Rm, Rn */
   968                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   969                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   970                         }
   971                         break;
   972                     case 0x8:
   973                         { /* SUB Rm, Rn */
   974                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   975                         sh4r.r[Rn] -= sh4r.r[Rm];
   976                         }
   977                         break;
   978                     case 0xA:
   979                         { /* SUBC Rm, Rn */
   980                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   981                         tmp = sh4r.r[Rn];
   982                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   983                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   984                         }
   985                         break;
   986                     case 0xB:
   987                         UNIMP(ir); /* SUBV Rm, Rn */
   988                         break;
   989                     case 0xC:
   990                         { /* ADD Rm, Rn */
   991                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   992                         sh4r.r[Rn] += sh4r.r[Rm];
   993                         }
   994                         break;
   995                     case 0xD:
   996                         { /* DMULS.L Rm, Rn */
   997                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   998                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
   999                         }
  1000                         break;
  1001                     case 0xE:
  1002                         { /* ADDC Rm, Rn */
  1003                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1004                         tmp = sh4r.r[Rn];
  1005                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
  1006                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
  1008                         break;
  1009                     case 0xF:
  1010                         { /* ADDV Rm, Rn */
  1011                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1012                         tmp = sh4r.r[Rn] + sh4r.r[Rm];
  1013                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
  1014                         sh4r.r[Rn] = tmp;
  1016                         break;
  1017                     default:
  1018                         UNDEF();
  1019                         break;
  1021                 break;
  1022             case 0x4:
  1023                 switch( ir&0xF ) {
  1024                     case 0x0:
  1025                         switch( (ir&0xF0) >> 4 ) {
  1026                             case 0x0:
  1027                                 { /* SHLL Rn */
  1028                                 uint32_t Rn = ((ir>>8)&0xF); 
  1029                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
  1031                                 break;
  1032                             case 0x1:
  1033                                 { /* DT Rn */
  1034                                 uint32_t Rn = ((ir>>8)&0xF); 
  1035                                 sh4r.r[Rn] --;
  1036                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
  1038                                 break;
  1039                             case 0x2:
  1040                                 { /* SHAL Rn */
  1041                                 uint32_t Rn = ((ir>>8)&0xF); 
  1042                                 sh4r.t = sh4r.r[Rn] >> 31;
  1043                                 sh4r.r[Rn] <<= 1;
  1045                                 break;
  1046                             default:
  1047                                 UNDEF();
  1048                                 break;
  1050                         break;
  1051                     case 0x1:
  1052                         switch( (ir&0xF0) >> 4 ) {
  1053                             case 0x0:
  1054                                 { /* SHLR Rn */
  1055                                 uint32_t Rn = ((ir>>8)&0xF); 
  1056                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
  1058                                 break;
  1059                             case 0x1:
  1060                                 { /* CMP/PZ Rn */
  1061                                 uint32_t Rn = ((ir>>8)&0xF); 
  1062                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
  1064                                 break;
  1065                             case 0x2:
  1066                                 { /* SHAR Rn */
  1067                                 uint32_t Rn = ((ir>>8)&0xF); 
  1068                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1069                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
  1071                                 break;
  1072                             default:
  1073                                 UNDEF();
  1074                                 break;
  1076                         break;
  1077                     case 0x2:
  1078                         switch( (ir&0xF0) >> 4 ) {
  1079                             case 0x0:
  1080                                 { /* STS.L MACH, @-Rn */
  1081                                 uint32_t Rn = ((ir>>8)&0xF); 
  1082                                 sh4r.r[Rn] -= 4;
  1083                                 CHECKWALIGN32( sh4r.r[Rn] );
  1084                                 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
  1086                                 break;
  1087                             case 0x1:
  1088                                 { /* STS.L MACL, @-Rn */
  1089                                 uint32_t Rn = ((ir>>8)&0xF); 
  1090                                 sh4r.r[Rn] -= 4;
  1091                                 CHECKWALIGN32( sh4r.r[Rn] );
  1092                                 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
  1094                                 break;
  1095                             case 0x2:
  1096                                 { /* STS.L PR, @-Rn */
  1097                                 uint32_t Rn = ((ir>>8)&0xF); 
  1098                                 sh4r.r[Rn] -= 4;
  1099                                 CHECKWALIGN32( sh4r.r[Rn] );
  1100                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
  1102                                 break;
  1103                             case 0x3:
  1104                                 { /* STC.L SGR, @-Rn */
  1105                                 uint32_t Rn = ((ir>>8)&0xF); 
  1106                                 CHECKPRIV();
  1107                                 sh4r.r[Rn] -= 4;
  1108                                 CHECKWALIGN32( sh4r.r[Rn] );
  1109                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
  1111                                 break;
  1112                             case 0x5:
  1113                                 { /* STS.L FPUL, @-Rn */
  1114                                 uint32_t Rn = ((ir>>8)&0xF); 
  1115                                 sh4r.r[Rn] -= 4;
  1116                                 CHECKWALIGN32( sh4r.r[Rn] );
  1117                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
  1119                                 break;
  1120                             case 0x6:
  1121                                 { /* STS.L FPSCR, @-Rn */
  1122                                 uint32_t Rn = ((ir>>8)&0xF); 
  1123                                 sh4r.r[Rn] -= 4;
  1124                                 CHECKWALIGN32( sh4r.r[Rn] );
  1125                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
  1127                                 break;
  1128                             case 0xF:
  1129                                 { /* STC.L DBR, @-Rn */
  1130                                 uint32_t Rn = ((ir>>8)&0xF); 
  1131                                 CHECKPRIV();
  1132                                 sh4r.r[Rn] -= 4;
  1133                                 CHECKWALIGN32( sh4r.r[Rn] );
  1134                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
  1136                                 break;
  1137                             default:
  1138                                 UNDEF();
  1139                                 break;
  1141                         break;
  1142                     case 0x3:
  1143                         switch( (ir&0x80) >> 7 ) {
  1144                             case 0x0:
  1145                                 switch( (ir&0x70) >> 4 ) {
  1146                                     case 0x0:
  1147                                         { /* STC.L SR, @-Rn */
  1148                                         uint32_t Rn = ((ir>>8)&0xF); 
  1149                                         CHECKPRIV();
  1150                                         sh4r.r[Rn] -= 4;
  1151                                         CHECKWALIGN32( sh4r.r[Rn] );
  1152                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
  1154                                         break;
  1155                                     case 0x1:
  1156                                         { /* STC.L GBR, @-Rn */
  1157                                         uint32_t Rn = ((ir>>8)&0xF); 
  1158                                         sh4r.r[Rn] -= 4;
  1159                                         CHECKWALIGN32( sh4r.r[Rn] );
  1160                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
  1162                                         break;
  1163                                     case 0x2:
  1164                                         { /* STC.L VBR, @-Rn */
  1165                                         uint32_t Rn = ((ir>>8)&0xF); 
  1166                                         CHECKPRIV();
  1167                                         sh4r.r[Rn] -= 4;
  1168                                         CHECKWALIGN32( sh4r.r[Rn] );
  1169                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
  1171                                         break;
  1172                                     case 0x3:
  1173                                         { /* STC.L SSR, @-Rn */
  1174                                         uint32_t Rn = ((ir>>8)&0xF); 
  1175                                         CHECKPRIV();
  1176                                         sh4r.r[Rn] -= 4;
  1177                                         CHECKWALIGN32( sh4r.r[Rn] );
  1178                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
  1180                                         break;
  1181                                     case 0x4:
  1182                                         { /* STC.L SPC, @-Rn */
  1183                                         uint32_t Rn = ((ir>>8)&0xF); 
  1184                                         CHECKPRIV();
  1185                                         sh4r.r[Rn] -= 4;
  1186                                         CHECKWALIGN32( sh4r.r[Rn] );
  1187                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
  1189                                         break;
  1190                                     default:
  1191                                         UNDEF();
  1192                                         break;
  1194                                 break;
  1195                             case 0x1:
  1196                                 { /* STC.L Rm_BANK, @-Rn */
  1197                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1198                                 CHECKPRIV();
  1199                                 sh4r.r[Rn] -= 4;
  1200                                 CHECKWALIGN32( sh4r.r[Rn] );
  1201                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
  1203                                 break;
  1205                         break;
  1206                     case 0x4:
  1207                         switch( (ir&0xF0) >> 4 ) {
  1208                             case 0x0:
  1209                                 { /* ROTL Rn */
  1210                                 uint32_t Rn = ((ir>>8)&0xF); 
  1211                                 sh4r.t = sh4r.r[Rn] >> 31;
  1212                                 sh4r.r[Rn] <<= 1;
  1213                                 sh4r.r[Rn] |= sh4r.t;
  1215                                 break;
  1216                             case 0x2:
  1217                                 { /* ROTCL Rn */
  1218                                 uint32_t Rn = ((ir>>8)&0xF); 
  1219                                 tmp = sh4r.r[Rn] >> 31;
  1220                                 sh4r.r[Rn] <<= 1;
  1221                                 sh4r.r[Rn] |= sh4r.t;
  1222                                 sh4r.t = tmp;
  1224                                 break;
  1225                             default:
  1226                                 UNDEF();
  1227                                 break;
  1229                         break;
  1230                     case 0x5:
  1231                         switch( (ir&0xF0) >> 4 ) {
  1232                             case 0x0:
  1233                                 { /* ROTR Rn */
  1234                                 uint32_t Rn = ((ir>>8)&0xF); 
  1235                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1236                                 sh4r.r[Rn] >>= 1;
  1237                                 sh4r.r[Rn] |= (sh4r.t << 31);
  1239                                 break;
  1240                             case 0x1:
  1241                                 { /* CMP/PL Rn */
  1242                                 uint32_t Rn = ((ir>>8)&0xF); 
  1243                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
  1245                                 break;
  1246                             case 0x2:
  1247                                 { /* ROTCR Rn */
  1248                                 uint32_t Rn = ((ir>>8)&0xF); 
  1249                                 tmp = sh4r.r[Rn] & 0x00000001;
  1250                                 sh4r.r[Rn] >>= 1;
  1251                                 sh4r.r[Rn] |= (sh4r.t << 31 );
  1252                                 sh4r.t = tmp;
  1254                                 break;
  1255                             default:
  1256                                 UNDEF();
  1257                                 break;
  1259                         break;
  1260                     case 0x6:
  1261                         switch( (ir&0xF0) >> 4 ) {
  1262                             case 0x0:
  1263                                 { /* LDS.L @Rm+, MACH */
  1264                                 uint32_t Rm = ((ir>>8)&0xF); 
  1265                                 CHECKRALIGN32( sh4r.r[Rm] );
  1266                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1267                                            (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
  1268                                 sh4r.r[Rm] += 4;
  1270                                 break;
  1271                             case 0x1:
  1272                                 { /* LDS.L @Rm+, MACL */
  1273                                 uint32_t Rm = ((ir>>8)&0xF); 
  1274                                 CHECKRALIGN32( sh4r.r[Rm] );
  1275                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1276                                            (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
  1277                                 sh4r.r[Rm] += 4;
  1279                                 break;
  1280                             case 0x2:
  1281                                 { /* LDS.L @Rm+, PR */
  1282                                 uint32_t Rm = ((ir>>8)&0xF); 
  1283                                 CHECKRALIGN32( sh4r.r[Rm] );
  1284                                 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
  1285                                 sh4r.r[Rm] += 4;
  1287                                 break;
  1288                             case 0x3:
  1289                                 { /* LDC.L @Rm+, SGR */
  1290                                 uint32_t Rm = ((ir>>8)&0xF); 
  1291                                 CHECKPRIV();
  1292                                 CHECKRALIGN32( sh4r.r[Rm] );
  1293                                 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
  1294                                 sh4r.r[Rm] +=4;
  1296                                 break;
  1297                             case 0x5:
  1298                                 { /* LDS.L @Rm+, FPUL */
  1299                                 uint32_t Rm = ((ir>>8)&0xF); 
  1300                                 CHECKRALIGN32( sh4r.r[Rm] );
  1301                                 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
  1302                                 sh4r.r[Rm] +=4;
  1304                                 break;
  1305                             case 0x6:
  1306                                 { /* LDS.L @Rm+, FPSCR */
  1307                                 uint32_t Rm = ((ir>>8)&0xF); 
  1308                                 CHECKRALIGN32( sh4r.r[Rm] );
  1309                                 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
  1310                                 sh4r.r[Rm] +=4;
  1311                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1313                                 break;
  1314                             case 0xF:
  1315                                 { /* LDC.L @Rm+, DBR */
  1316                                 uint32_t Rm = ((ir>>8)&0xF); 
  1317                                 CHECKPRIV();
  1318                                 CHECKRALIGN32( sh4r.r[Rm] );
  1319                                 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
  1320                                 sh4r.r[Rm] +=4;
  1322                                 break;
  1323                             default:
  1324                                 UNDEF();
  1325                                 break;
  1327                         break;
  1328                     case 0x7:
  1329                         switch( (ir&0x80) >> 7 ) {
  1330                             case 0x0:
  1331                                 switch( (ir&0x70) >> 4 ) {
  1332                                     case 0x0:
  1333                                         { /* LDC.L @Rm+, SR */
  1334                                         uint32_t Rm = ((ir>>8)&0xF); 
  1335                                         CHECKSLOTILLEGAL();
  1336                                         CHECKPRIV();
  1337                                         CHECKWALIGN32( sh4r.r[Rm] );
  1338                                         sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );
  1339                                         sh4r.r[Rm] +=4;
  1341                                         break;
  1342                                     case 0x1:
  1343                                         { /* LDC.L @Rm+, GBR */
  1344                                         uint32_t Rm = ((ir>>8)&0xF); 
  1345                                         CHECKRALIGN32( sh4r.r[Rm] );
  1346                                         sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
  1347                                         sh4r.r[Rm] +=4;
  1349                                         break;
  1350                                     case 0x2:
  1351                                         { /* LDC.L @Rm+, VBR */
  1352                                         uint32_t Rm = ((ir>>8)&0xF); 
  1353                                         CHECKPRIV();
  1354                                         CHECKRALIGN32( sh4r.r[Rm] );
  1355                                         sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
  1356                                         sh4r.r[Rm] +=4;
  1358                                         break;
  1359                                     case 0x3:
  1360                                         { /* LDC.L @Rm+, SSR */
  1361                                         uint32_t Rm = ((ir>>8)&0xF); 
  1362                                         CHECKPRIV();
  1363                                         CHECKRALIGN32( sh4r.r[Rm] );
  1364                                         sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
  1365                                         sh4r.r[Rm] +=4;
  1367                                         break;
  1368                                     case 0x4:
  1369                                         { /* LDC.L @Rm+, SPC */
  1370                                         uint32_t Rm = ((ir>>8)&0xF); 
  1371                                         CHECKPRIV();
  1372                                         CHECKRALIGN32( sh4r.r[Rm] );
  1373                                         sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
  1374                                         sh4r.r[Rm] +=4;
  1376                                         break;
  1377                                     default:
  1378                                         UNDEF();
  1379                                         break;
  1381                                 break;
  1382                             case 0x1:
  1383                                 { /* LDC.L @Rm+, Rn_BANK */
  1384                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1385                                 CHECKPRIV();
  1386                                 CHECKRALIGN32( sh4r.r[Rm] );
  1387                                 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
  1388                                 sh4r.r[Rm] += 4;
  1390                                 break;
  1392                         break;
  1393                     case 0x8:
  1394                         switch( (ir&0xF0) >> 4 ) {
  1395                             case 0x0:
  1396                                 { /* SHLL2 Rn */
  1397                                 uint32_t Rn = ((ir>>8)&0xF); 
  1398                                 sh4r.r[Rn] <<= 2;
  1400                                 break;
  1401                             case 0x1:
  1402                                 { /* SHLL8 Rn */
  1403                                 uint32_t Rn = ((ir>>8)&0xF); 
  1404                                 sh4r.r[Rn] <<= 8;
  1406                                 break;
  1407                             case 0x2:
  1408                                 { /* SHLL16 Rn */
  1409                                 uint32_t Rn = ((ir>>8)&0xF); 
  1410                                 sh4r.r[Rn] <<= 16;
  1412                                 break;
  1413                             default:
  1414                                 UNDEF();
  1415                                 break;
  1417                         break;
  1418                     case 0x9:
  1419                         switch( (ir&0xF0) >> 4 ) {
  1420                             case 0x0:
  1421                                 { /* SHLR2 Rn */
  1422                                 uint32_t Rn = ((ir>>8)&0xF); 
  1423                                 sh4r.r[Rn] >>= 2;
  1425                                 break;
  1426                             case 0x1:
  1427                                 { /* SHLR8 Rn */
  1428                                 uint32_t Rn = ((ir>>8)&0xF); 
  1429                                 sh4r.r[Rn] >>= 8;
  1431                                 break;
  1432                             case 0x2:
  1433                                 { /* SHLR16 Rn */
  1434                                 uint32_t Rn = ((ir>>8)&0xF); 
  1435                                 sh4r.r[Rn] >>= 16;
  1437                                 break;
  1438                             default:
  1439                                 UNDEF();
  1440                                 break;
  1442                         break;
  1443                     case 0xA:
  1444                         switch( (ir&0xF0) >> 4 ) {
  1445                             case 0x0:
  1446                                 { /* LDS Rm, MACH */
  1447                                 uint32_t Rm = ((ir>>8)&0xF); 
  1448                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1449                                            (((uint64_t)sh4r.r[Rm])<<32);
  1451                                 break;
  1452                             case 0x1:
  1453                                 { /* LDS Rm, MACL */
  1454                                 uint32_t Rm = ((ir>>8)&0xF); 
  1455                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1456                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));
  1458                                 break;
  1459                             case 0x2:
  1460                                 { /* LDS Rm, PR */
  1461                                 uint32_t Rm = ((ir>>8)&0xF); 
  1462                                 sh4r.pr = sh4r.r[Rm];
  1464                                 break;
  1465                             case 0x3:
  1466                                 { /* LDC Rm, SGR */
  1467                                 uint32_t Rm = ((ir>>8)&0xF); 
  1468                                 CHECKPRIV();
  1469                                 sh4r.sgr = sh4r.r[Rm];
  1471                                 break;
  1472                             case 0x5:
  1473                                 { /* LDS Rm, FPUL */
  1474                                 uint32_t Rm = ((ir>>8)&0xF); 
  1475                                 sh4r.fpul = sh4r.r[Rm];
  1477                                 break;
  1478                             case 0x6:
  1479                                 { /* LDS Rm, FPSCR */
  1480                                 uint32_t Rm = ((ir>>8)&0xF); 
  1481                                 sh4r.fpscr = sh4r.r[Rm]; 
  1482                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1484                                 break;
  1485                             case 0xF:
  1486                                 { /* LDC Rm, DBR */
  1487                                 uint32_t Rm = ((ir>>8)&0xF); 
  1488                                 CHECKPRIV();
  1489                                 sh4r.dbr = sh4r.r[Rm];
  1491                                 break;
  1492                             default:
  1493                                 UNDEF();
  1494                                 break;
  1496                         break;
  1497                     case 0xB:
  1498                         switch( (ir&0xF0) >> 4 ) {
  1499                             case 0x0:
  1500                                 { /* JSR @Rn */
  1501                                 uint32_t Rn = ((ir>>8)&0xF); 
  1502                                 CHECKDEST( sh4r.r[Rn] );
  1503                                 CHECKSLOTILLEGAL();
  1504                                 sh4r.in_delay_slot = 1;
  1505                                 sh4r.pc = sh4r.new_pc;
  1506                                 sh4r.new_pc = sh4r.r[Rn];
  1507                                 sh4r.pr = pc + 4;
  1508                                 TRACE_CALL( pc, sh4r.new_pc );
  1509                                 return TRUE;
  1511                                 break;
  1512                             case 0x1:
  1513                                 { /* TAS.B @Rn */
  1514                                 uint32_t Rn = ((ir>>8)&0xF); 
  1515                                 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
  1516                                 sh4r.t = ( tmp == 0 ? 1 : 0 );
  1517                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
  1519                                 break;
  1520                             case 0x2:
  1521                                 { /* JMP @Rn */
  1522                                 uint32_t Rn = ((ir>>8)&0xF); 
  1523                                 CHECKDEST( sh4r.r[Rn] );
  1524                                 CHECKSLOTILLEGAL();
  1525                                 sh4r.in_delay_slot = 1;
  1526                                 sh4r.pc = sh4r.new_pc;
  1527                                 sh4r.new_pc = sh4r.r[Rn];
  1528                                 return TRUE;
  1530                                 break;
  1531                             default:
  1532                                 UNDEF();
  1533                                 break;
  1535                         break;
  1536                     case 0xC:
  1537                         { /* SHAD Rm, Rn */
  1538                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1539                         tmp = sh4r.r[Rm];
  1540                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1541                         else if( (tmp & 0x1F) == 0 )  
  1542                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
  1543                         else 
  1544                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
  1546                         break;
  1547                     case 0xD:
  1548                         { /* SHLD Rm, Rn */
  1549                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1550                         tmp = sh4r.r[Rm];
  1551                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1552                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
  1553                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
  1555                         break;
  1556                     case 0xE:
  1557                         switch( (ir&0x80) >> 7 ) {
  1558                             case 0x0:
  1559                                 switch( (ir&0x70) >> 4 ) {
  1560                                     case 0x0:
  1561                                         { /* LDC Rm, SR */
  1562                                         uint32_t Rm = ((ir>>8)&0xF); 
  1563                                         CHECKSLOTILLEGAL();
  1564                                         CHECKPRIV();
  1565                                         sh4_write_sr( sh4r.r[Rm] );
  1567                                         break;
  1568                                     case 0x1:
  1569                                         { /* LDC Rm, GBR */
  1570                                         uint32_t Rm = ((ir>>8)&0xF); 
  1571                                         sh4r.gbr = sh4r.r[Rm];
  1573                                         break;
  1574                                     case 0x2:
  1575                                         { /* LDC Rm, VBR */
  1576                                         uint32_t Rm = ((ir>>8)&0xF); 
  1577                                         CHECKPRIV();
  1578                                         sh4r.vbr = sh4r.r[Rm];
  1580                                         break;
  1581                                     case 0x3:
  1582                                         { /* LDC Rm, SSR */
  1583                                         uint32_t Rm = ((ir>>8)&0xF); 
  1584                                         CHECKPRIV();
  1585                                         sh4r.ssr = sh4r.r[Rm];
  1587                                         break;
  1588                                     case 0x4:
  1589                                         { /* LDC Rm, SPC */
  1590                                         uint32_t Rm = ((ir>>8)&0xF); 
  1591                                         CHECKPRIV();
  1592                                         sh4r.spc = sh4r.r[Rm];
  1594                                         break;
  1595                                     default:
  1596                                         UNDEF();
  1597                                         break;
  1599                                 break;
  1600                             case 0x1:
  1601                                 { /* LDC Rm, Rn_BANK */
  1602                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1603                                 CHECKPRIV();
  1604                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1606                                 break;
  1608                         break;
  1609                     case 0xF:
  1610                         { /* MAC.W @Rm+, @Rn+ */
  1611                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1612                         CHECKRALIGN16( sh4r.r[Rn] );
  1613                         CHECKRALIGN16( sh4r.r[Rm] );
  1614                         int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
  1615                         sh4r.r[Rn] += 2;
  1616                         stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
  1617                         sh4r.r[Rm] += 2;
  1618                         if( sh4r.s ) {
  1619                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
  1620                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
  1621                     	    sh4r.mac = 0x000000017FFFFFFFLL;
  1622                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
  1623                     	    sh4r.mac = 0x0000000180000000LL;
  1624                     	} else {
  1625                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1626                     		((uint32_t)(sh4r.mac + stmp));
  1628                         } else {
  1629                     	sh4r.mac += SIGNEXT32(stmp);
  1632                         break;
  1634                 break;
  1635             case 0x5:
  1636                 { /* MOV.L @(disp, Rm), Rn */
  1637                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  1638                 tmp = sh4r.r[Rm] + disp;
  1639                 CHECKRALIGN32( tmp );
  1640                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  1642                 break;
  1643             case 0x6:
  1644                 switch( ir&0xF ) {
  1645                     case 0x0:
  1646                         { /* MOV.B @Rm, Rn */
  1647                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1648                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] );
  1650                         break;
  1651                     case 0x1:
  1652                         { /* MOV.W @Rm, Rn */
  1653                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1654                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] );
  1656                         break;
  1657                     case 0x2:
  1658                         { /* MOV.L @Rm, Rn */
  1659                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1660                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] );
  1662                         break;
  1663                     case 0x3:
  1664                         { /* MOV Rm, Rn */
  1665                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1666                         sh4r.r[Rn] = sh4r.r[Rm];
  1668                         break;
  1669                     case 0x4:
  1670                         { /* MOV.B @Rm+, Rn */
  1671                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1672                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++;
  1674                         break;
  1675                     case 0x5:
  1676                         { /* MOV.W @Rm+, Rn */
  1677                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1678                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2;
  1680                         break;
  1681                     case 0x6:
  1682                         { /* MOV.L @Rm+, Rn */
  1683                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1684                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4;
  1686                         break;
  1687                     case 0x7:
  1688                         { /* NOT Rm, Rn */
  1689                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1690                         sh4r.r[Rn] = ~sh4r.r[Rm];
  1692                         break;
  1693                     case 0x8:
  1694                         { /* SWAP.B Rm, Rn */
  1695                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1696                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
  1698                         break;
  1699                     case 0x9:
  1700                         { /* SWAP.W Rm, Rn */
  1701                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1702                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
  1704                         break;
  1705                     case 0xA:
  1706                         { /* NEGC Rm, Rn */
  1707                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1708                         tmp = 0 - sh4r.r[Rm];
  1709                         sh4r.r[Rn] = tmp - sh4r.t;
  1710                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
  1712                         break;
  1713                     case 0xB:
  1714                         { /* NEG Rm, Rn */
  1715                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1716                         sh4r.r[Rn] = 0 - sh4r.r[Rm];
  1718                         break;
  1719                     case 0xC:
  1720                         { /* EXTU.B Rm, Rn */
  1721                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1722                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
  1724                         break;
  1725                     case 0xD:
  1726                         { /* EXTU.W Rm, Rn */
  1727                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1728                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
  1730                         break;
  1731                     case 0xE:
  1732                         { /* EXTS.B Rm, Rn */
  1733                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1734                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
  1736                         break;
  1737                     case 0xF:
  1738                         { /* EXTS.W Rm, Rn */
  1739                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1740                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
  1742                         break;
  1744                 break;
  1745             case 0x7:
  1746                 { /* ADD #imm, Rn */
  1747                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1748                 sh4r.r[Rn] += imm;
  1750                 break;
  1751             case 0x8:
  1752                 switch( (ir&0xF00) >> 8 ) {
  1753                     case 0x0:
  1754                         { /* MOV.B R0, @(disp, Rn) */
  1755                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1756                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
  1758                         break;
  1759                     case 0x1:
  1760                         { /* MOV.W R0, @(disp, Rn) */
  1761                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1762                         tmp = sh4r.r[Rn] + disp;
  1763                         CHECKWALIGN16( tmp );
  1764                         MEM_WRITE_WORD( tmp, R0 );
  1766                         break;
  1767                     case 0x4:
  1768                         { /* MOV.B @(disp, Rm), R0 */
  1769                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1770                         R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp );
  1772                         break;
  1773                     case 0x5:
  1774                         { /* MOV.W @(disp, Rm), R0 */
  1775                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1776                         tmp = sh4r.r[Rm] + disp;
  1777                         CHECKRALIGN16( tmp );
  1778                         R0 = MEM_READ_WORD( tmp );
  1780                         break;
  1781                     case 0x8:
  1782                         { /* CMP/EQ #imm, R0 */
  1783                         int32_t imm = SIGNEXT8(ir&0xFF); 
  1784                         sh4r.t = ( R0 == imm ? 1 : 0 );
  1786                         break;
  1787                     case 0x9:
  1788                         { /* BT disp */
  1789                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1790                         CHECKSLOTILLEGAL();
  1791                         if( sh4r.t ) {
  1792                             CHECKDEST( sh4r.pc + disp + 4 )
  1793                             sh4r.pc += disp + 4;
  1794                             sh4r.new_pc = sh4r.pc + 2;
  1795                             return TRUE;
  1798                         break;
  1799                     case 0xB:
  1800                         { /* BF disp */
  1801                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1802                         CHECKSLOTILLEGAL();
  1803                         if( !sh4r.t ) {
  1804                             CHECKDEST( sh4r.pc + disp + 4 )
  1805                             sh4r.pc += disp + 4;
  1806                             sh4r.new_pc = sh4r.pc + 2;
  1807                             return TRUE;
  1810                         break;
  1811                     case 0xD:
  1812                         { /* BT/S disp */
  1813                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1814                         CHECKSLOTILLEGAL();
  1815                         if( sh4r.t ) {
  1816                             CHECKDEST( sh4r.pc + disp + 4 )
  1817                             sh4r.in_delay_slot = 1;
  1818                             sh4r.pc = sh4r.new_pc;
  1819                             sh4r.new_pc = pc + disp + 4;
  1820                             sh4r.in_delay_slot = 1;
  1821                             return TRUE;
  1824                         break;
  1825                     case 0xF:
  1826                         { /* BF/S disp */
  1827                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1828                         CHECKSLOTILLEGAL();
  1829                         if( !sh4r.t ) {
  1830                             CHECKDEST( sh4r.pc + disp + 4 )
  1831                             sh4r.in_delay_slot = 1;
  1832                             sh4r.pc = sh4r.new_pc;
  1833                             sh4r.new_pc = pc + disp + 4;
  1834                             return TRUE;
  1837                         break;
  1838                     default:
  1839                         UNDEF();
  1840                         break;
  1842                 break;
  1843             case 0x9:
  1844                 { /* MOV.W @(disp, PC), Rn */
  1845                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  1846                 CHECKSLOTILLEGAL();
  1847                 tmp = pc + 4 + disp;
  1848                 sh4r.r[Rn] = MEM_READ_WORD( tmp );
  1850                 break;
  1851             case 0xA:
  1852                 { /* BRA disp */
  1853                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1854                 CHECKSLOTILLEGAL();
  1855                 CHECKDEST( sh4r.pc + disp + 4 );
  1856                 sh4r.in_delay_slot = 1;
  1857                 sh4r.pc = sh4r.new_pc;
  1858                 sh4r.new_pc = pc + 4 + disp;
  1859                 return TRUE;
  1861                 break;
  1862             case 0xB:
  1863                 { /* BSR disp */
  1864                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1865                 CHECKDEST( sh4r.pc + disp + 4 );
  1866                 CHECKSLOTILLEGAL();
  1867                 sh4r.in_delay_slot = 1;
  1868                 sh4r.pr = pc + 4;
  1869                 sh4r.pc = sh4r.new_pc;
  1870                 sh4r.new_pc = pc + 4 + disp;
  1871                 TRACE_CALL( pc, sh4r.new_pc );
  1872                 return TRUE;
  1874                 break;
  1875             case 0xC:
  1876                 switch( (ir&0xF00) >> 8 ) {
  1877                     case 0x0:
  1878                         { /* MOV.B R0, @(disp, GBR) */
  1879                         uint32_t disp = (ir&0xFF); 
  1880                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
  1882                         break;
  1883                     case 0x1:
  1884                         { /* MOV.W R0, @(disp, GBR) */
  1885                         uint32_t disp = (ir&0xFF)<<1; 
  1886                         tmp = sh4r.gbr + disp;
  1887                         CHECKWALIGN16( tmp );
  1888                         MEM_WRITE_WORD( tmp, R0 );
  1890                         break;
  1891                     case 0x2:
  1892                         { /* MOV.L R0, @(disp, GBR) */
  1893                         uint32_t disp = (ir&0xFF)<<2; 
  1894                         tmp = sh4r.gbr + disp;
  1895                         CHECKWALIGN32( tmp );
  1896                         MEM_WRITE_LONG( tmp, R0 );
  1898                         break;
  1899                     case 0x3:
  1900                         { /* TRAPA #imm */
  1901                         uint32_t imm = (ir&0xFF); 
  1902                         CHECKSLOTILLEGAL();
  1903                         MMIO_WRITE( MMU, TRA, imm<<2 );
  1904                         sh4r.pc += 2;
  1905                         sh4_raise_exception( EXC_TRAP );
  1907                         break;
  1908                     case 0x4:
  1909                         { /* MOV.B @(disp, GBR), R0 */
  1910                         uint32_t disp = (ir&0xFF); 
  1911                         R0 = MEM_READ_BYTE( sh4r.gbr + disp );
  1913                         break;
  1914                     case 0x5:
  1915                         { /* MOV.W @(disp, GBR), R0 */
  1916                         uint32_t disp = (ir&0xFF)<<1; 
  1917                         tmp = sh4r.gbr + disp;
  1918                         CHECKRALIGN16( tmp );
  1919                         R0 = MEM_READ_WORD( tmp );
  1921                         break;
  1922                     case 0x6:
  1923                         { /* MOV.L @(disp, GBR), R0 */
  1924                         uint32_t disp = (ir&0xFF)<<2; 
  1925                         tmp = sh4r.gbr + disp;
  1926                         CHECKRALIGN32( tmp );
  1927                         R0 = MEM_READ_LONG( tmp );
  1929                         break;
  1930                     case 0x7:
  1931                         { /* MOVA @(disp, PC), R0 */
  1932                         uint32_t disp = (ir&0xFF)<<2; 
  1933                         CHECKSLOTILLEGAL();
  1934                         R0 = (pc&0xFFFFFFFC) + disp + 4;
  1936                         break;
  1937                     case 0x8:
  1938                         { /* TST #imm, R0 */
  1939                         uint32_t imm = (ir&0xFF); 
  1940                         sh4r.t = (R0 & imm ? 0 : 1);
  1942                         break;
  1943                     case 0x9:
  1944                         { /* AND #imm, R0 */
  1945                         uint32_t imm = (ir&0xFF); 
  1946                         R0 &= imm;
  1948                         break;
  1949                     case 0xA:
  1950                         { /* XOR #imm, R0 */
  1951                         uint32_t imm = (ir&0xFF); 
  1952                         R0 ^= imm;
  1954                         break;
  1955                     case 0xB:
  1956                         { /* OR #imm, R0 */
  1957                         uint32_t imm = (ir&0xFF); 
  1958                         R0 |= imm;
  1960                         break;
  1961                     case 0xC:
  1962                         { /* TST.B #imm, @(R0, GBR) */
  1963                         uint32_t imm = (ir&0xFF); 
  1964                         sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 );
  1966                         break;
  1967                     case 0xD:
  1968                         { /* AND.B #imm, @(R0, GBR) */
  1969                         uint32_t imm = (ir&0xFF); 
  1970                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1972                         break;
  1973                     case 0xE:
  1974                         { /* XOR.B #imm, @(R0, GBR) */
  1975                         uint32_t imm = (ir&0xFF); 
  1976                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1978                         break;
  1979                     case 0xF:
  1980                         { /* OR.B #imm, @(R0, GBR) */
  1981                         uint32_t imm = (ir&0xFF); 
  1982                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1984                         break;
  1986                 break;
  1987             case 0xD:
  1988                 { /* MOV.L @(disp, PC), Rn */
  1989                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  1990                 CHECKSLOTILLEGAL();
  1991                 tmp = (pc&0xFFFFFFFC) + disp + 4;
  1992                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  1994                 break;
  1995             case 0xE:
  1996                 { /* MOV #imm, Rn */
  1997                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1998                 sh4r.r[Rn] = imm;
  2000                 break;
  2001             case 0xF:
  2002                 switch( ir&0xF ) {
  2003                     case 0x0:
  2004                         { /* FADD FRm, FRn */
  2005                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2006                         CHECKFPUEN();
  2007                         if( IS_FPU_DOUBLEPREC() ) {
  2008                     	DR(FRn) += DR(FRm);
  2009                         } else {
  2010                     	FR(FRn) += FR(FRm);
  2013                         break;
  2014                     case 0x1:
  2015                         { /* FSUB FRm, FRn */
  2016                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2017                         CHECKFPUEN();
  2018                         if( IS_FPU_DOUBLEPREC() ) {
  2019                     	DR(FRn) -= DR(FRm);
  2020                         } else {
  2021                     	FR(FRn) -= FR(FRm);
  2024                         break;
  2025                     case 0x2:
  2026                         { /* FMUL FRm, FRn */
  2027                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2028                         CHECKFPUEN();
  2029                         if( IS_FPU_DOUBLEPREC() ) {
  2030                     	DR(FRn) *= DR(FRm);
  2031                         } else {
  2032                     	FR(FRn) *= FR(FRm);
  2035                         break;
  2036                     case 0x3:
  2037                         { /* FDIV FRm, FRn */
  2038                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2039                         CHECKFPUEN();
  2040                         if( IS_FPU_DOUBLEPREC() ) {
  2041                     	DR(FRn) /= DR(FRm);
  2042                         } else {
  2043                     	FR(FRn) /= FR(FRm);
  2046                         break;
  2047                     case 0x4:
  2048                         { /* FCMP/EQ FRm, FRn */
  2049                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2050                         CHECKFPUEN();
  2051                         if( IS_FPU_DOUBLEPREC() ) {
  2052                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  2053                         } else {
  2054                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  2057                         break;
  2058                     case 0x5:
  2059                         { /* FCMP/GT FRm, FRn */
  2060                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2061                         CHECKFPUEN();
  2062                         if( IS_FPU_DOUBLEPREC() ) {
  2063                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  2064                         } else {
  2065                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  2068                         break;
  2069                     case 0x6:
  2070                         { /* FMOV @(R0, Rm), FRn */
  2071                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2072                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
  2074                         break;
  2075                     case 0x7:
  2076                         { /* FMOV FRm, @(R0, Rn) */
  2077                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2078                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
  2080                         break;
  2081                     case 0x8:
  2082                         { /* FMOV @Rm, FRn */
  2083                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2084                         MEM_FP_READ( sh4r.r[Rm], FRn );
  2086                         break;
  2087                     case 0x9:
  2088                         { /* FMOV @Rm+, FRn */
  2089                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2090                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
  2092                         break;
  2093                     case 0xA:
  2094                         { /* FMOV FRm, @Rn */
  2095                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2096                         MEM_FP_WRITE( sh4r.r[Rn], FRm );
  2098                         break;
  2099                     case 0xB:
  2100                         { /* FMOV FRm, @-Rn */
  2101                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2102                         sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );
  2104                         break;
  2105                     case 0xC:
  2106                         { /* FMOV FRm, FRn */
  2107                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2108                         if( IS_FPU_DOUBLESIZE() )
  2109                     	DR(FRn) = DR(FRm);
  2110                         else
  2111                     	FR(FRn) = FR(FRm);
  2113                         break;
  2114                     case 0xD:
  2115                         switch( (ir&0xF0) >> 4 ) {
  2116                             case 0x0:
  2117                                 { /* FSTS FPUL, FRn */
  2118                                 uint32_t FRn = ((ir>>8)&0xF); 
  2119                                 CHECKFPUEN(); FR(FRn) = FPULf;
  2121                                 break;
  2122                             case 0x1:
  2123                                 { /* FLDS FRm, FPUL */
  2124                                 uint32_t FRm = ((ir>>8)&0xF); 
  2125                                 CHECKFPUEN(); FPULf = FR(FRm);
  2127                                 break;
  2128                             case 0x2:
  2129                                 { /* FLOAT FPUL, FRn */
  2130                                 uint32_t FRn = ((ir>>8)&0xF); 
  2131                                 CHECKFPUEN();
  2132                                 if( IS_FPU_DOUBLEPREC() ) {
  2133                             	if( FRn&1 ) { // No, really...
  2134                             	    dtmp = (double)FPULi;
  2135                             	    FR(FRn) = *(((float *)&dtmp)+1);
  2136                             	} else {
  2137                             	    DRF(FRn>>1) = (double)FPULi;
  2139                                 } else {
  2140                             	FR(FRn) = (float)FPULi;
  2143                                 break;
  2144                             case 0x3:
  2145                                 { /* FTRC FRm, FPUL */
  2146                                 uint32_t FRm = ((ir>>8)&0xF); 
  2147                                 CHECKFPUEN();
  2148                                 if( IS_FPU_DOUBLEPREC() ) {
  2149                             	if( FRm&1 ) {
  2150                             	    dtmp = 0;
  2151                             	    *(((float *)&dtmp)+1) = FR(FRm);
  2152                             	} else {
  2153                             	    dtmp = DRF(FRm>>1);
  2155                                     if( dtmp >= MAX_INTF )
  2156                                         FPULi = MAX_INT;
  2157                                     else if( dtmp <= MIN_INTF )
  2158                                         FPULi = MIN_INT;
  2159                                     else 
  2160                                         FPULi = (int32_t)dtmp;
  2161                                 } else {
  2162                             	ftmp = FR(FRm);
  2163                             	if( ftmp >= MAX_INTF )
  2164                             	    FPULi = MAX_INT;
  2165                             	else if( ftmp <= MIN_INTF )
  2166                             	    FPULi = MIN_INT;
  2167                             	else
  2168                             	    FPULi = (int32_t)ftmp;
  2171                                 break;
  2172                             case 0x4:
  2173                                 { /* FNEG FRn */
  2174                                 uint32_t FRn = ((ir>>8)&0xF); 
  2175                                 CHECKFPUEN();
  2176                                 if( IS_FPU_DOUBLEPREC() ) {
  2177                             	DR(FRn) = -DR(FRn);
  2178                                 } else {
  2179                                     FR(FRn) = -FR(FRn);
  2182                                 break;
  2183                             case 0x5:
  2184                                 { /* FABS FRn */
  2185                                 uint32_t FRn = ((ir>>8)&0xF); 
  2186                                 CHECKFPUEN();
  2187                                 if( IS_FPU_DOUBLEPREC() ) {
  2188                             	DR(FRn) = fabs(DR(FRn));
  2189                                 } else {
  2190                                     FR(FRn) = fabsf(FR(FRn));
  2193                                 break;
  2194                             case 0x6:
  2195                                 { /* FSQRT FRn */
  2196                                 uint32_t FRn = ((ir>>8)&0xF); 
  2197                                 CHECKFPUEN();
  2198                                 if( IS_FPU_DOUBLEPREC() ) {
  2199                             	DR(FRn) = sqrt(DR(FRn));
  2200                                 } else {
  2201                                     FR(FRn) = sqrtf(FR(FRn));
  2204                                 break;
  2205                             case 0x7:
  2206                                 { /* FSRRA FRn */
  2207                                 uint32_t FRn = ((ir>>8)&0xF); 
  2208                                 CHECKFPUEN();
  2209                                 if( !IS_FPU_DOUBLEPREC() ) {
  2210                             	FR(FRn) = 1.0/sqrtf(FR(FRn));
  2213                                 break;
  2214                             case 0x8:
  2215                                 { /* FLDI0 FRn */
  2216                                 uint32_t FRn = ((ir>>8)&0xF); 
  2217                                 CHECKFPUEN();
  2218                                 if( IS_FPU_DOUBLEPREC() ) {
  2219                             	DR(FRn) = 0.0;
  2220                                 } else {
  2221                                     FR(FRn) = 0.0;
  2224                                 break;
  2225                             case 0x9:
  2226                                 { /* FLDI1 FRn */
  2227                                 uint32_t FRn = ((ir>>8)&0xF); 
  2228                                 CHECKFPUEN();
  2229                                 if( IS_FPU_DOUBLEPREC() ) {
  2230                             	DR(FRn) = 1.0;
  2231                                 } else {
  2232                                     FR(FRn) = 1.0;
  2235                                 break;
  2236                             case 0xA:
  2237                                 { /* FCNVSD FPUL, FRn */
  2238                                 uint32_t FRn = ((ir>>8)&0xF); 
  2239                                 CHECKFPUEN();
  2240                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2241                             	DR(FRn) = (double)FPULf;
  2244                                 break;
  2245                             case 0xB:
  2246                                 { /* FCNVDS FRm, FPUL */
  2247                                 uint32_t FRm = ((ir>>8)&0xF); 
  2248                                 CHECKFPUEN();
  2249                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2250                             	FPULf = (float)DR(FRm);
  2253                                 break;
  2254                             case 0xE:
  2255                                 { /* FIPR FVm, FVn */
  2256                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  2257                                 CHECKFPUEN();
  2258                                 if( !IS_FPU_DOUBLEPREC() ) {
  2259                                     int tmp2 = FVn<<2;
  2260                                     tmp = FVm<<2;
  2261                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  2262                                         FR(tmp+1)*FR(tmp2+1) +
  2263                                         FR(tmp+2)*FR(tmp2+2) +
  2264                                         FR(tmp+3)*FR(tmp2+3);
  2267                                 break;
  2268                             case 0xF:
  2269                                 switch( (ir&0x100) >> 8 ) {
  2270                                     case 0x0:
  2271                                         { /* FSCA FPUL, FRn */
  2272                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  2273                                         CHECKFPUEN();
  2274                                         if( !IS_FPU_DOUBLEPREC() ) {
  2275                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  2276                                             FR(FRn) = sinf(angle);
  2277                                             FR((FRn)+1) = cosf(angle);
  2280                                         break;
  2281                                     case 0x1:
  2282                                         switch( (ir&0x200) >> 9 ) {
  2283                                             case 0x0:
  2284                                                 { /* FTRV XMTRX, FVn */
  2285                                                 uint32_t FVn = ((ir>>10)&0x3); 
  2286                                                 CHECKFPUEN();
  2287                                                 if( !IS_FPU_DOUBLEPREC() ) {
  2288                                                     tmp = FVn<<2;
  2289                                             	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
  2290                                                     float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  2291                                                     FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
  2292                                             	    xf[9]*fv[2] + xf[13]*fv[3];
  2293                                                     FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
  2294                                             	    xf[8]*fv[2] + xf[12]*fv[3];
  2295                                                     FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
  2296                                             	    xf[11]*fv[2] + xf[15]*fv[3];
  2297                                                     FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
  2298                                             	    xf[10]*fv[2] + xf[14]*fv[3];
  2301                                                 break;
  2302                                             case 0x1:
  2303                                                 switch( (ir&0xC00) >> 10 ) {
  2304                                                     case 0x0:
  2305                                                         { /* FSCHG */
  2306                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
  2308                                                         break;
  2309                                                     case 0x2:
  2310                                                         { /* FRCHG */
  2311                                                         CHECKFPUEN(); 
  2312                                                         sh4r.fpscr ^= FPSCR_FR; 
  2313                                                         sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  2315                                                         break;
  2316                                                     case 0x3:
  2317                                                         { /* UNDEF */
  2318                                                         UNDEF(ir);
  2320                                                         break;
  2321                                                     default:
  2322                                                         UNDEF();
  2323                                                         break;
  2325                                                 break;
  2327                                         break;
  2329                                 break;
  2330                             default:
  2331                                 UNDEF();
  2332                                 break;
  2334                         break;
  2335                     case 0xE:
  2336                         { /* FMAC FR0, FRm, FRn */
  2337                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2338                         CHECKFPUEN();
  2339                         if( IS_FPU_DOUBLEPREC() ) {
  2340                             DR(FRn) += DR(FRm)*DR(0);
  2341                         } else {
  2342                     	FR(FRn) += FR(FRm)*FR(0);
  2345                         break;
  2346                     default:
  2347                         UNDEF();
  2348                         break;
  2350                 break;
  2353     sh4r.pc = sh4r.new_pc;
  2354     sh4r.new_pc += 2;
  2355     sh4r.in_delay_slot = 0;
  2356     return TRUE;
.