lxdream 0.9.1| filename | src/pvr2/pvr2.c |
| changeset | 106:9048bac046c3 |
| prev | 103:9b9cfc5855e0 |
| next | 107:e576dd36073a |
| author | nkeynes |
| date | Tue Mar 14 12:45:53 2006 +0000 (18 years ago) |
| permissions | -rw-r--r-- |
| last change | Move driver selection out to main at long last. Add video NULL driver for headless operation Make dcload exit() actually exit |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: pvr2.c,v 1.18 2006-03-14 12:45:53 nkeynes Exp $
3 *
4 * PVR2 (Video) Core MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include "dream.h"
21 #include "video.h"
22 #include "mem.h"
23 #include "asic.h"
24 #include "pvr2/pvr2.h"
25 #include "sh4/sh4core.h"
26 #define MMIO_IMPL
27 #include "pvr2/pvr2mmio.h"
29 char *video_base;
31 void pvr2_init( void );
32 uint32_t pvr2_run_slice( uint32_t );
33 void pvr2_display_frame( void );
35 /**
36 * Current PVR2 ram address of the data (if any) currently held in the
37 * OpenGL buffers.
38 */
40 video_driver_t video_driver = NULL;
41 struct video_buffer video_buffer[2];
42 int video_buffer_idx = 0;
44 struct video_timing {
45 int fields_per_second;
46 int total_lines;
47 int display_lines;
48 int line_time_ns;
49 };
51 struct video_timing pal_timing = { 50, 625, 575, 32000 };
52 struct video_timing ntsc_timing= { 60, 525, 480, 31746 };
54 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL,
55 pvr2_run_slice, NULL,
56 NULL, NULL };
58 void pvr2_init( void )
59 {
60 register_io_region( &mmio_region_PVR2 );
61 register_io_region( &mmio_region_PVR2PAL );
62 register_io_region( &mmio_region_PVR2TA );
63 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
64 }
66 void video_set_driver( video_driver_t driver )
67 {
68 if( video_driver != NULL && video_driver->shutdown_driver != NULL )
69 video_driver->shutdown_driver();
71 video_driver = driver;
72 if( driver->init_driver != NULL )
73 driver->init_driver();
74 driver->set_display_format( 640, 480, COLFMT_RGB32 );
75 }
77 uint32_t pvr2_line_count = 0;
78 uint32_t pvr2_line_remainder = 0;
79 uint32_t pvr2_irq_vpos1 = 0;
80 uint32_t pvr2_irq_vpos2 = 0;
81 struct video_timing *pvr2_timing = &ntsc_timing;
82 uint32_t pvr2_time_counter = 0;
83 uint32_t pvr2_frame_counter = 0;
84 uint32_t pvr2_time_per_frame = 20000000;
86 uint32_t pvr2_run_slice( uint32_t nanosecs )
87 {
88 pvr2_line_remainder += nanosecs;
89 while( pvr2_line_remainder >= pvr2_timing->line_time_ns ) {
90 pvr2_line_remainder -= pvr2_timing->line_time_ns;
91 pvr2_line_count++;
92 if( pvr2_line_count == pvr2_irq_vpos1 ) {
93 asic_event( EVENT_SCANLINE1 );
94 }
95 if( pvr2_line_count == pvr2_irq_vpos2 ) {
96 asic_event( EVENT_SCANLINE2 );
97 }
98 if( pvr2_line_count == pvr2_timing->display_lines ) {
99 asic_event( EVENT_RETRACE );
100 } else if( pvr2_line_count == pvr2_timing->total_lines ) {
101 pvr2_display_frame();
102 pvr2_line_count = 0;
103 }
104 }
105 return nanosecs;
106 }
108 uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
109 int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
110 char *frame_start; /* current video start address (in real memory) */
112 /**
113 * Display the next frame, copying the current contents of video ram to
114 * the window. If the video configuration has changed, first recompute the
115 * new frame size/depth.
116 */
117 void pvr2_display_frame( void )
118 {
119 uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
121 int dispsize = MMIO_READ( PVR2, DISPSIZE );
122 int dispmode = MMIO_READ( PVR2, DISPMODE );
123 int vidcfg = MMIO_READ( PVR2, DISPCFG );
124 int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
125 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
126 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
127 gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
128 gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
129 if( bEnabled ) {
130 video_buffer_t buffer = &video_buffer[video_buffer_idx];
131 video_buffer_idx = !video_buffer_idx;
132 video_buffer_t last = &video_buffer[video_buffer_idx];
133 buffer->rowstride = (vid_ppl + vid_stride) << 2;
134 buffer->data = frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
135 buffer->vres = vid_lpf;
136 if( interlaced ) buffer->vres <<= 1;
137 switch( (dispmode & DISPMODE_COL) >> 2 ) {
138 case 0:
139 buffer->colour_format = COLFMT_ARGB1555;
140 buffer->hres = vid_ppl << 1;
141 break;
142 case 1:
143 buffer->colour_format = COLFMT_RGB565;
144 buffer->hres = vid_ppl << 1;
145 break;
146 case 2:
147 buffer->colour_format = COLFMT_RGB888;
148 buffer->hres = (vid_ppl << 2) / 3;
149 break;
150 case 3:
151 buffer->colour_format = COLFMT_ARGB8888;
152 buffer->hres = vid_ppl;
153 break;
154 }
156 if( video_driver != NULL ) {
157 if( buffer->hres != last->hres ||
158 buffer->vres != last->vres ||
159 buffer->colour_format != last->colour_format) {
160 video_driver->set_display_format( buffer->hres, buffer->vres,
161 buffer->colour_format );
162 }
163 if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
164 uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
165 video_driver->display_blank_frame( colour );
166 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
167 video_driver->display_frame( buffer );
168 }
169 }
170 } else {
171 video_buffer_idx = 0;
172 video_buffer[0].hres = video_buffer[0].vres = 0;
173 }
174 pvr2_frame_counter++;
175 asic_event( EVENT_SCANLINE1 );
176 asic_event( EVENT_SCANLINE2 );
177 asic_event( EVENT_RETRACE );
178 }
180 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
181 {
182 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
183 MMIO_WRITE( PVR2, reg, val );
184 /* I don't want to hear about these */
185 return;
186 }
188 INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val,
189 MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
191 switch(reg) {
192 case VPOS_IRQ:
193 pvr2_irq_vpos1 = (val >> 16) & 0x03FF;
194 pvr2_irq_vpos2 = val & 0x03FF;
195 break;
196 case TAINIT:
197 if( val & 0x80000000 )
198 pvr2_ta_init();
199 break;
200 case RENDSTART:
201 if( val == 0xFFFFFFFF )
202 pvr2_render_scene();
203 break;
204 }
205 MMIO_WRITE( PVR2, reg, val );
206 }
208 MMIO_REGION_READ_FN( PVR2, reg )
209 {
210 switch( reg ) {
211 case BEAMPOS:
212 return sh4r.icount&0x20 ? 0x2000 : 1;
213 default:
214 return MMIO_READ( PVR2, reg );
215 }
216 }
218 MMIO_REGION_DEFFNS( PVR2PAL )
220 void pvr2_set_base_address( uint32_t base )
221 {
222 mmio_region_PVR2_write( DISPADDR1, base );
223 }
228 int32_t mmio_region_PVR2TA_read( uint32_t reg )
229 {
230 return 0xFFFFFFFF;
231 }
233 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
234 {
235 pvr2_ta_write( &val, sizeof(uint32_t) );
236 }
239 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
240 {
241 int bank_flag = (destaddr & 0x04) >> 2;
242 uint32_t *banks[2];
243 uint32_t *dwsrc;
244 int i;
246 destaddr = destaddr & 0x7FFFFF;
247 if( destaddr + length > 0x800000 ) {
248 length = 0x800000 - destaddr;
249 }
251 for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
252 texcache_invalidate_page( i );
253 }
255 banks[0] = ((uint32_t *)(video_base + (destaddr>>3)));
256 banks[1] = banks[0] + 0x100000;
258 /* Handle non-aligned start of source */
259 if( destaddr & 0x03 ) {
260 char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
261 for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
262 *dest++ = *src++;
263 }
264 bank_flag = !bank_flag;
265 }
267 dwsrc = (uint32_t *)src;
268 while( length >= 4 ) {
269 *banks[bank_flag]++ = *dwsrc++;
270 bank_flag = !bank_flag;
271 length -= 4;
272 }
274 /* Handle non-aligned end of source */
275 if( length ) {
276 src = (char *)dwsrc;
277 char *dest = (char *)banks[bank_flag];
278 while( length-- > 0 ) {
279 *dest++ = *src++;
280 }
281 }
283 }
285 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
286 {
287 int bank_flag = (srcaddr & 0x04) >> 2;
288 uint32_t *banks[2];
289 uint32_t *dwdest;
290 int i;
292 srcaddr = srcaddr & 0x7FFFFF;
293 if( srcaddr + length > 0x800000 )
294 length = 0x800000 - srcaddr;
296 banks[0] = ((uint32_t *)(video_base + (srcaddr>>3)));
297 banks[1] = banks[0] + 0x100000;
299 /* Handle non-aligned start of source */
300 if( srcaddr & 0x03 ) {
301 char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
302 for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
303 *dest++ = *src++;
304 }
305 bank_flag = !bank_flag;
306 }
308 dwdest = (uint32_t *)dest;
309 while( length >= 4 ) {
310 *dwdest++ = *banks[bank_flag]++;
311 bank_flag = !bank_flag;
312 length -= 4;
313 }
315 /* Handle non-aligned end of source */
316 if( length ) {
317 dest = (char *)dwdest;
318 char *src = (char *)banks[bank_flag];
319 while( length-- > 0 ) {
320 *dest++ = *src++;
321 }
322 }
323 }
.