filename | src/sh4/sh4core.in |
changeset | 401:f79327f39818 |
prev | 391:16afb90b5d47 |
next | 430:467519b050f4 |
author | nkeynes |
date | Fri Sep 28 07:25:22 2007 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Remove MMU check (probably shouldn't be here anyway), and disable TRACE_IO checks by default |
view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4core.in,v 1.8 2007-09-20 08:37:19 nkeynes Exp $
3 *
4 * SH4 emulation core, and parent module for all the SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include "dream.h"
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
25 #include "sh4/intc.h"
26 #include "mem.h"
27 #include "clock.h"
28 #include "syscall.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 /********************** SH4 Module Definition ****************************/
39 uint16_t *sh4_icache = NULL;
40 uint32_t sh4_icache_addr = 0;
42 uint32_t sh4_run_slice( uint32_t nanosecs )
43 {
44 int i;
45 sh4r.slice_cycle = 0;
47 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
48 if( sh4r.event_pending < nanosecs ) {
49 sh4r.sh4_state = SH4_STATE_RUNNING;
50 sh4r.slice_cycle = sh4r.event_pending;
51 }
52 }
54 if( sh4_breakpoint_count == 0 ) {
55 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
56 if( SH4_EVENT_PENDING() ) {
57 if( sh4r.event_types & PENDING_EVENT ) {
58 event_execute();
59 }
60 /* Eventq execute may (quite likely) deliver an immediate IRQ */
61 if( sh4r.event_types & PENDING_IRQ ) {
62 sh4_accept_interrupt();
63 }
64 }
65 if( !sh4_execute_instruction() ) {
66 break;
67 }
68 }
69 } else {
70 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
71 if( SH4_EVENT_PENDING() ) {
72 if( sh4r.event_types & PENDING_EVENT ) {
73 event_execute();
74 }
75 /* Eventq execute may (quite likely) deliver an immediate IRQ */
76 if( sh4r.event_types & PENDING_IRQ ) {
77 sh4_accept_interrupt();
78 }
79 }
81 if( !sh4_execute_instruction() )
82 break;
83 #ifdef ENABLE_DEBUG_MODE
84 for( i=0; i<sh4_breakpoint_count; i++ ) {
85 if( sh4_breakpoints[i].address == sh4r.pc ) {
86 break;
87 }
88 }
89 if( i != sh4_breakpoint_count ) {
90 dreamcast_stop();
91 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
92 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
93 break;
94 }
95 #endif
96 }
97 }
99 /* If we aborted early, but the cpu is still technically running,
100 * we're doing a hard abort - cut the timeslice back to what we
101 * actually executed
102 */
103 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
104 nanosecs = sh4r.slice_cycle;
105 }
106 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
107 TMU_run_slice( nanosecs );
108 SCIF_run_slice( nanosecs );
109 }
110 return nanosecs;
111 }
113 /********************** SH4 emulation core ****************************/
115 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
116 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
118 #if(SH4_CALLTRACE == 1)
119 #define MAX_CALLSTACK 32
120 static struct call_stack {
121 sh4addr_t call_addr;
122 sh4addr_t target_addr;
123 sh4addr_t stack_pointer;
124 } call_stack[MAX_CALLSTACK];
126 static int call_stack_depth = 0;
127 int sh4_call_trace_on = 0;
129 static inline trace_call( sh4addr_t source, sh4addr_t dest )
130 {
131 if( call_stack_depth < MAX_CALLSTACK ) {
132 call_stack[call_stack_depth].call_addr = source;
133 call_stack[call_stack_depth].target_addr = dest;
134 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
135 }
136 call_stack_depth++;
137 }
139 static inline trace_return( sh4addr_t source, sh4addr_t dest )
140 {
141 if( call_stack_depth > 0 ) {
142 call_stack_depth--;
143 }
144 }
146 void fprint_stack_trace( FILE *f )
147 {
148 int i = call_stack_depth -1;
149 if( i >= MAX_CALLSTACK )
150 i = MAX_CALLSTACK - 1;
151 for( ; i >= 0; i-- ) {
152 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
153 (call_stack_depth - i), call_stack[i].call_addr,
154 call_stack[i].target_addr, call_stack[i].stack_pointer );
155 }
156 }
158 #define TRACE_CALL( source, dest ) trace_call(source, dest)
159 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
160 #else
161 #define TRACE_CALL( dest, rts )
162 #define TRACE_RETURN( source, dest )
163 #endif
165 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
166 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
167 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
168 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
169 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
170 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
172 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
174 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
175 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
177 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
178 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
179 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
180 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
181 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
183 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
184 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
185 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
187 static void sh4_write_float( uint32_t addr, int reg )
188 {
189 if( IS_FPU_DOUBLESIZE() ) {
190 if( reg & 1 ) {
191 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
192 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
193 } else {
194 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
195 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
196 }
197 } else {
198 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
199 }
200 }
202 static void sh4_read_float( uint32_t addr, int reg )
203 {
204 if( IS_FPU_DOUBLESIZE() ) {
205 if( reg & 1 ) {
206 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
207 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
208 } else {
209 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
210 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
211 }
212 } else {
213 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
214 }
215 }
217 gboolean sh4_execute_instruction( void )
218 {
219 uint32_t pc;
220 unsigned short ir;
221 uint32_t tmp;
222 float ftmp;
223 double dtmp;
225 #define R0 sh4r.r[0]
226 pc = sh4r.pc;
227 if( pc > 0xFFFFFF00 ) {
228 /* SYSCALL Magic */
229 syscall_invoke( pc );
230 sh4r.in_delay_slot = 0;
231 pc = sh4r.pc = sh4r.pr;
232 sh4r.new_pc = sh4r.pc + 2;
233 }
234 CHECKRALIGN16(pc);
236 /* Read instruction */
237 uint32_t pageaddr = pc >> 12;
238 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
239 ir = sh4_icache[(pc&0xFFF)>>1];
240 } else {
241 sh4_icache = (uint16_t *)mem_get_page(pc);
242 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
243 /* If someone's actually been so daft as to try to execute out of an IO
244 * region, fallback on the full-blown memory read
245 */
246 sh4_icache = NULL;
247 ir = MEM_READ_WORD(pc);
248 } else {
249 sh4_icache_addr = pageaddr;
250 ir = sh4_icache[(pc&0xFFF)>>1];
251 }
252 }
253 %%
254 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
255 AND #imm, R0 {: R0 &= imm; :}
256 AND.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
257 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
258 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
259 OR #imm, R0 {: R0 |= imm; :}
260 OR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
261 TAS.B @Rn {:
262 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
263 sh4r.t = ( tmp == 0 ? 1 : 0 );
264 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
265 :}
266 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
267 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
268 TST.B #imm, @(R0, GBR) {: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); :}
269 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
270 XOR #imm, R0 {: R0 ^= imm; :}
271 XOR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
272 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
274 ROTL Rn {:
275 sh4r.t = sh4r.r[Rn] >> 31;
276 sh4r.r[Rn] <<= 1;
277 sh4r.r[Rn] |= sh4r.t;
278 :}
279 ROTR Rn {:
280 sh4r.t = sh4r.r[Rn] & 0x00000001;
281 sh4r.r[Rn] >>= 1;
282 sh4r.r[Rn] |= (sh4r.t << 31);
283 :}
284 ROTCL Rn {:
285 tmp = sh4r.r[Rn] >> 31;
286 sh4r.r[Rn] <<= 1;
287 sh4r.r[Rn] |= sh4r.t;
288 sh4r.t = tmp;
289 :}
290 ROTCR Rn {:
291 tmp = sh4r.r[Rn] & 0x00000001;
292 sh4r.r[Rn] >>= 1;
293 sh4r.r[Rn] |= (sh4r.t << 31 );
294 sh4r.t = tmp;
295 :}
296 SHAD Rm, Rn {:
297 tmp = sh4r.r[Rm];
298 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
299 else if( (tmp & 0x1F) == 0 )
300 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
301 else
302 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
303 :}
304 SHLD Rm, Rn {:
305 tmp = sh4r.r[Rm];
306 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
307 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
308 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
309 :}
310 SHAL Rn {:
311 sh4r.t = sh4r.r[Rn] >> 31;
312 sh4r.r[Rn] <<= 1;
313 :}
314 SHAR Rn {:
315 sh4r.t = sh4r.r[Rn] & 0x00000001;
316 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
317 :}
318 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
319 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
320 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
321 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
322 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
323 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
324 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
325 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
327 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
328 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
329 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
330 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
331 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
332 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
334 CLRT {: sh4r.t = 0; :}
335 SETT {: sh4r.t = 1; :}
336 CLRMAC {: sh4r.mac = 0; :}
337 LDTLB {: /* TODO */ :}
338 CLRS {: sh4r.s = 0; :}
339 SETS {: sh4r.s = 1; :}
340 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
341 NOP {: /* NOP */ :}
343 PREF @Rn {:
344 tmp = sh4r.r[Rn];
345 if( (tmp & 0xFC000000) == 0xE0000000 ) {
346 sh4_flush_store_queue(tmp);
347 }
348 :}
349 OCBI @Rn {: :}
350 OCBP @Rn {: :}
351 OCBWB @Rn {: :}
352 MOVCA.L R0, @Rn {:
353 tmp = sh4r.r[Rn];
354 CHECKWALIGN32(tmp);
355 MEM_WRITE_LONG( tmp, R0 );
356 :}
357 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
358 MOV.W Rm, @(R0, Rn) {:
359 CHECKWALIGN16( R0 + sh4r.r[Rn] );
360 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
361 :}
362 MOV.L Rm, @(R0, Rn) {:
363 CHECKWALIGN32( R0 + sh4r.r[Rn] );
364 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
365 :}
366 MOV.B @(R0, Rm), Rn {: sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); :}
367 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
368 sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
369 :}
370 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
371 sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
372 :}
373 MOV.L Rm, @(disp, Rn) {:
374 tmp = sh4r.r[Rn] + disp;
375 CHECKWALIGN32( tmp );
376 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
377 :}
378 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
379 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
380 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
381 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
382 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
383 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
384 MOV.L @(disp, Rm), Rn {:
385 tmp = sh4r.r[Rm] + disp;
386 CHECKRALIGN32( tmp );
387 sh4r.r[Rn] = MEM_READ_LONG( tmp );
388 :}
389 MOV.B @Rm, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); :}
390 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); :}
391 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); :}
392 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
393 MOV.B @Rm+, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; :}
394 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; :}
395 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; :}
396 MOV.L @(disp, PC), Rn {:
397 CHECKSLOTILLEGAL();
398 tmp = (pc&0xFFFFFFFC) + disp + 4;
399 sh4r.r[Rn] = MEM_READ_LONG( tmp );
400 :}
401 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
402 MOV.W R0, @(disp, GBR) {:
403 tmp = sh4r.gbr + disp;
404 CHECKWALIGN16( tmp );
405 MEM_WRITE_WORD( tmp, R0 );
406 :}
407 MOV.L R0, @(disp, GBR) {:
408 tmp = sh4r.gbr + disp;
409 CHECKWALIGN32( tmp );
410 MEM_WRITE_LONG( tmp, R0 );
411 :}
412 MOV.B @(disp, GBR), R0 {: R0 = MEM_READ_BYTE( sh4r.gbr + disp ); :}
413 MOV.W @(disp, GBR), R0 {:
414 tmp = sh4r.gbr + disp;
415 CHECKRALIGN16( tmp );
416 R0 = MEM_READ_WORD( tmp );
417 :}
418 MOV.L @(disp, GBR), R0 {:
419 tmp = sh4r.gbr + disp;
420 CHECKRALIGN32( tmp );
421 R0 = MEM_READ_LONG( tmp );
422 :}
423 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
424 MOV.W R0, @(disp, Rn) {:
425 tmp = sh4r.r[Rn] + disp;
426 CHECKWALIGN16( tmp );
427 MEM_WRITE_WORD( tmp, R0 );
428 :}
429 MOV.B @(disp, Rm), R0 {: R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); :}
430 MOV.W @(disp, Rm), R0 {:
431 tmp = sh4r.r[Rm] + disp;
432 CHECKRALIGN16( tmp );
433 R0 = MEM_READ_WORD( tmp );
434 :}
435 MOV.W @(disp, PC), Rn {:
436 CHECKSLOTILLEGAL();
437 tmp = pc + 4 + disp;
438 sh4r.r[Rn] = MEM_READ_WORD( tmp );
439 :}
440 MOVA @(disp, PC), R0 {:
441 CHECKSLOTILLEGAL();
442 R0 = (pc&0xFFFFFFFC) + disp + 4;
443 :}
444 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
446 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
447 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
448 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
449 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
450 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
451 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
452 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
453 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
454 CMP/STR Rm, Rn {:
455 /* set T = 1 if any byte in RM & RN is the same */
456 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
457 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
458 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
459 :}
461 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
462 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
463 ADDC Rm, Rn {:
464 tmp = sh4r.r[Rn];
465 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
466 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
467 :}
468 ADDV Rm, Rn {:
469 tmp = sh4r.r[Rn] + sh4r.r[Rm];
470 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
471 sh4r.r[Rn] = tmp;
472 :}
473 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
474 DIV0S Rm, Rn {:
475 sh4r.q = sh4r.r[Rn]>>31;
476 sh4r.m = sh4r.r[Rm]>>31;
477 sh4r.t = sh4r.q ^ sh4r.m;
478 :}
479 DIV1 Rm, Rn {:
480 /* This is derived from the sh4 manual with some simplifications */
481 uint32_t tmp0, tmp1, tmp2, dir;
483 dir = sh4r.q ^ sh4r.m;
484 sh4r.q = (sh4r.r[Rn] >> 31);
485 tmp2 = sh4r.r[Rm];
486 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
487 tmp0 = sh4r.r[Rn];
488 if( dir ) {
489 sh4r.r[Rn] += tmp2;
490 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
491 } else {
492 sh4r.r[Rn] -= tmp2;
493 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
494 }
495 sh4r.q ^= sh4r.m ^ tmp1;
496 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
497 :}
498 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
499 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
500 DT Rn {:
501 sh4r.r[Rn] --;
502 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
503 :}
504 MAC.W @Rm+, @Rn+ {:
505 CHECKRALIGN16( sh4r.r[Rn] );
506 CHECKRALIGN16( sh4r.r[Rm] );
507 int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
508 sh4r.r[Rn] += 2;
509 stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
510 sh4r.r[Rm] += 2;
511 if( sh4r.s ) {
512 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
513 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
514 sh4r.mac = 0x000000017FFFFFFFLL;
515 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
516 sh4r.mac = 0x0000000180000000LL;
517 } else {
518 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
519 ((uint32_t)(sh4r.mac + stmp));
520 }
521 } else {
522 sh4r.mac += SIGNEXT32(stmp);
523 }
524 :}
525 MAC.L @Rm+, @Rn+ {:
526 CHECKRALIGN32( sh4r.r[Rm] );
527 CHECKRALIGN32( sh4r.r[Rn] );
528 int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
529 sh4r.r[Rn] += 4;
530 tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
531 sh4r.r[Rm] += 4;
532 if( sh4r.s ) {
533 /* 48-bit Saturation. Yuch */
534 if( tmpl < (int64_t)0xFFFF800000000000LL )
535 tmpl = 0xFFFF800000000000LL;
536 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
537 tmpl = 0x00007FFFFFFFFFFFLL;
538 }
539 sh4r.mac = tmpl;
540 :}
541 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
542 (sh4r.r[Rm] * sh4r.r[Rn]); :}
543 MULU.W Rm, Rn {:
544 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
545 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
546 :}
547 MULS.W Rm, Rn {:
548 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
549 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
550 :}
551 NEGC Rm, Rn {:
552 tmp = 0 - sh4r.r[Rm];
553 sh4r.r[Rn] = tmp - sh4r.t;
554 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
555 :}
556 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
557 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
558 SUBC Rm, Rn {:
559 tmp = sh4r.r[Rn];
560 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
561 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
562 :}
564 BRAF Rn {:
565 CHECKSLOTILLEGAL();
566 CHECKDEST( pc + 4 + sh4r.r[Rn] );
567 sh4r.in_delay_slot = 1;
568 sh4r.pc = sh4r.new_pc;
569 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
570 return TRUE;
571 :}
572 BSRF Rn {:
573 CHECKSLOTILLEGAL();
574 CHECKDEST( pc + 4 + sh4r.r[Rn] );
575 sh4r.in_delay_slot = 1;
576 sh4r.pr = sh4r.pc + 4;
577 sh4r.pc = sh4r.new_pc;
578 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
579 TRACE_CALL( pc, sh4r.new_pc );
580 return TRUE;
581 :}
582 BT disp {:
583 CHECKSLOTILLEGAL();
584 if( sh4r.t ) {
585 CHECKDEST( sh4r.pc + disp + 4 )
586 sh4r.pc += disp + 4;
587 sh4r.new_pc = sh4r.pc + 2;
588 return TRUE;
589 }
590 :}
591 BF disp {:
592 CHECKSLOTILLEGAL();
593 if( !sh4r.t ) {
594 CHECKDEST( sh4r.pc + disp + 4 )
595 sh4r.pc += disp + 4;
596 sh4r.new_pc = sh4r.pc + 2;
597 return TRUE;
598 }
599 :}
600 BT/S disp {:
601 CHECKSLOTILLEGAL();
602 if( sh4r.t ) {
603 CHECKDEST( sh4r.pc + disp + 4 )
604 sh4r.in_delay_slot = 1;
605 sh4r.pc = sh4r.new_pc;
606 sh4r.new_pc = pc + disp + 4;
607 sh4r.in_delay_slot = 1;
608 return TRUE;
609 }
610 :}
611 BF/S disp {:
612 CHECKSLOTILLEGAL();
613 if( !sh4r.t ) {
614 CHECKDEST( sh4r.pc + disp + 4 )
615 sh4r.in_delay_slot = 1;
616 sh4r.pc = sh4r.new_pc;
617 sh4r.new_pc = pc + disp + 4;
618 return TRUE;
619 }
620 :}
621 BRA disp {:
622 CHECKSLOTILLEGAL();
623 CHECKDEST( sh4r.pc + disp + 4 );
624 sh4r.in_delay_slot = 1;
625 sh4r.pc = sh4r.new_pc;
626 sh4r.new_pc = pc + 4 + disp;
627 return TRUE;
628 :}
629 BSR disp {:
630 CHECKDEST( sh4r.pc + disp + 4 );
631 CHECKSLOTILLEGAL();
632 sh4r.in_delay_slot = 1;
633 sh4r.pr = pc + 4;
634 sh4r.pc = sh4r.new_pc;
635 sh4r.new_pc = pc + 4 + disp;
636 TRACE_CALL( pc, sh4r.new_pc );
637 return TRUE;
638 :}
639 TRAPA #imm {:
640 CHECKSLOTILLEGAL();
641 MMIO_WRITE( MMU, TRA, imm<<2 );
642 sh4r.pc += 2;
643 sh4_raise_exception( EXC_TRAP );
644 :}
645 RTS {:
646 CHECKSLOTILLEGAL();
647 CHECKDEST( sh4r.pr );
648 sh4r.in_delay_slot = 1;
649 sh4r.pc = sh4r.new_pc;
650 sh4r.new_pc = sh4r.pr;
651 TRACE_RETURN( pc, sh4r.new_pc );
652 return TRUE;
653 :}
654 SLEEP {:
655 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
656 sh4r.sh4_state = SH4_STATE_STANDBY;
657 } else {
658 sh4r.sh4_state = SH4_STATE_SLEEP;
659 }
660 return FALSE; /* Halt CPU */
661 :}
662 RTE {:
663 CHECKPRIV();
664 CHECKDEST( sh4r.spc );
665 CHECKSLOTILLEGAL();
666 sh4r.in_delay_slot = 1;
667 sh4r.pc = sh4r.new_pc;
668 sh4r.new_pc = sh4r.spc;
669 sh4_write_sr( sh4r.ssr );
670 return TRUE;
671 :}
672 JMP @Rn {:
673 CHECKDEST( sh4r.r[Rn] );
674 CHECKSLOTILLEGAL();
675 sh4r.in_delay_slot = 1;
676 sh4r.pc = sh4r.new_pc;
677 sh4r.new_pc = sh4r.r[Rn];
678 return TRUE;
679 :}
680 JSR @Rn {:
681 CHECKDEST( sh4r.r[Rn] );
682 CHECKSLOTILLEGAL();
683 sh4r.in_delay_slot = 1;
684 sh4r.pc = sh4r.new_pc;
685 sh4r.new_pc = sh4r.r[Rn];
686 sh4r.pr = pc + 4;
687 TRACE_CALL( pc, sh4r.new_pc );
688 return TRUE;
689 :}
690 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
691 STS.L MACH, @-Rn {:
692 sh4r.r[Rn] -= 4;
693 CHECKWALIGN32( sh4r.r[Rn] );
694 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
695 :}
696 STC.L SR, @-Rn {:
697 CHECKPRIV();
698 sh4r.r[Rn] -= 4;
699 CHECKWALIGN32( sh4r.r[Rn] );
700 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
701 :}
702 LDS.L @Rm+, MACH {:
703 CHECKRALIGN32( sh4r.r[Rm] );
704 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
705 (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
706 sh4r.r[Rm] += 4;
707 :}
708 LDC.L @Rm+, SR {:
709 CHECKSLOTILLEGAL();
710 CHECKPRIV();
711 CHECKWALIGN32( sh4r.r[Rm] );
712 sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );
713 sh4r.r[Rm] +=4;
714 :}
715 LDS Rm, MACH {:
716 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
717 (((uint64_t)sh4r.r[Rm])<<32);
718 :}
719 LDC Rm, SR {:
720 CHECKSLOTILLEGAL();
721 CHECKPRIV();
722 sh4_write_sr( sh4r.r[Rm] );
723 :}
724 LDC Rm, SGR {:
725 CHECKPRIV();
726 sh4r.sgr = sh4r.r[Rm];
727 :}
728 LDC.L @Rm+, SGR {:
729 CHECKPRIV();
730 CHECKRALIGN32( sh4r.r[Rm] );
731 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
732 sh4r.r[Rm] +=4;
733 :}
734 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
735 STS.L MACL, @-Rn {:
736 sh4r.r[Rn] -= 4;
737 CHECKWALIGN32( sh4r.r[Rn] );
738 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
739 :}
740 STC.L GBR, @-Rn {:
741 sh4r.r[Rn] -= 4;
742 CHECKWALIGN32( sh4r.r[Rn] );
743 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
744 :}
745 LDS.L @Rm+, MACL {:
746 CHECKRALIGN32( sh4r.r[Rm] );
747 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
748 (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
749 sh4r.r[Rm] += 4;
750 :}
751 LDC.L @Rm+, GBR {:
752 CHECKRALIGN32( sh4r.r[Rm] );
753 sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
754 sh4r.r[Rm] +=4;
755 :}
756 LDS Rm, MACL {:
757 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
758 (uint64_t)((uint32_t)(sh4r.r[Rm]));
759 :}
760 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
761 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
762 STS.L PR, @-Rn {:
763 sh4r.r[Rn] -= 4;
764 CHECKWALIGN32( sh4r.r[Rn] );
765 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
766 :}
767 STC.L VBR, @-Rn {:
768 CHECKPRIV();
769 sh4r.r[Rn] -= 4;
770 CHECKWALIGN32( sh4r.r[Rn] );
771 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
772 :}
773 LDS.L @Rm+, PR {:
774 CHECKRALIGN32( sh4r.r[Rm] );
775 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
776 sh4r.r[Rm] += 4;
777 :}
778 LDC.L @Rm+, VBR {:
779 CHECKPRIV();
780 CHECKRALIGN32( sh4r.r[Rm] );
781 sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
782 sh4r.r[Rm] +=4;
783 :}
784 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
785 LDC Rm, VBR {:
786 CHECKPRIV();
787 sh4r.vbr = sh4r.r[Rm];
788 :}
789 STC SGR, Rn {:
790 CHECKPRIV();
791 sh4r.r[Rn] = sh4r.sgr;
792 :}
793 STC.L SGR, @-Rn {:
794 CHECKPRIV();
795 sh4r.r[Rn] -= 4;
796 CHECKWALIGN32( sh4r.r[Rn] );
797 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
798 :}
799 STC.L SSR, @-Rn {:
800 CHECKPRIV();
801 sh4r.r[Rn] -= 4;
802 CHECKWALIGN32( sh4r.r[Rn] );
803 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
804 :}
805 LDC.L @Rm+, SSR {:
806 CHECKPRIV();
807 CHECKRALIGN32( sh4r.r[Rm] );
808 sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
809 sh4r.r[Rm] +=4;
810 :}
811 LDC Rm, SSR {:
812 CHECKPRIV();
813 sh4r.ssr = sh4r.r[Rm];
814 :}
815 STC.L SPC, @-Rn {:
816 CHECKPRIV();
817 sh4r.r[Rn] -= 4;
818 CHECKWALIGN32( sh4r.r[Rn] );
819 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
820 :}
821 LDC.L @Rm+, SPC {:
822 CHECKPRIV();
823 CHECKRALIGN32( sh4r.r[Rm] );
824 sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
825 sh4r.r[Rm] +=4;
826 :}
827 LDC Rm, SPC {:
828 CHECKPRIV();
829 sh4r.spc = sh4r.r[Rm];
830 :}
831 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
832 STS.L FPUL, @-Rn {:
833 sh4r.r[Rn] -= 4;
834 CHECKWALIGN32( sh4r.r[Rn] );
835 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
836 :}
837 LDS.L @Rm+, FPUL {:
838 CHECKRALIGN32( sh4r.r[Rm] );
839 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
840 sh4r.r[Rm] +=4;
841 :}
842 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
843 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
844 STS.L FPSCR, @-Rn {:
845 sh4r.r[Rn] -= 4;
846 CHECKWALIGN32( sh4r.r[Rn] );
847 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
848 :}
849 LDS.L @Rm+, FPSCR {:
850 CHECKRALIGN32( sh4r.r[Rm] );
851 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
852 sh4r.r[Rm] +=4;
853 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
854 :}
855 LDS Rm, FPSCR {:
856 sh4r.fpscr = sh4r.r[Rm];
857 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
858 :}
859 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
860 STC.L DBR, @-Rn {:
861 CHECKPRIV();
862 sh4r.r[Rn] -= 4;
863 CHECKWALIGN32( sh4r.r[Rn] );
864 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
865 :}
866 LDC.L @Rm+, DBR {:
867 CHECKPRIV();
868 CHECKRALIGN32( sh4r.r[Rm] );
869 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
870 sh4r.r[Rm] +=4;
871 :}
872 LDC Rm, DBR {:
873 CHECKPRIV();
874 sh4r.dbr = sh4r.r[Rm];
875 :}
876 STC.L Rm_BANK, @-Rn {:
877 CHECKPRIV();
878 sh4r.r[Rn] -= 4;
879 CHECKWALIGN32( sh4r.r[Rn] );
880 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
881 :}
882 LDC.L @Rm+, Rn_BANK {:
883 CHECKPRIV();
884 CHECKRALIGN32( sh4r.r[Rm] );
885 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
886 sh4r.r[Rm] += 4;
887 :}
888 LDC Rm, Rn_BANK {:
889 CHECKPRIV();
890 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
891 :}
892 STC SR, Rn {:
893 CHECKPRIV();
894 sh4r.r[Rn] = sh4_read_sr();
895 :}
896 STC GBR, Rn {:
897 CHECKPRIV();
898 sh4r.r[Rn] = sh4r.gbr;
899 :}
900 STC VBR, Rn {:
901 CHECKPRIV();
902 sh4r.r[Rn] = sh4r.vbr;
903 :}
904 STC SSR, Rn {:
905 CHECKPRIV();
906 sh4r.r[Rn] = sh4r.ssr;
907 :}
908 STC SPC, Rn {:
909 CHECKPRIV();
910 sh4r.r[Rn] = sh4r.spc;
911 :}
912 STC Rm_BANK, Rn {:
913 CHECKPRIV();
914 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
915 :}
917 FADD FRm, FRn {:
918 CHECKFPUEN();
919 if( IS_FPU_DOUBLEPREC() ) {
920 DR(FRn) += DR(FRm);
921 } else {
922 FR(FRn) += FR(FRm);
923 }
924 :}
925 FSUB FRm, FRn {:
926 CHECKFPUEN();
927 if( IS_FPU_DOUBLEPREC() ) {
928 DR(FRn) -= DR(FRm);
929 } else {
930 FR(FRn) -= FR(FRm);
931 }
932 :}
934 FMUL FRm, FRn {:
935 CHECKFPUEN();
936 if( IS_FPU_DOUBLEPREC() ) {
937 DR(FRn) *= DR(FRm);
938 } else {
939 FR(FRn) *= FR(FRm);
940 }
941 :}
943 FDIV FRm, FRn {:
944 CHECKFPUEN();
945 if( IS_FPU_DOUBLEPREC() ) {
946 DR(FRn) /= DR(FRm);
947 } else {
948 FR(FRn) /= FR(FRm);
949 }
950 :}
952 FCMP/EQ FRm, FRn {:
953 CHECKFPUEN();
954 if( IS_FPU_DOUBLEPREC() ) {
955 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
956 } else {
957 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
958 }
959 :}
961 FCMP/GT FRm, FRn {:
962 CHECKFPUEN();
963 if( IS_FPU_DOUBLEPREC() ) {
964 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
965 } else {
966 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
967 }
968 :}
970 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
971 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
972 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
973 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
974 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
975 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
976 FMOV FRm, FRn {:
977 if( IS_FPU_DOUBLESIZE() )
978 DR(FRn) = DR(FRm);
979 else
980 FR(FRn) = FR(FRm);
981 :}
982 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
983 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
984 FLOAT FPUL, FRn {:
985 CHECKFPUEN();
986 if( IS_FPU_DOUBLEPREC() ) {
987 if( FRn&1 ) { // No, really...
988 dtmp = (double)FPULi;
989 FR(FRn) = *(((float *)&dtmp)+1);
990 } else {
991 DRF(FRn>>1) = (double)FPULi;
992 }
993 } else {
994 FR(FRn) = (float)FPULi;
995 }
996 :}
997 FTRC FRm, FPUL {:
998 CHECKFPUEN();
999 if( IS_FPU_DOUBLEPREC() ) {
1000 if( FRm&1 ) {
1001 dtmp = 0;
1002 *(((float *)&dtmp)+1) = FR(FRm);
1003 } else {
1004 dtmp = DRF(FRm>>1);
1005 }
1006 if( dtmp >= MAX_INTF )
1007 FPULi = MAX_INT;
1008 else if( dtmp <= MIN_INTF )
1009 FPULi = MIN_INT;
1010 else
1011 FPULi = (int32_t)dtmp;
1012 } else {
1013 ftmp = FR(FRm);
1014 if( ftmp >= MAX_INTF )
1015 FPULi = MAX_INT;
1016 else if( ftmp <= MIN_INTF )
1017 FPULi = MIN_INT;
1018 else
1019 FPULi = (int32_t)ftmp;
1020 }
1021 :}
1022 FNEG FRn {:
1023 CHECKFPUEN();
1024 if( IS_FPU_DOUBLEPREC() ) {
1025 DR(FRn) = -DR(FRn);
1026 } else {
1027 FR(FRn) = -FR(FRn);
1028 }
1029 :}
1030 FABS FRn {:
1031 CHECKFPUEN();
1032 if( IS_FPU_DOUBLEPREC() ) {
1033 DR(FRn) = fabs(DR(FRn));
1034 } else {
1035 FR(FRn) = fabsf(FR(FRn));
1036 }
1037 :}
1038 FSQRT FRn {:
1039 CHECKFPUEN();
1040 if( IS_FPU_DOUBLEPREC() ) {
1041 DR(FRn) = sqrt(DR(FRn));
1042 } else {
1043 FR(FRn) = sqrtf(FR(FRn));
1044 }
1045 :}
1046 FLDI0 FRn {:
1047 CHECKFPUEN();
1048 if( IS_FPU_DOUBLEPREC() ) {
1049 DR(FRn) = 0.0;
1050 } else {
1051 FR(FRn) = 0.0;
1052 }
1053 :}
1054 FLDI1 FRn {:
1055 CHECKFPUEN();
1056 if( IS_FPU_DOUBLEPREC() ) {
1057 DR(FRn) = 1.0;
1058 } else {
1059 FR(FRn) = 1.0;
1060 }
1061 :}
1062 FMAC FR0, FRm, FRn {:
1063 CHECKFPUEN();
1064 if( IS_FPU_DOUBLEPREC() ) {
1065 DR(FRn) += DR(FRm)*DR(0);
1066 } else {
1067 FR(FRn) += FR(FRm)*FR(0);
1068 }
1069 :}
1070 FRCHG {:
1071 CHECKFPUEN();
1072 sh4r.fpscr ^= FPSCR_FR;
1073 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1074 :}
1075 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1076 FCNVSD FPUL, FRn {:
1077 CHECKFPUEN();
1078 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1079 DR(FRn) = (double)FPULf;
1080 }
1081 :}
1082 FCNVDS FRm, FPUL {:
1083 CHECKFPUEN();
1084 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1085 FPULf = (float)DR(FRm);
1086 }
1087 :}
1089 FSRRA FRn {:
1090 CHECKFPUEN();
1091 if( !IS_FPU_DOUBLEPREC() ) {
1092 FR(FRn) = 1.0/sqrtf(FR(FRn));
1093 }
1094 :}
1095 FIPR FVm, FVn {:
1096 CHECKFPUEN();
1097 if( !IS_FPU_DOUBLEPREC() ) {
1098 int tmp2 = FVn<<2;
1099 tmp = FVm<<2;
1100 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1101 FR(tmp+1)*FR(tmp2+1) +
1102 FR(tmp+2)*FR(tmp2+2) +
1103 FR(tmp+3)*FR(tmp2+3);
1104 }
1105 :}
1106 FSCA FPUL, FRn {:
1107 CHECKFPUEN();
1108 if( !IS_FPU_DOUBLEPREC() ) {
1109 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
1110 /*
1111 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1112 FR(FRn) = sinf(angle);
1113 FR((FRn)+1) = cosf(angle);
1114 */
1115 }
1116 :}
1117 FTRV XMTRX, FVn {:
1118 CHECKFPUEN();
1119 if( !IS_FPU_DOUBLEPREC() ) {
1120 sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
1121 /*
1122 tmp = FVn<<2;
1123 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
1124 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1125 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
1126 xf[9]*fv[2] + xf[13]*fv[3];
1127 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
1128 xf[8]*fv[2] + xf[12]*fv[3];
1129 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
1130 xf[11]*fv[2] + xf[15]*fv[3];
1131 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
1132 xf[10]*fv[2] + xf[14]*fv[3];
1133 */
1134 }
1135 :}
1136 UNDEF {:
1137 UNDEF(ir);
1138 :}
1139 %%
1140 sh4r.pc = sh4r.new_pc;
1141 sh4r.new_pc += 2;
1142 sh4r.in_delay_slot = 0;
1143 return TRUE;
1144 }
.