filename | src/sh4/sh4.c |
changeset | 790:a0c7d28bbb0c |
prev | 740:dd11269ee48b |
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author | nkeynes |
date | Thu Aug 07 23:32:34 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Unroll first iteration of the bounding loop in ta_commit_polygon - more to remove the compiler warnings than for performance really. |
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1 /**
2 * $Id$
3 *
4 * SH4 parent module for all CPU modes and SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include <setjmp.h>
23 #include <assert.h>
24 #include "lxdream.h"
25 #include "dreamcast.h"
26 #include "mem.h"
27 #include "clock.h"
28 #include "eventq.h"
29 #include "syscall.h"
30 #include "sh4/intc.h"
31 #include "sh4/sh4core.h"
32 #include "sh4/sh4mmio.h"
33 #include "sh4/sh4stat.h"
34 #include "sh4/sh4trans.h"
35 #include "sh4/xltcache.h"
37 void sh4_init( void );
38 void sh4_xlat_init( void );
39 void sh4_reset( void );
40 void sh4_start( void );
41 void sh4_stop( void );
42 void sh4_save_state( FILE *f );
43 int sh4_load_state( FILE *f );
45 uint32_t sh4_run_slice( uint32_t );
46 uint32_t sh4_xlat_run_slice( uint32_t );
48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
49 sh4_start, sh4_run_slice, sh4_stop,
50 sh4_save_state, sh4_load_state };
52 struct sh4_registers sh4r;
53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
54 int sh4_breakpoint_count = 0;
55 sh4ptr_t sh4_main_ram;
56 gboolean sh4_starting = FALSE;
57 static gboolean sh4_use_translator = FALSE;
58 static jmp_buf sh4_exit_jmp_buf;
59 static gboolean sh4_running = FALSE;
60 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
62 void sh4_translate_set_enabled( gboolean use )
63 {
64 // No-op if the translator was not built
65 #ifdef SH4_TRANSLATOR
66 xlat_cache_init();
67 if( use ) {
68 sh4_translate_init();
69 }
70 sh4_use_translator = use;
71 #endif
72 }
74 gboolean sh4_translate_is_enabled()
75 {
76 return sh4_use_translator;
77 }
79 void sh4_init(void)
80 {
81 register_io_regions( mmio_list_sh4mmio );
82 sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
83 MMU_init();
84 TMU_init();
85 sh4_reset();
86 #ifdef ENABLE_SH4STATS
87 sh4_stats_reset();
88 #endif
89 }
91 void sh4_start(void)
92 {
93 sh4_starting = TRUE;
94 }
96 void sh4_reset(void)
97 {
98 if( sh4_use_translator ) {
99 xlat_flush_cache();
100 }
102 /* zero everything out, for the sake of having a consistent state. */
103 memset( &sh4r, 0, sizeof(sh4r) );
105 /* Resume running if we were halted */
106 sh4r.sh4_state = SH4_STATE_RUNNING;
108 sh4r.pc = 0xA0000000;
109 sh4r.new_pc= 0xA0000002;
110 sh4r.vbr = 0x00000000;
111 sh4r.fpscr = 0x00040001;
112 sh4r.sr = 0x700000F0;
114 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
115 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
117 /* Peripheral modules */
118 CPG_reset();
119 INTC_reset();
120 MMU_reset();
121 TMU_reset();
122 SCIF_reset();
124 #ifdef ENABLE_SH4STATS
125 sh4_stats_reset();
126 #endif
127 }
129 void sh4_stop(void)
130 {
131 if( sh4_use_translator ) {
132 /* If we were running with the translator, update new_pc and in_delay_slot */
133 sh4r.new_pc = sh4r.pc+2;
134 sh4r.in_delay_slot = FALSE;
135 }
137 }
139 /**
140 * Execute a timeslice using translated code only (ie translate/execute loop)
141 */
142 uint32_t sh4_run_slice( uint32_t nanosecs )
143 {
144 sh4r.slice_cycle = 0;
146 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
147 sh4_sleep_run_slice(nanosecs);
148 }
150 /* Setup for sudden vm exits */
151 switch( setjmp(sh4_exit_jmp_buf) ) {
152 case CORE_EXIT_BREAKPOINT:
153 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
154 /* fallthrough */
155 case CORE_EXIT_HALT:
156 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
157 TMU_run_slice( sh4r.slice_cycle );
158 SCIF_run_slice( sh4r.slice_cycle );
159 dreamcast_stop();
160 return sh4r.slice_cycle;
161 }
162 case CORE_EXIT_SYSRESET:
163 dreamcast_reset();
164 break;
165 case CORE_EXIT_SLEEP:
166 sh4_sleep_run_slice(nanosecs);
167 break;
168 case CORE_EXIT_FLUSH_ICACHE:
169 #ifdef SH4_TRANSLATOR
170 xlat_flush_cache();
171 #endif
172 break;
173 }
175 sh4_running = TRUE;
177 /* Execute the core's real slice */
178 #ifdef SH4_TRANSLATOR
179 if( sh4_use_translator ) {
180 sh4_translate_run_slice(nanosecs);
181 } else {
182 sh4_emulate_run_slice(nanosecs);
183 }
184 #else
185 sh4_emulate_run_slice(nanosecs);
186 #endif
188 /* And finish off the peripherals afterwards */
190 sh4_running = FALSE;
191 sh4_starting = FALSE;
192 sh4r.slice_cycle = nanosecs;
193 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
194 TMU_run_slice( nanosecs );
195 SCIF_run_slice( nanosecs );
196 }
197 return nanosecs;
198 }
200 void sh4_core_exit( int exit_code )
201 {
202 if( sh4_running ) {
203 #ifdef SH4_TRANSLATOR
204 if( sh4_use_translator ) {
205 sh4_translate_exit_recover();
206 }
207 #endif
208 // longjmp back into sh4_run_slice
209 sh4_running = FALSE;
210 longjmp(sh4_exit_jmp_buf, exit_code);
211 }
212 }
214 void sh4_flush_icache()
215 {
216 #ifdef SH4_TRANSLATOR
217 // FIXME: Special case needs to be generalized
218 if( sh4_use_translator ) {
219 if( sh4_translate_flush_cache() ) {
220 longjmp(sh4_exit_jmp_buf, CORE_EXIT_CONTINUE);
221 }
222 }
223 #endif
224 }
226 void sh4_save_state( FILE *f )
227 {
228 if( sh4_use_translator ) {
229 /* If we were running with the translator, update new_pc and in_delay_slot */
230 sh4r.new_pc = sh4r.pc+2;
231 sh4r.in_delay_slot = FALSE;
232 }
234 fwrite( &sh4r, sizeof(sh4r), 1, f );
235 MMU_save_state( f );
236 INTC_save_state( f );
237 TMU_save_state( f );
238 SCIF_save_state( f );
239 }
241 int sh4_load_state( FILE * f )
242 {
243 if( sh4_use_translator ) {
244 xlat_flush_cache();
245 }
246 fread( &sh4r, sizeof(sh4r), 1, f );
247 MMU_load_state( f );
248 INTC_load_state( f );
249 TMU_load_state( f );
250 return SCIF_load_state( f );
251 }
254 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
255 {
256 sh4_breakpoints[sh4_breakpoint_count].address = pc;
257 sh4_breakpoints[sh4_breakpoint_count].type = type;
258 if( sh4_use_translator ) {
259 xlat_invalidate_word( pc );
260 }
261 sh4_breakpoint_count++;
262 }
264 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
265 {
266 int i;
268 for( i=0; i<sh4_breakpoint_count; i++ ) {
269 if( sh4_breakpoints[i].address == pc &&
270 sh4_breakpoints[i].type == type ) {
271 while( ++i < sh4_breakpoint_count ) {
272 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
273 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
274 }
275 if( sh4_use_translator ) {
276 xlat_invalidate_word( pc );
277 }
278 sh4_breakpoint_count--;
279 return TRUE;
280 }
281 }
282 return FALSE;
283 }
285 int sh4_get_breakpoint( uint32_t pc )
286 {
287 int i;
288 for( i=0; i<sh4_breakpoint_count; i++ ) {
289 if( sh4_breakpoints[i].address == pc )
290 return sh4_breakpoints[i].type;
291 }
292 return 0;
293 }
295 void sh4_set_pc( int pc )
296 {
297 sh4r.pc = pc;
298 sh4r.new_pc = pc+2;
299 }
302 /******************************* Support methods ***************************/
304 static void sh4_switch_banks( )
305 {
306 uint32_t tmp[8];
308 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
309 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
310 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
311 }
313 void sh4_switch_fr_banks()
314 {
315 int i;
316 for( i=0; i<16; i++ ) {
317 float tmp = sh4r.fr[0][i];
318 sh4r.fr[0][i] = sh4r.fr[1][i];
319 sh4r.fr[1][i] = tmp;
320 }
321 }
323 void sh4_write_sr( uint32_t newval )
324 {
325 int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
326 int newbank = (newval&SR_MDRB) == SR_MDRB;
327 if( oldbank != newbank )
328 sh4_switch_banks();
329 sh4r.sr = newval;
330 sh4r.t = (newval&SR_T) ? 1 : 0;
331 sh4r.s = (newval&SR_S) ? 1 : 0;
332 sh4r.m = (newval&SR_M) ? 1 : 0;
333 sh4r.q = (newval&SR_Q) ? 1 : 0;
334 intc_mask_changed();
335 }
337 void sh4_write_fpscr( uint32_t newval )
338 {
339 if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
340 sh4_switch_fr_banks();
341 }
342 sh4r.fpscr = newval;
343 }
345 uint32_t sh4_read_sr( void )
346 {
347 /* synchronize sh4r.sr with the various bitflags */
348 sh4r.sr &= SR_MQSTMASK;
349 if( sh4r.t ) sh4r.sr |= SR_T;
350 if( sh4r.s ) sh4r.sr |= SR_S;
351 if( sh4r.m ) sh4r.sr |= SR_M;
352 if( sh4r.q ) sh4r.sr |= SR_Q;
353 return sh4r.sr;
354 }
358 #define RAISE( x, v ) do{ \
359 if( sh4r.vbr == 0 ) { \
360 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
361 sh4_core_exit(CORE_EXIT_HALT); return FALSE; \
362 } else { \
363 sh4r.spc = sh4r.pc; \
364 sh4r.ssr = sh4_read_sr(); \
365 sh4r.sgr = sh4r.r[15]; \
366 MMIO_WRITE(MMU,EXPEVT,x); \
367 sh4r.pc = sh4r.vbr + v; \
368 sh4r.new_pc = sh4r.pc + 2; \
369 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
370 if( sh4r.in_delay_slot ) { \
371 sh4r.in_delay_slot = 0; \
372 sh4r.spc -= 2; \
373 } \
374 } \
375 return TRUE; } while(0)
377 /**
378 * Raise a general CPU exception for the specified exception code.
379 * (NOT for TRAPA or TLB exceptions)
380 */
381 gboolean sh4_raise_exception( int code )
382 {
383 RAISE( code, EXV_EXCEPTION );
384 }
386 /**
387 * Raise a CPU reset exception with the specified exception code.
388 */
389 gboolean sh4_raise_reset( int code )
390 {
391 // FIXME: reset modules as per "manual reset"
392 sh4_reset();
393 MMIO_WRITE(MMU,EXPEVT,code);
394 sh4r.vbr = 0;
395 sh4r.pc = 0xA0000000;
396 sh4r.new_pc = sh4r.pc + 2;
397 sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
398 &(~SR_FD) );
399 return TRUE;
400 }
402 gboolean sh4_raise_trap( int trap )
403 {
404 MMIO_WRITE( MMU, TRA, trap<<2 );
405 RAISE( EXC_TRAP, EXV_EXCEPTION );
406 }
408 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
409 if( sh4r.in_delay_slot ) {
410 return sh4_raise_exception(slot_code);
411 } else {
412 return sh4_raise_exception(normal_code);
413 }
414 }
416 gboolean sh4_raise_tlb_exception( int code )
417 {
418 RAISE( code, EXV_TLBMISS );
419 }
421 void sh4_accept_interrupt( void )
422 {
423 uint32_t code = intc_accept_interrupt();
424 sh4r.ssr = sh4_read_sr();
425 sh4r.spc = sh4r.pc;
426 sh4r.sgr = sh4r.r[15];
427 sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
428 MMIO_WRITE( MMU, INTEVT, code );
429 sh4r.pc = sh4r.vbr + 0x600;
430 sh4r.new_pc = sh4r.pc + 2;
431 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
432 }
434 void signsat48( void )
435 {
436 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
437 sh4r.mac = 0xFFFF800000000000LL;
438 else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
439 sh4r.mac = 0x00007FFFFFFFFFFFLL;
440 }
442 void sh4_fsca( uint32_t anglei, float *fr )
443 {
444 float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
445 *fr++ = cosf(angle);
446 *fr = sinf(angle);
447 }
449 /**
450 * Enter sleep mode (eg by executing a SLEEP instruction).
451 * Sets sh4_state appropriately and ensures any stopping peripheral modules
452 * are up to date.
453 */
454 void sh4_sleep(void)
455 {
456 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
457 sh4r.sh4_state = SH4_STATE_STANDBY;
458 /* Bring all running peripheral modules up to date, and then halt them. */
459 TMU_run_slice( sh4r.slice_cycle );
460 SCIF_run_slice( sh4r.slice_cycle );
461 } else {
462 if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
463 sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
464 /* Halt DMAC but other peripherals still running */
466 } else {
467 sh4r.sh4_state = SH4_STATE_SLEEP;
468 }
469 }
470 sh4_core_exit( CORE_EXIT_SLEEP );
471 }
473 /**
474 * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
475 * and restarts any peripheral devices that were stopped.
476 */
477 void sh4_wakeup(void)
478 {
479 switch( sh4r.sh4_state ) {
480 case SH4_STATE_STANDBY:
481 break;
482 case SH4_STATE_DEEP_SLEEP:
483 break;
484 case SH4_STATE_SLEEP:
485 break;
486 }
487 sh4r.sh4_state = SH4_STATE_RUNNING;
488 }
490 /**
491 * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
492 * Returns when either the SH4 wakes up (interrupt received) or the end of
493 * the slice is reached. Updates sh4.slice_cycle with the exit time and
494 * returns the same value.
495 */
496 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
497 {
498 int sleep_state = sh4r.sh4_state;
499 assert( sleep_state != SH4_STATE_RUNNING );
501 while( sh4r.event_pending < nanosecs ) {
502 sh4r.slice_cycle = sh4r.event_pending;
503 if( sh4r.event_types & PENDING_EVENT ) {
504 event_execute();
505 }
506 if( sh4r.event_types & PENDING_IRQ ) {
507 sh4_wakeup();
508 return sh4r.slice_cycle;
509 }
510 }
511 sh4r.slice_cycle = nanosecs;
512 return sh4r.slice_cycle;
513 }
516 /**
517 * Compute the matrix tranform of fv given the matrix xf.
518 * Both fv and xf are word-swapped as per the sh4r.fr banks
519 */
520 void sh4_ftrv( float *target )
521 {
522 float fv[4] = { target[1], target[0], target[3], target[2] };
523 target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
524 sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
525 target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
526 sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
527 target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
528 sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
529 target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
530 sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
531 }
533 gboolean sh4_has_page( sh4vma_t vma )
534 {
535 sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
536 return addr != MMU_VMA_ERROR && mem_has_page(addr);
537 }
.