lxdream 0.9.1| filename | src/sh4/sh4core.c |
| changeset | 104:94b2d9962b59 |
| prev | 102:844a3f2a76ff |
| next | 116:87e3bea309a5 |
| author | nkeynes |
| date | Tue Mar 14 11:44:04 2006 +0000 (16 years ago) |
| permissions | -rw-r--r-- |
| last change | Remove call-slot-delay on syscall ensure dreamcast_stop on error conditions for the time being |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4core.c,v 1.22 2006-03-14 11:44:04 nkeynes Exp $
3 *
4 * SH4 emulation core, and parent module for all the SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include "dream.h"
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
25 #include "sh4/intc.h"
26 #include "mem.h"
27 #include "clock.h"
28 #include "syscall.h"
30 /* CPU-generated exception code/vector pairs */
31 #define EXC_POWER_RESET 0x000 /* vector special */
32 #define EXC_MANUAL_RESET 0x020
33 #define EXC_SLOT_ILLEGAL 0x1A0
34 #define EXC_ILLEGAL 0x180
35 #define EXV_ILLEGAL 0x100
36 #define EXC_TRAP 0x160
37 #define EXV_TRAP 0x100
38 #define EXC_FPDISABLE 0x800
39 #define EXV_FPDISABLE 0x100
41 /********************** SH4 Module Definition ****************************/
43 void sh4_init( void );
44 void sh4_reset( void );
45 uint32_t sh4_run_slice( uint32_t );
46 void sh4_start( void );
47 void sh4_stop( void );
48 void sh4_save_state( FILE *f );
49 int sh4_load_state( FILE *f );
51 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
52 NULL, sh4_run_slice, sh4_stop,
53 sh4_save_state, sh4_load_state };
55 struct sh4_registers sh4r;
57 void sh4_init(void)
58 {
59 register_io_regions( mmio_list_sh4mmio );
60 mmu_init();
61 sh4_reset();
62 }
64 void sh4_reset(void)
65 {
66 /* zero everything out, for the sake of having a consistent state. */
67 memset( &sh4r, 0, sizeof(sh4r) );
69 /* Resume running if we were halted */
70 sh4r.sh4_state = SH4_STATE_RUNNING;
72 sh4r.pc = 0xA0000000;
73 sh4r.new_pc= 0xA0000002;
74 sh4r.vbr = 0x00000000;
75 sh4r.fpscr = 0x00040001;
76 sh4r.sr = 0x700000F0;
78 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
79 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
81 /* Peripheral modules */
82 intc_reset();
83 SCIF_reset();
84 }
86 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
87 static int sh4_breakpoint_count = 0;
89 void sh4_set_breakpoint( uint32_t pc, int type )
90 {
91 sh4_breakpoints[sh4_breakpoint_count].address = pc;
92 sh4_breakpoints[sh4_breakpoint_count].type = type;
93 sh4_breakpoint_count++;
94 }
96 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
97 {
98 int i;
100 for( i=0; i<sh4_breakpoint_count; i++ ) {
101 if( sh4_breakpoints[i].address == pc &&
102 sh4_breakpoints[i].type == type ) {
103 while( ++i < sh4_breakpoint_count ) {
104 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
105 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
106 }
107 sh4_breakpoint_count--;
108 return TRUE;
109 }
110 }
111 return FALSE;
112 }
114 int sh4_get_breakpoint( uint32_t pc )
115 {
116 int i;
117 for( i=0; i<sh4_breakpoint_count; i++ ) {
118 if( sh4_breakpoints[i].address == pc )
119 return sh4_breakpoints[i].type;
120 }
121 return 0;
122 }
124 uint32_t sh4_run_slice( uint32_t nanosecs )
125 {
126 int target = sh4r.icount + nanosecs / sh4_cpu_period;
127 int start = sh4r.icount;
128 int i;
130 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
131 if( sh4r.int_pending != 0 )
132 sh4r.sh4_state = SH4_STATE_RUNNING;;
133 }
135 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
136 if( !sh4_execute_instruction() )
137 break;
138 #ifdef ENABLE_DEBUG_MODE
139 for( i=0; i<sh4_breakpoint_count; i++ ) {
140 if( sh4_breakpoints[i].address == sh4r.pc ) {
141 break;
142 }
143 }
144 if( i != sh4_breakpoint_count ) {
145 dreamcast_stop();
146 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
147 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
148 break;
149 }
150 #endif
151 }
153 /* If we aborted early, but the cpu is still technically running,
154 * we're doing a hard abort - cut the timeslice back to what we
155 * actually executed
156 */
157 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
158 nanosecs = sh4r.slice_cycle;
159 }
160 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
161 TMU_run_slice( nanosecs );
162 SCIF_run_slice( nanosecs );
163 }
164 sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
165 return nanosecs;
166 }
168 void sh4_stop(void)
169 {
171 }
173 void sh4_save_state( FILE *f )
174 {
175 fwrite( &sh4r, sizeof(sh4r), 1, f );
176 TMU_save_state( f );
177 SCIF_save_state( f );
178 }
180 int sh4_load_state( FILE * f )
181 {
182 fread( &sh4r, sizeof(sh4r), 1, f );
183 TMU_load_state( f );
184 return SCIF_load_state( f );
185 }
187 /********************** SH4 emulation core ****************************/
189 void sh4_set_pc( int pc )
190 {
191 sh4r.pc = pc;
192 sh4r.new_pc = pc+2;
193 }
195 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
196 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
198 #define RAISE( x, v ) do{ \
199 if( sh4r.vbr == 0 ) { \
200 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
201 dreamcast_stop(); return FALSE; \
202 } else { \
203 sh4r.spc = sh4r.pc + 2; \
204 sh4r.ssr = sh4_read_sr(); \
205 sh4r.sgr = sh4r.r[15]; \
206 MMIO_WRITE(MMU,EXPEVT,x); \
207 sh4r.pc = sh4r.vbr + v; \
208 sh4r.new_pc = sh4r.pc + 2; \
209 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
210 } \
211 return TRUE; } while(0)
213 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
214 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
215 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
216 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
217 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
218 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
220 #define MEM_FR_READ( addr, reg ) *((uint32_t *)&FR(reg)) = sh4_read_long(addr)
222 #define MEM_DR_READ( addr, reg ) do { \
223 *((uint32_t *)&FR((reg) & 0x0E)) = sh4_read_long(addr); \
224 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4); } while(0)
226 #define MEM_FR_WRITE( addr, reg ) sh4_write_long( addr, *((uint32_t *)&FR((reg))) )
228 #define MEM_DR_WRITE( addr, reg ) do { \
229 sh4_write_long( addr, *((uint32_t *)&FR((reg)&0x0E)) ); \
230 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); } while(0)
232 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
234 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_READ(addr, reg ); else MEM_FR_READ( addr, reg )
236 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_WRITE(addr, reg ); else MEM_FR_WRITE( addr, reg )
238 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
239 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
240 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
241 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
242 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
244 static void sh4_switch_banks( )
245 {
246 uint32_t tmp[8];
248 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
249 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
250 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
251 }
253 static void sh4_load_sr( uint32_t newval )
254 {
255 if( (newval ^ sh4r.sr) & SR_RB )
256 sh4_switch_banks();
257 sh4r.sr = newval;
258 sh4r.t = (newval&SR_T) ? 1 : 0;
259 sh4r.s = (newval&SR_S) ? 1 : 0;
260 sh4r.m = (newval&SR_M) ? 1 : 0;
261 sh4r.q = (newval&SR_Q) ? 1 : 0;
262 intc_mask_changed();
263 }
265 static uint32_t sh4_read_sr( void )
266 {
267 /* synchronize sh4r.sr with the various bitflags */
268 sh4r.sr &= SR_MQSTMASK;
269 if( sh4r.t ) sh4r.sr |= SR_T;
270 if( sh4r.s ) sh4r.sr |= SR_S;
271 if( sh4r.m ) sh4r.sr |= SR_M;
272 if( sh4r.q ) sh4r.sr |= SR_Q;
273 return sh4r.sr;
274 }
275 /* function for external use */
276 void sh4_raise_exception( int code, int vector )
277 {
278 RAISE(code, vector);
279 }
281 static void sh4_accept_interrupt( void )
282 {
283 uint32_t code = intc_accept_interrupt();
284 sh4r.ssr = sh4_read_sr();
285 sh4r.spc = sh4r.pc;
286 sh4r.sgr = sh4r.r[15];
287 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
288 MMIO_WRITE( MMU, INTEVT, code );
289 sh4r.pc = sh4r.vbr + 0x600;
290 sh4r.new_pc = sh4r.pc + 2;
291 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
292 }
294 gboolean sh4_execute_instruction( void )
295 {
296 uint32_t pc;
297 unsigned short ir;
298 uint32_t tmp;
299 uint64_t tmpl;
301 #define R0 sh4r.r[0]
302 #define FR0 FR(0)
303 #define DR0 DR(0)
304 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
305 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
306 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
307 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
308 #define DISP8(ir) (ir&0x00FF)
309 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
310 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
311 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
312 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
313 #define FRNn(ir) ((ir&0x0F00)>>8)
314 #define FRMn(ir) ((ir&0x00F0)>>4)
315 #define DRNn(ir) ((ir&0x0E00)>>9)
316 #define DRMn(ir) ((ir&0x00E0)>>5)
317 #define FVN(ir) ((ir&0x0C00)>>8)
318 #define FVM(ir) ((ir&0x0300)>>6)
319 #define FRN(ir) FR(FRNn(ir))
320 #define FRM(ir) FR(FRMn(ir))
321 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
322 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
323 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
324 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
325 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
326 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
327 #define FPULf *((float *)&sh4r.fpul)
328 #define FPULi (sh4r.fpul)
330 if( SH4_INT_PENDING() )
331 sh4_accept_interrupt();
333 pc = sh4r.pc;
334 if( pc > 0xFFFFFF00 ) {
335 /* SYSCALL Magic */
336 syscall_invoke( pc );
337 sh4r.in_delay_slot = 0;
338 pc = sh4r.pc = sh4r.pr;
339 sh4r.new_pc = sh4r.pc + 2;
340 }
341 ir = MEM_READ_WORD(pc);
342 sh4r.icount++;
344 switch( (ir&0xF000)>>12 ) {
345 case 0: /* 0000nnnnmmmmxxxx */
346 switch( ir&0x000F ) {
347 case 2:
348 switch( (ir&0x00F0)>>4 ) {
349 case 0: /* STC SR, Rn */
350 CHECKPRIV();
351 RN(ir) = sh4_read_sr();
352 break;
353 case 1: /* STC GBR, Rn */
354 RN(ir) = sh4r.gbr;
355 break;
356 case 2: /* STC VBR, Rn */
357 CHECKPRIV();
358 RN(ir) = sh4r.vbr;
359 break;
360 case 3: /* STC SSR, Rn */
361 CHECKPRIV();
362 RN(ir) = sh4r.ssr;
363 break;
364 case 4: /* STC SPC, Rn */
365 CHECKPRIV();
366 RN(ir) = sh4r.spc;
367 break;
368 case 8: case 9: case 10: case 11: case 12: case 13:
369 case 14: case 15:/* STC Rm_bank, Rn */
370 CHECKPRIV();
371 RN(ir) = RN_BANK(ir);
372 break;
373 default: UNDEF(ir);
374 }
375 break;
376 case 3:
377 switch( (ir&0x00F0)>>4 ) {
378 case 0: /* BSRF Rn */
379 CHECKDEST( pc + 4 + RN(ir) );
380 CHECKSLOTILLEGAL();
381 sh4r.in_delay_slot = 1;
382 sh4r.pr = sh4r.pc + 4;
383 sh4r.pc = sh4r.new_pc;
384 sh4r.new_pc = pc + 4 + RN(ir);
385 return TRUE;
386 case 2: /* BRAF Rn */
387 CHECKDEST( pc + 4 + RN(ir) );
388 CHECKSLOTILLEGAL();
389 sh4r.in_delay_slot = 1;
390 sh4r.pc = sh4r.new_pc;
391 sh4r.new_pc = pc + 4 + RN(ir);
392 return TRUE;
393 case 8: /* PREF [Rn] */
394 tmp = RN(ir);
395 if( (tmp & 0xFC000000) == 0xE0000000 ) {
396 /* Store queue operation */
397 int queue = (tmp&0x20)>>2;
398 int32_t *src = &sh4r.store_queue[queue];
399 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
400 uint32_t target = tmp&0x03FFFFE0 | hi;
401 mem_copy_to_sh4( target, src, 32 );
402 //if( (target &0xFF000000) != 0x04000000 )
403 // WARN( "Executed SQ%c => %08X",
404 // (queue == 0 ? '0' : '1'), target );
405 }
406 break;
407 case 9: /* OCBI [Rn] */
408 case 10:/* OCBP [Rn] */
409 case 11:/* OCBWB [Rn] */
410 /* anything? */
411 break;
412 case 12:/* MOVCA.L R0, [Rn] */
413 UNIMP(ir);
414 default: UNDEF(ir);
415 }
416 break;
417 case 4: /* MOV.B Rm, [R0 + Rn] */
418 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
419 break;
420 case 5: /* MOV.W Rm, [R0 + Rn] */
421 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
422 break;
423 case 6: /* MOV.L Rm, [R0 + Rn] */
424 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
425 break;
426 case 7: /* MUL.L Rm, Rn */
427 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
428 (RM(ir) * RN(ir));
429 break;
430 case 8:
431 switch( (ir&0x0FF0)>>4 ) {
432 case 0: /* CLRT */
433 sh4r.t = 0;
434 break;
435 case 1: /* SETT */
436 sh4r.t = 1;
437 break;
438 case 2: /* CLRMAC */
439 sh4r.mac = 0;
440 break;
441 case 3: /* LDTLB */
442 break;
443 case 4: /* CLRS */
444 sh4r.s = 0;
445 break;
446 case 5: /* SETS */
447 sh4r.s = 1;
448 break;
449 default: UNDEF(ir);
450 }
451 break;
452 case 9:
453 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
454 RN(ir) = sh4r.t;
455 else if( ir == 0x0019 ) /* DIV0U */
456 sh4r.m = sh4r.q = sh4r.t = 0;
457 else if( ir == 0x0009 )
458 /* NOP */;
459 else UNDEF(ir);
460 break;
461 case 10:
462 switch( (ir&0x00F0) >> 4 ) {
463 case 0: /* STS MACH, Rn */
464 RN(ir) = sh4r.mac >> 32;
465 break;
466 case 1: /* STS MACL, Rn */
467 RN(ir) = (uint32_t)sh4r.mac;
468 break;
469 case 2: /* STS PR, Rn */
470 RN(ir) = sh4r.pr;
471 break;
472 case 3: /* STC SGR, Rn */
473 CHECKPRIV();
474 RN(ir) = sh4r.sgr;
475 break;
476 case 5:/* STS FPUL, Rn */
477 RN(ir) = sh4r.fpul;
478 break;
479 case 6: /* STS FPSCR, Rn */
480 RN(ir) = sh4r.fpscr;
481 break;
482 case 15:/* STC DBR, Rn */
483 CHECKPRIV();
484 RN(ir) = sh4r.dbr;
485 break;
486 default: UNDEF(ir);
487 }
488 break;
489 case 11:
490 switch( (ir&0x0FF0)>>4 ) {
491 case 0: /* RTS */
492 CHECKDEST( sh4r.pr );
493 CHECKSLOTILLEGAL();
494 sh4r.in_delay_slot = 1;
495 sh4r.pc = sh4r.new_pc;
496 sh4r.new_pc = sh4r.pr;
497 return TRUE;
498 case 1: /* SLEEP */
499 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
500 sh4r.sh4_state = SH4_STATE_STANDBY;
501 } else {
502 sh4r.sh4_state = SH4_STATE_SLEEP;
503 }
504 return FALSE; /* Halt CPU */
505 case 2: /* RTE */
506 CHECKPRIV();
507 CHECKDEST( sh4r.spc );
508 CHECKSLOTILLEGAL();
509 sh4r.in_delay_slot = 1;
510 sh4r.pc = sh4r.new_pc;
511 sh4r.new_pc = sh4r.spc;
512 sh4_load_sr( sh4r.ssr );
513 return TRUE;
514 default:UNDEF(ir);
515 }
516 break;
517 case 12:/* MOV.B [R0+R%d], R%d */
518 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
519 break;
520 case 13:/* MOV.W [R0+R%d], R%d */
521 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
522 break;
523 case 14:/* MOV.L [R0+R%d], R%d */
524 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
525 break;
526 case 15:/* MAC.L [Rm++], [Rn++] */
527 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
528 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
529 if( sh4r.s ) {
530 /* 48-bit Saturation. Yuch */
531 tmpl += SIGNEXT48(sh4r.mac);
532 if( tmpl < 0xFFFF800000000000LL )
533 tmpl = 0xFFFF800000000000LL;
534 else if( tmpl > 0x00007FFFFFFFFFFFLL )
535 tmpl = 0x00007FFFFFFFFFFFLL;
536 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
537 (tmpl&0x0000FFFFFFFFFFFFLL);
538 } else sh4r.mac = tmpl;
540 RM(ir) += 4;
541 RN(ir) += 4;
543 break;
544 default: UNDEF(ir);
545 }
546 break;
547 case 1: /* 0001nnnnmmmmdddd */
548 /* MOV.L Rm, [Rn + disp4*4] */
549 MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
550 break;
551 case 2: /* 0010nnnnmmmmxxxx */
552 switch( ir&0x000F ) {
553 case 0: /* MOV.B Rm, [Rn] */
554 MEM_WRITE_BYTE( RN(ir), RM(ir) );
555 break;
556 case 1: /* MOV.W Rm, [Rn] */
557 MEM_WRITE_WORD( RN(ir), RM(ir) );
558 break;
559 case 2: /* MOV.L Rm, [Rn] */
560 MEM_WRITE_LONG( RN(ir), RM(ir) );
561 break;
562 case 3: UNDEF(ir);
563 break;
564 case 4: /* MOV.B Rm, [--Rn] */
565 RN(ir) --;
566 MEM_WRITE_BYTE( RN(ir), RM(ir) );
567 break;
568 case 5: /* MOV.W Rm, [--Rn] */
569 RN(ir) -= 2;
570 MEM_WRITE_WORD( RN(ir), RM(ir) );
571 break;
572 case 6: /* MOV.L Rm, [--Rn] */
573 RN(ir) -= 4;
574 MEM_WRITE_LONG( RN(ir), RM(ir) );
575 break;
576 case 7: /* DIV0S Rm, Rn */
577 sh4r.q = RN(ir)>>31;
578 sh4r.m = RM(ir)>>31;
579 sh4r.t = sh4r.q ^ sh4r.m;
580 break;
581 case 8: /* TST Rm, Rn */
582 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
583 break;
584 case 9: /* AND Rm, Rn */
585 RN(ir) &= RM(ir);
586 break;
587 case 10:/* XOR Rm, Rn */
588 RN(ir) ^= RM(ir);
589 break;
590 case 11:/* OR Rm, Rn */
591 RN(ir) |= RM(ir);
592 break;
593 case 12:/* CMP/STR Rm, Rn */
594 /* set T = 1 if any byte in RM & RN is the same */
595 tmp = RM(ir) ^ RN(ir);
596 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
597 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
598 break;
599 case 13:/* XTRCT Rm, Rn */
600 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
601 break;
602 case 14:/* MULU.W Rm, Rn */
603 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
604 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
605 break;
606 case 15:/* MULS.W Rm, Rn */
607 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
608 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
609 break;
610 }
611 break;
612 case 3: /* 0011nnnnmmmmxxxx */
613 switch( ir&0x000F ) {
614 case 0: /* CMP/EQ Rm, Rn */
615 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
616 break;
617 case 2: /* CMP/HS Rm, Rn */
618 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
619 break;
620 case 3: /* CMP/GE Rm, Rn */
621 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
622 break;
623 case 4: { /* DIV1 Rm, Rn */
624 /* This is just from the sh4p manual with some
625 * simplifications (someone want to check it's correct? :)
626 * Why they couldn't just provide a real DIV instruction...
627 * Please oh please let the translator batch these things
628 * up into a single DIV... */
629 uint32_t tmp0, tmp1, tmp2, dir;
631 dir = sh4r.q ^ sh4r.m;
632 sh4r.q = (RN(ir) >> 31);
633 tmp2 = RM(ir);
634 RN(ir) = (RN(ir) << 1) | sh4r.t;
635 tmp0 = RN(ir);
636 if( dir ) {
637 RN(ir) += tmp2;
638 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
639 } else {
640 RN(ir) -= tmp2;
641 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
642 }
643 sh4r.q ^= sh4r.m ^ tmp1;
644 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
645 break; }
646 case 5: /* DMULU.L Rm, Rn */
647 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
648 break;
649 case 6: /* CMP/HI Rm, Rn */
650 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
651 break;
652 case 7: /* CMP/GT Rm, Rn */
653 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
654 break;
655 case 8: /* SUB Rm, Rn */
656 RN(ir) -= RM(ir);
657 break;
658 case 10:/* SUBC Rm, Rn */
659 tmp = RN(ir);
660 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
661 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
662 break;
663 case 11:/* SUBV Rm, Rn */
664 UNIMP(ir);
665 break;
666 case 12:/* ADD Rm, Rn */
667 RN(ir) += RM(ir);
668 break;
669 case 13:/* DMULS.L Rm, Rn */
670 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
671 break;
672 case 14:/* ADDC Rm, Rn */
673 tmp = RN(ir);
674 RN(ir) += RM(ir) + sh4r.t;
675 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
676 break;
677 case 15:/* ADDV Rm, Rn */
678 UNIMP(ir);
679 break;
680 default: UNDEF(ir);
681 }
682 break;
683 case 4: /* 0100nnnnxxxxxxxx */
684 switch( ir&0x00FF ) {
685 case 0x00: /* SHLL Rn */
686 sh4r.t = RN(ir) >> 31;
687 RN(ir) <<= 1;
688 break;
689 case 0x01: /* SHLR Rn */
690 sh4r.t = RN(ir) & 0x00000001;
691 RN(ir) >>= 1;
692 break;
693 case 0x02: /* STS.L MACH, [--Rn] */
694 RN(ir) -= 4;
695 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
696 break;
697 case 0x03: /* STC.L SR, [--Rn] */
698 CHECKPRIV();
699 RN(ir) -= 4;
700 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
701 break;
702 case 0x04: /* ROTL Rn */
703 sh4r.t = RN(ir) >> 31;
704 RN(ir) <<= 1;
705 RN(ir) |= sh4r.t;
706 break;
707 case 0x05: /* ROTR Rn */
708 sh4r.t = RN(ir) & 0x00000001;
709 RN(ir) >>= 1;
710 RN(ir) |= (sh4r.t << 31);
711 break;
712 case 0x06: /* LDS.L [Rn++], MACH */
713 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
714 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
715 RN(ir) += 4;
716 break;
717 case 0x07: /* LDC.L [Rn++], SR */
718 CHECKPRIV();
719 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
720 RN(ir) +=4;
721 break;
722 case 0x08: /* SHLL2 Rn */
723 RN(ir) <<= 2;
724 break;
725 case 0x09: /* SHLR2 Rn */
726 RN(ir) >>= 2;
727 break;
728 case 0x0A: /* LDS Rn, MACH */
729 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
730 (((uint64_t)RN(ir))<<32);
731 break;
732 case 0x0B: /* JSR [Rn] */
733 CHECKDEST( RN(ir) );
734 CHECKSLOTILLEGAL();
735 sh4r.in_delay_slot = 1;
736 sh4r.pc = sh4r.new_pc;
737 sh4r.new_pc = RN(ir);
738 sh4r.pr = pc + 4;
739 return TRUE;
740 case 0x0E: /* LDC Rn, SR */
741 CHECKPRIV();
742 sh4_load_sr( RN(ir) );
743 break;
744 case 0x10: /* DT Rn */
745 RN(ir) --;
746 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
747 break;
748 case 0x11: /* CMP/PZ Rn */
749 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
750 break;
751 case 0x12: /* STS.L MACL, [--Rn] */
752 RN(ir) -= 4;
753 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
754 break;
755 case 0x13: /* STC.L GBR, [--Rn] */
756 RN(ir) -= 4;
757 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
758 break;
759 case 0x15: /* CMP/PL Rn */
760 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
761 break;
762 case 0x16: /* LDS.L [Rn++], MACL */
763 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
764 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
765 RN(ir) += 4;
766 break;
767 case 0x17: /* LDC.L [Rn++], GBR */
768 sh4r.gbr = MEM_READ_LONG(RN(ir));
769 RN(ir) +=4;
770 break;
771 case 0x18: /* SHLL8 Rn */
772 RN(ir) <<= 8;
773 break;
774 case 0x19: /* SHLR8 Rn */
775 RN(ir) >>= 8;
776 break;
777 case 0x1A: /* LDS Rn, MACL */
778 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
779 (uint64_t)((uint32_t)(RN(ir)));
780 break;
781 case 0x1B: /* TAS.B [Rn] */
782 tmp = MEM_READ_BYTE( RN(ir) );
783 sh4r.t = ( tmp == 0 ? 1 : 0 );
784 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
785 break;
786 case 0x1E: /* LDC Rn, GBR */
787 sh4r.gbr = RN(ir);
788 break;
789 case 0x20: /* SHAL Rn */
790 sh4r.t = RN(ir) >> 31;
791 RN(ir) <<= 1;
792 break;
793 case 0x21: /* SHAR Rn */
794 sh4r.t = RN(ir) & 0x00000001;
795 RN(ir) = ((int32_t)RN(ir)) >> 1;
796 break;
797 case 0x22: /* STS.L PR, [--Rn] */
798 RN(ir) -= 4;
799 MEM_WRITE_LONG( RN(ir), sh4r.pr );
800 break;
801 case 0x23: /* STC.L VBR, [--Rn] */
802 CHECKPRIV();
803 RN(ir) -= 4;
804 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
805 break;
806 case 0x24: /* ROTCL Rn */
807 tmp = RN(ir) >> 31;
808 RN(ir) <<= 1;
809 RN(ir) |= sh4r.t;
810 sh4r.t = tmp;
811 break;
812 case 0x25: /* ROTCR Rn */
813 tmp = RN(ir) & 0x00000001;
814 RN(ir) >>= 1;
815 RN(ir) |= (sh4r.t << 31 );
816 sh4r.t = tmp;
817 break;
818 case 0x26: /* LDS.L [Rn++], PR */
819 sh4r.pr = MEM_READ_LONG( RN(ir) );
820 RN(ir) += 4;
821 break;
822 case 0x27: /* LDC.L [Rn++], VBR */
823 CHECKPRIV();
824 sh4r.vbr = MEM_READ_LONG(RN(ir));
825 RN(ir) +=4;
826 break;
827 case 0x28: /* SHLL16 Rn */
828 RN(ir) <<= 16;
829 break;
830 case 0x29: /* SHLR16 Rn */
831 RN(ir) >>= 16;
832 break;
833 case 0x2A: /* LDS Rn, PR */
834 sh4r.pr = RN(ir);
835 break;
836 case 0x2B: /* JMP [Rn] */
837 CHECKDEST( RN(ir) );
838 CHECKSLOTILLEGAL();
839 sh4r.in_delay_slot = 1;
840 sh4r.pc = sh4r.new_pc;
841 sh4r.new_pc = RN(ir);
842 return TRUE;
843 case 0x2E: /* LDC Rn, VBR */
844 CHECKPRIV();
845 sh4r.vbr = RN(ir);
846 break;
847 case 0x32: /* STC.L SGR, [--Rn] */
848 CHECKPRIV();
849 RN(ir) -= 4;
850 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
851 break;
852 case 0x33: /* STC.L SSR, [--Rn] */
853 CHECKPRIV();
854 RN(ir) -= 4;
855 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
856 break;
857 case 0x37: /* LDC.L [Rn++], SSR */
858 CHECKPRIV();
859 sh4r.ssr = MEM_READ_LONG(RN(ir));
860 RN(ir) +=4;
861 break;
862 case 0x3E: /* LDC Rn, SSR */
863 CHECKPRIV();
864 sh4r.ssr = RN(ir);
865 break;
866 case 0x43: /* STC.L SPC, [--Rn] */
867 CHECKPRIV();
868 RN(ir) -= 4;
869 MEM_WRITE_LONG( RN(ir), sh4r.spc );
870 break;
871 case 0x47: /* LDC.L [Rn++], SPC */
872 CHECKPRIV();
873 sh4r.spc = MEM_READ_LONG(RN(ir));
874 RN(ir) +=4;
875 break;
876 case 0x4E: /* LDC Rn, SPC */
877 CHECKPRIV();
878 sh4r.spc = RN(ir);
879 break;
880 case 0x52: /* STS.L FPUL, [--Rn] */
881 RN(ir) -= 4;
882 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
883 break;
884 case 0x56: /* LDS.L [Rn++], FPUL */
885 sh4r.fpul = MEM_READ_LONG(RN(ir));
886 RN(ir) +=4;
887 break;
888 case 0x5A: /* LDS Rn, FPUL */
889 sh4r.fpul = RN(ir);
890 break;
891 case 0x62: /* STS.L FPSCR, [--Rn] */
892 RN(ir) -= 4;
893 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
894 break;
895 case 0x66: /* LDS.L [Rn++], FPSCR */
896 sh4r.fpscr = MEM_READ_LONG(RN(ir));
897 RN(ir) +=4;
898 break;
899 case 0x6A: /* LDS Rn, FPSCR */
900 sh4r.fpscr = RN(ir);
901 break;
902 case 0xF2: /* STC.L DBR, [--Rn] */
903 CHECKPRIV();
904 RN(ir) -= 4;
905 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
906 break;
907 case 0xF6: /* LDC.L [Rn++], DBR */
908 CHECKPRIV();
909 sh4r.dbr = MEM_READ_LONG(RN(ir));
910 RN(ir) +=4;
911 break;
912 case 0xFA: /* LDC Rn, DBR */
913 CHECKPRIV();
914 sh4r.dbr = RN(ir);
915 break;
916 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
917 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
918 CHECKPRIV();
919 RN(ir) -= 4;
920 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
921 break;
922 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
923 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
924 CHECKPRIV();
925 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
926 RN(ir) += 4;
927 break;
928 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
929 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
930 CHECKPRIV();
931 RN_BANK(ir) = RM(ir);
932 break;
933 default:
934 if( (ir&0x000F) == 0x0F ) {
935 /* MAC.W [Rm++], [Rn++] */
936 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
937 SIGNEXT16(MEM_READ_WORD(RN(ir)));
938 if( sh4r.s ) {
939 /* FIXME */
940 UNIMP(ir);
941 } else sh4r.mac += SIGNEXT32(tmp);
942 RM(ir) += 2;
943 RN(ir) += 2;
944 } else if( (ir&0x000F) == 0x0C ) {
945 /* SHAD Rm, Rn */
946 tmp = RM(ir);
947 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
948 else if( (tmp & 0x1F) == 0 )
949 RN(ir) = ((int32_t)RN(ir)) >> 31;
950 else
951 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
952 } else if( (ir&0x000F) == 0x0D ) {
953 /* SHLD Rm, Rn */
954 tmp = RM(ir);
955 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
956 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
957 else RN(ir) >>= (((~tmp) & 0x1F)+1);
958 } else UNDEF(ir);
959 }
960 break;
961 case 5: /* 0101nnnnmmmmdddd */
962 /* MOV.L [Rm + disp4*4], Rn */
963 RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
964 break;
965 case 6: /* 0110xxxxxxxxxxxx */
966 switch( ir&0x000f ) {
967 case 0: /* MOV.B [Rm], Rn */
968 RN(ir) = MEM_READ_BYTE( RM(ir) );
969 break;
970 case 1: /* MOV.W [Rm], Rn */
971 RN(ir) = MEM_READ_WORD( RM(ir) );
972 break;
973 case 2: /* MOV.L [Rm], Rn */
974 RN(ir) = MEM_READ_LONG( RM(ir) );
975 break;
976 case 3: /* MOV Rm, Rn */
977 RN(ir) = RM(ir);
978 break;
979 case 4: /* MOV.B [Rm++], Rn */
980 RN(ir) = MEM_READ_BYTE( RM(ir) );
981 RM(ir) ++;
982 break;
983 case 5: /* MOV.W [Rm++], Rn */
984 RN(ir) = MEM_READ_WORD( RM(ir) );
985 RM(ir) += 2;
986 break;
987 case 6: /* MOV.L [Rm++], Rn */
988 RN(ir) = MEM_READ_LONG( RM(ir) );
989 RM(ir) += 4;
990 break;
991 case 7: /* NOT Rm, Rn */
992 RN(ir) = ~RM(ir);
993 break;
994 case 8: /* SWAP.B Rm, Rn */
995 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
996 ((RM(ir)&0x000000FF)<<8);
997 break;
998 case 9: /* SWAP.W Rm, Rn */
999 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
1000 break;
1001 case 10:/* NEGC Rm, Rn */
1002 tmp = 0 - RM(ir);
1003 RN(ir) = tmp - sh4r.t;
1004 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
1005 break;
1006 case 11:/* NEG Rm, Rn */
1007 RN(ir) = 0 - RM(ir);
1008 break;
1009 case 12:/* EXTU.B Rm, Rn */
1010 RN(ir) = RM(ir)&0x000000FF;
1011 break;
1012 case 13:/* EXTU.W Rm, Rn */
1013 RN(ir) = RM(ir)&0x0000FFFF;
1014 break;
1015 case 14:/* EXTS.B Rm, Rn */
1016 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
1017 break;
1018 case 15:/* EXTS.W Rm, Rn */
1019 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
1020 break;
1021 }
1022 break;
1023 case 7: /* 0111nnnniiiiiiii */
1024 /* ADD imm8, Rn */
1025 RN(ir) += IMM8(ir);
1026 break;
1027 case 8: /* 1000xxxxxxxxxxxx */
1028 switch( (ir&0x0F00) >> 8 ) {
1029 case 0: /* MOV.B R0, [Rm + disp4] */
1030 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
1031 break;
1032 case 1: /* MOV.W R0, [Rm + disp4*2] */
1033 MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
1034 break;
1035 case 4: /* MOV.B [Rm + disp4], R0 */
1036 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
1037 break;
1038 case 5: /* MOV.W [Rm + disp4*2], R0 */
1039 R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
1040 break;
1041 case 8: /* CMP/EQ imm, R0 */
1042 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
1043 break;
1044 case 9: /* BT disp8 */
1045 CHECKSLOTILLEGAL()
1046 if( sh4r.t ) {
1047 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1048 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1049 sh4r.new_pc = sh4r.pc + 2;
1050 return TRUE;
1051 }
1052 break;
1053 case 11:/* BF disp8 */
1054 CHECKSLOTILLEGAL()
1055 if( !sh4r.t ) {
1056 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1057 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1058 sh4r.new_pc = sh4r.pc + 2;
1059 return TRUE;
1060 }
1061 break;
1062 case 13:/* BT/S disp8 */
1063 CHECKSLOTILLEGAL()
1064 if( sh4r.t ) {
1065 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1066 sh4r.in_delay_slot = 1;
1067 sh4r.pc = sh4r.new_pc;
1068 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1069 sh4r.in_delay_slot = 1;
1070 return TRUE;
1071 }
1072 break;
1073 case 15:/* BF/S disp8 */
1074 CHECKSLOTILLEGAL()
1075 if( !sh4r.t ) {
1076 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1077 sh4r.in_delay_slot = 1;
1078 sh4r.pc = sh4r.new_pc;
1079 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1080 return TRUE;
1081 }
1082 break;
1083 default: UNDEF(ir);
1084 }
1085 break;
1086 case 9: /* 1001xxxxxxxxxxxx */
1087 /* MOV.W [disp8*2 + pc + 4], Rn */
1088 RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
1089 break;
1090 case 10:/* 1010dddddddddddd */
1091 /* BRA disp12 */
1092 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1093 CHECKSLOTILLEGAL()
1094 sh4r.in_delay_slot = 1;
1095 sh4r.pc = sh4r.new_pc;
1096 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1097 return TRUE;
1098 case 11:/* 1011dddddddddddd */
1099 /* BSR disp12 */
1100 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1101 CHECKSLOTILLEGAL()
1102 sh4r.in_delay_slot = 1;
1103 sh4r.pr = pc + 4;
1104 sh4r.pc = sh4r.new_pc;
1105 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1106 return TRUE;
1107 case 12:/* 1100xxxxdddddddd */
1108 switch( (ir&0x0F00)>>8 ) {
1109 case 0: /* MOV.B R0, [GBR + disp8] */
1110 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1111 break;
1112 case 1: /* MOV.W R0, [GBR + disp8*2] */
1113 MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
1114 break;
1115 case 2: /*MOV.L R0, [GBR + disp8*4] */
1116 MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
1117 break;
1118 case 3: /* TRAPA imm8 */
1119 CHECKSLOTILLEGAL()
1120 sh4r.in_delay_slot = 1;
1121 MMIO_WRITE( MMU, TRA, UIMM8(ir) );
1122 sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */
1123 sh4r.new_pc += 2;
1124 RAISE( EXC_TRAP, EXV_TRAP );
1125 break;
1126 case 4: /* MOV.B [GBR + disp8], R0 */
1127 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1128 break;
1129 case 5: /* MOV.W [GBR + disp8*2], R0 */
1130 R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
1131 break;
1132 case 6: /* MOV.L [GBR + disp8*4], R0 */
1133 R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
1134 break;
1135 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1136 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1137 break;
1138 case 8: /* TST imm8, R0 */
1139 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1140 break;
1141 case 9: /* AND imm8, R0 */
1142 R0 &= UIMM8(ir);
1143 break;
1144 case 10:/* XOR imm8, R0 */
1145 R0 ^= UIMM8(ir);
1146 break;
1147 case 11:/* OR imm8, R0 */
1148 R0 |= UIMM8(ir);
1149 break;
1150 case 12:/* TST.B imm8, [R0+GBR] */
1151 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1152 break;
1153 case 13:/* AND.B imm8, [R0+GBR] */
1154 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1155 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1156 break;
1157 case 14:/* XOR.B imm8, [R0+GBR] */
1158 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1159 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1160 break;
1161 case 15:/* OR.B imm8, [R0+GBR] */
1162 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1163 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1164 break;
1165 }
1166 break;
1167 case 13:/* 1101nnnndddddddd */
1168 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1169 RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
1170 break;
1171 case 14:/* 1110nnnniiiiiiii */
1172 /* MOV imm8, Rn */
1173 RN(ir) = IMM8(ir);
1174 break;
1175 case 15:/* 1111xxxxxxxxxxxx */
1176 CHECKFPUEN();
1177 if( IS_FPU_DOUBLEPREC() ) {
1178 switch( ir&0x000F ) {
1179 case 0: /* FADD FRm, FRn */
1180 DRN(ir) += DRM(ir);
1181 break;
1182 case 1: /* FSUB FRm, FRn */
1183 DRN(ir) -= DRM(ir);
1184 break;
1185 case 2: /* FMUL FRm, FRn */
1186 DRN(ir) = DRN(ir) * DRM(ir);
1187 break;
1188 case 3: /* FDIV FRm, FRn */
1189 DRN(ir) = DRN(ir) / DRM(ir);
1190 break;
1191 case 4: /* FCMP/EQ FRm, FRn */
1192 sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
1193 break;
1194 case 5: /* FCMP/GT FRm, FRn */
1195 sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
1196 break;
1197 case 6: /* FMOV.S [Rm+R0], FRn */
1198 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1199 break;
1200 case 7: /* FMOV.S FRm, [Rn+R0] */
1201 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1202 break;
1203 case 8: /* FMOV.S [Rm], FRn */
1204 MEM_FP_READ( RM(ir), FRNn(ir) );
1205 break;
1206 case 9: /* FMOV.S [Rm++], FRn */
1207 MEM_FP_READ( RM(ir), FRNn(ir) );
1208 RM(ir) += FP_WIDTH;
1209 break;
1210 case 10:/* FMOV.S FRm, [Rn] */
1211 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1212 break;
1213 case 11:/* FMOV.S FRm, [--Rn] */
1214 RN(ir) -= FP_WIDTH;
1215 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1216 break;
1217 case 12:/* FMOV FRm, FRn */
1218 if( IS_FPU_DOUBLESIZE() )
1219 DRN(ir) = DRM(ir);
1220 else
1221 FRN(ir) = FRM(ir);
1222 break;
1223 case 13:
1224 switch( (ir&0x00F0) >> 4 ) {
1225 case 0: /* FSTS FPUL, FRn */
1226 FRN(ir) = FPULf;
1227 break;
1228 case 1: /* FLDS FRn,FPUL */
1229 FPULf = FRN(ir);
1230 break;
1231 case 2: /* FLOAT FPUL, FRn */
1232 DRN(ir) = (float)FPULi;
1233 break;
1234 case 3: /* FTRC FRn, FPUL */
1235 FPULi = (uint32_t)DRN(ir);
1236 /* FIXME: is this sufficient? */
1237 break;
1238 case 4: /* FNEG FRn */
1239 DRN(ir) = -DRN(ir);
1240 break;
1241 case 5: /* FABS FRn */
1242 DRN(ir) = fabs(DRN(ir));
1243 break;
1244 case 6: /* FSQRT FRn */
1245 DRN(ir) = sqrt(DRN(ir));
1246 break;
1247 case 7: /* FSRRA FRn */
1248 DRN(ir) = 1.0/sqrt(DRN(ir));
1249 break;
1250 case 8: /* FLDI0 FRn */
1251 DRN(ir) = 0.0;
1252 break;
1253 case 9: /* FLDI1 FRn */
1254 DRN(ir) = 1.0;
1255 break;
1256 case 10: /* FCNVSD FPUL, DRn */
1257 DRN(ir) = (double)FPULf;
1258 break;
1259 case 11: /* FCNVDS DRn, FPUL */
1260 FPULf = (float)DRN(ir);
1261 break;
1262 case 14:/* FIPR FVm, FVn */
1263 UNDEF(ir);
1264 break;
1265 case 15:
1266 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1267 break;
1268 }
1269 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1270 float angle = (((float)(short)(FPULi>>16)) +
1271 ((float)(FPULi&16)/65536.0)) *
1272 2 * M_PI;
1273 int reg = DRNn(ir);
1274 DR(reg) = sinf(angle);
1275 DR(reg+1) = cosf(angle);
1276 break;
1277 }
1278 else if( ir == 0xFBFD ) {
1279 /* FRCHG */
1280 sh4r.fpscr ^= FPSCR_FR;
1281 break;
1282 }
1283 else if( ir == 0xF3FD ) {
1284 /* FSCHG */
1285 sh4r.fpscr ^= FPSCR_SZ;
1286 break;
1287 }
1288 default: UNDEF(ir);
1289 }
1290 break;
1291 case 14:/* FMAC FR0, FRm, FRn */
1292 DRN(ir) += DRM(ir)*DR0;
1293 break;
1294 default: UNDEF(ir);
1295 }
1296 } else {
1297 switch( ir&0x000F ) {
1298 case 0: /* FADD FRm, FRn */
1299 FRN(ir) += FRM(ir);
1300 break;
1301 case 1: /* FSUB FRm, FRn */
1302 FRN(ir) -= FRM(ir);
1303 break;
1304 case 2: /* FMUL FRm, FRn */
1305 FRN(ir) = FRN(ir) * FRM(ir);
1306 break;
1307 case 3: /* FDIV FRm, FRn */
1308 FRN(ir) = FRN(ir) / FRM(ir);
1309 break;
1310 case 4: /* FCMP/EQ FRm, FRn */
1311 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1312 break;
1313 case 5: /* FCMP/GT FRm, FRn */
1314 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1315 break;
1316 case 6: /* FMOV.S [Rm+R0], FRn */
1317 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1318 break;
1319 case 7: /* FMOV.S FRm, [Rn+R0] */
1320 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1321 break;
1322 case 8: /* FMOV.S [Rm], FRn */
1323 MEM_FP_READ( RM(ir), FRNn(ir) );
1324 break;
1325 case 9: /* FMOV.S [Rm++], FRn */
1326 MEM_FP_READ( RM(ir), FRNn(ir) );
1327 RM(ir) += FP_WIDTH;
1328 break;
1329 case 10:/* FMOV.S FRm, [Rn] */
1330 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1331 break;
1332 case 11:/* FMOV.S FRm, [--Rn] */
1333 RN(ir) -= FP_WIDTH;
1334 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1335 break;
1336 case 12:/* FMOV FRm, FRn */
1337 if( IS_FPU_DOUBLESIZE() )
1338 DRN(ir) = DRM(ir);
1339 else
1340 FRN(ir) = FRM(ir);
1341 break;
1342 case 13:
1343 switch( (ir&0x00F0) >> 4 ) {
1344 case 0: /* FSTS FPUL, FRn */
1345 FRN(ir) = FPULf;
1346 break;
1347 case 1: /* FLDS FRn,FPUL */
1348 FPULf = FRN(ir);
1349 break;
1350 case 2: /* FLOAT FPUL, FRn */
1351 FRN(ir) = (float)FPULi;
1352 break;
1353 case 3: /* FTRC FRn, FPUL */
1354 FPULi = (uint32_t)FRN(ir);
1355 /* FIXME: is this sufficient? */
1356 break;
1357 case 4: /* FNEG FRn */
1358 FRN(ir) = -FRN(ir);
1359 break;
1360 case 5: /* FABS FRn */
1361 FRN(ir) = fabsf(FRN(ir));
1362 break;
1363 case 6: /* FSQRT FRn */
1364 FRN(ir) = sqrtf(FRN(ir));
1365 break;
1366 case 7: /* FSRRA FRn */
1367 FRN(ir) = 1.0/sqrtf(FRN(ir));
1368 break;
1369 case 8: /* FLDI0 FRn */
1370 FRN(ir) = 0.0;
1371 break;
1372 case 9: /* FLDI1 FRn */
1373 FRN(ir) = 1.0;
1374 break;
1375 case 10: /* FCNVSD FPUL, DRn */
1376 UNDEF(ir);
1377 break;
1378 case 11: /* FCNVDS DRn, FPUL */
1379 UNDEF(ir);
1380 break;
1381 case 14:/* FIPR FVm, FVn */
1382 /* FIXME: This is not going to be entirely accurate
1383 * as the SH4 instruction is less precise. Also
1384 * need to check for 0s and infinities.
1385 */
1386 {
1387 int tmp2 = FVN(ir);
1388 tmp = FVM(ir);
1389 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1390 FR(tmp+1)*FR(tmp2+1) +
1391 FR(tmp+2)*FR(tmp2+2) +
1392 FR(tmp+3)*FR(tmp2+3);
1393 break;
1394 }
1395 case 15:
1396 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1397 tmp = FVN(ir);
1398 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1399 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1400 XF(8)*fv[2] + XF(12)*fv[3];
1401 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1402 XF(9)*fv[2] + XF(13)*fv[3];
1403 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1404 XF(10)*fv[2] + XF(14)*fv[3];
1405 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1406 XF(11)*fv[2] + XF(15)*fv[3];
1407 break;
1408 }
1409 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1410 float angle = (((float)(short)(FPULi>>16)) +
1411 ((float)(FPULi&16)/65536.0)) *
1412 2 * M_PI;
1413 int reg = FRNn(ir);
1414 FR(reg) = sinf(angle);
1415 FR(reg+1) = cosf(angle);
1416 break;
1417 }
1418 else if( ir == 0xFBFD ) {
1419 /* FRCHG */
1420 sh4r.fpscr ^= FPSCR_FR;
1421 break;
1422 }
1423 else if( ir == 0xF3FD ) {
1424 /* FSCHG */
1425 sh4r.fpscr ^= FPSCR_SZ;
1426 break;
1427 }
1428 default: UNDEF(ir);
1429 }
1430 break;
1431 case 14:/* FMAC FR0, FRm, FRn */
1432 FRN(ir) += FRM(ir)*FR0;
1433 break;
1434 default: UNDEF(ir);
1435 }
1436 }
1437 break;
1438 }
1439 sh4r.pc = sh4r.new_pc;
1440 sh4r.new_pc += 2;
1441 sh4r.in_delay_slot = 0;
1442 }
.