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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 302:96b5cc24309c
prev279:7bb759c23271
next305:1191085c5988
author nkeynes
date Wed Jan 17 21:27:20 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Rename SPUDMA to G2DMA (following KOS's lead)
Remove sh4r.icount (obsolete)
Rewrite G2 fifo status in terms of slice cycles
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     1 /**
     2  * $Id: asic.c,v 1.24 2007-01-17 21:27:20 nkeynes Exp $
     3  *
     4  * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
     5  * and DMA). 
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE asic_module
    22 #include <assert.h>
    23 #include <stdlib.h>
    24 #include "dream.h"
    25 #include "mem.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/dmac.h"
    28 #include "dreamcast.h"
    29 #include "maple/maple.h"
    30 #include "gdrom/ide.h"
    31 #include "asic.h"
    32 #define MMIO_IMPL
    33 #include "asic.h"
    34 /*
    35  * Open questions:
    36  *   1) Does changing the mask after event occurance result in the
    37  *      interrupt being delivered immediately?
    38  * TODO: Logic diagram of ASIC event/interrupt logic.
    39  *
    40  * ... don't even get me started on the "EXTDMA" page, about which, apparently,
    41  * practically nothing is publicly known...
    42  */
    44 static void asic_check_cleared_events( void );
    45 static void asic_init( void );
    46 static void asic_reset( void );
    47 static uint32_t asic_run_slice( uint32_t nanosecs );
    48 static void asic_save_state( FILE *f );
    49 static int asic_load_state( FILE *f );
    50 static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
    52 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
    53 					NULL, asic_save_state, asic_load_state };
    55 #define G2_BIT5_TICKS 60
    56 #define G2_BIT4_TICKS 160
    57 #define G2_BIT0_ON_TICKS 120
    58 #define G2_BIT0_OFF_TICKS 420
    60 struct asic_g2_state {
    61     int bit5_off_timer;
    62     int bit4_on_timer;
    63     int bit4_off_timer;
    64     int bit0_on_timer;
    65     int bit0_off_timer;
    66 };
    68 static struct asic_g2_state g2_state;
    70 static uint32_t asic_run_slice( uint32_t nanosecs )
    71 {
    72     g2_update_fifo_status(nanosecs);
    73     if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
    74 	g2_state.bit5_off_timer = -1;
    75     } else {
    76 	g2_state.bit5_off_timer -= nanosecs;
    77     }
    79     if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
    80 	g2_state.bit4_off_timer = -1;
    81     } else {
    82 	g2_state.bit4_off_timer -= nanosecs;
    83     }
    84     if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
    85 	g2_state.bit4_on_timer = -1;
    86     } else {
    87 	g2_state.bit4_on_timer -= nanosecs;
    88     }
    90     if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
    91 	g2_state.bit0_off_timer = -1;
    92     } else {
    93 	g2_state.bit0_off_timer -= nanosecs;
    94     }
    95     if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
    96 	g2_state.bit0_on_timer = -1;
    97     } else {
    98 	g2_state.bit0_on_timer -= nanosecs;
    99     }
   101     return nanosecs;
   102 }
   104 static void asic_init( void )
   105 {
   106     register_io_region( &mmio_region_ASIC );
   107     register_io_region( &mmio_region_EXTDMA );
   108     asic_reset();
   109 }
   111 static void asic_reset( void )
   112 {
   113     memset( &g2_state, 0xFF, sizeof(g2_state) );
   114 }    
   116 static void asic_save_state( FILE *f )
   117 {
   118     fwrite( &g2_state, sizeof(g2_state), 1, f );
   119 }
   121 static int asic_load_state( FILE *f )
   122 {
   123     if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
   124 	return 1;
   125     else
   126 	return 0;
   127 }
   130 /**
   131  * Setup the timers for the 3 FIFO status bits following a write through the G2
   132  * bus from the SH4 side. The timing is roughly as follows: (times are
   133  * approximate based on software readings - I wouldn't take this as gospel but
   134  * it seems to be enough to fool most programs). 
   135  *    0ns: Bit 5 (Input fifo?) goes high immediately on the write
   136  *   40ns: Bit 5 goes low and bit 4 goes high
   137  *  120ns: Bit 4 goes low, bit 0 goes high
   138  *  240ns: Bit 0 goes low.
   139  *
   140  * Additional writes while the FIFO is in operation extend the time that the
   141  * bits remain high as one might expect, without altering the time at which
   142  * they initially go high.
   143  */
   144 void asic_g2_write_word()
   145 {
   146     if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
   147 	g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
   148     } else {
   149 	g2_state.bit5_off_timer += G2_BIT5_TICKS;
   150     }
   152     if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
   153 	g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
   154     }
   156     if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
   157 	g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
   158     } else {
   159 	g2_state.bit4_off_timer += G2_BIT4_TICKS;
   160     }
   162     if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
   163 	g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
   164     }
   166     if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
   167 	g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
   168     } else {
   169 	g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
   170     }
   172     MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
   173 }
   175 static uint32_t g2_update_fifo_status( uint32_t nanos )
   176 {
   177     uint32_t val = MMIO_READ( ASIC, G2STATUS );
   178     if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
   179 	val = val & (~0x20);
   180 	g2_state.bit5_off_timer = -1;
   181     }
   182     if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
   183 	val = val | 0x10;
   184 	g2_state.bit4_on_timer = -1;
   185     }
   186     if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
   187 	val = val & (~0x10);
   188 	g2_state.bit4_off_timer = -1;
   189     } 
   191     if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
   192 	val = val | 0x01;
   193 	g2_state.bit0_on_timer = -1;
   194     }
   195     if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
   196 	val = val & (~0x01);
   197 	g2_state.bit0_off_timer = -1;
   198     } 
   200     MMIO_WRITE( ASIC, G2STATUS, val );
   201     return val;
   202 }   
   204 static int g2_read_status() {
   205     return g2_update_fifo_status( sh4r.slice_cycle );
   206 }
   209 void asic_event( int event )
   210 {
   211     int offset = ((event&0x60)>>3);
   212     int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
   214     if( result & MMIO_READ(ASIC, IRQA0 + offset) )
   215         intc_raise_interrupt( INT_IRQ13 );
   216     if( result & MMIO_READ(ASIC, IRQB0 + offset) )
   217         intc_raise_interrupt( INT_IRQ11 );
   218     if( result & MMIO_READ(ASIC, IRQC0 + offset) )
   219         intc_raise_interrupt( INT_IRQ9 );
   220 }
   222 void asic_clear_event( int event ) {
   223     int offset = ((event&0x60)>>3);
   224     uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
   225     MMIO_WRITE( ASIC, PIRQ0 + offset, result );
   227     asic_check_cleared_events();
   228 }
   230 void asic_check_cleared_events( )
   231 {
   232     int i, setA = 0, setB = 0, setC = 0;
   233     uint32_t bits;
   234     for( i=0; i<3; i++ ) {
   235 	bits = MMIO_READ( ASIC, PIRQ0 + i );
   236 	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
   237 	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
   238 	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
   239     }
   240     if( setA == 0 )
   241 	intc_clear_interrupt( INT_IRQ13 );
   242     if( setB == 0 )
   243 	intc_clear_interrupt( INT_IRQ11 );
   244     if( setC == 0 )
   245 	intc_clear_interrupt( INT_IRQ9 );
   246 }
   248 void g2_dma_transfer( int channel )
   249 {
   250     uint32_t offset = channel << 5;
   252     if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
   253 	if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
   254 	    uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
   255 	    uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
   256 	    uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
   257 	    uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
   258 	    uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
   259 	    char buf[length];
   260 	    if( dir == 0 ) { /* SH4 to device */
   261 		mem_copy_from_sh4( buf, sh4addr, length );
   262 		mem_copy_to_sh4( extaddr, buf, length );
   263 	    } else { /* Device to SH4 */
   264 		mem_copy_from_sh4( buf, extaddr, length );
   265 		mem_copy_to_sh4( sh4addr, buf, length );
   266 	    }
   267 	    MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
   268 	    asic_event( EVENT_G2_DMA0 + channel );
   269 	} else {
   270 	    MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
   271 	}
   272     }
   273 }
   275 void asic_ide_dma_transfer( )
   276 {	
   277     if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
   278 	if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
   279 	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
   281 	    uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
   282 	    uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
   283 	    int dir = MMIO_READ( EXTDMA, IDEDMADIR );
   285 	    uint32_t xfer = ide_read_data_dma( addr, length );
   286 	    MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
   287 	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
   288 	} else { /* 0 */
   289 	    MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
   290 	}
   291     }
   293 }
   296 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
   297 {
   298     switch( reg ) {
   299     case PIRQ1:
   300 	val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
   301 	/* fallthrough */
   302     case PIRQ0:
   303     case PIRQ2:
   304 	/* Clear any interrupts */
   305 	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
   306 	asic_check_cleared_events();
   307 	break;
   308     case SYSRESET:
   309 	if( val == 0x7611 ) {
   310 	    dreamcast_reset();
   311 	    sh4r.new_pc = sh4r.pc;
   312 	} else {
   313 	    WARN( "Unknown value %08X written to SYSRESET port", val );
   314 	}
   315 	break;
   316     case MAPLE_STATE:
   317 	MMIO_WRITE( ASIC, reg, val );
   318 	if( val & 1 ) {
   319 	    uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
   320 	    maple_handle_buffer( maple_addr );
   321 	    MMIO_WRITE( ASIC, reg, 0 );
   322 	}
   323 	break;
   324     case PVRDMACTL: /* Initiate PVR DMA transfer */
   325 	MMIO_WRITE( ASIC, reg, val );
   326 	if( val & 1 ) {
   327 	    uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
   328 	    uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
   329 	    char *data = alloca( count );
   330 	    uint32_t rcount = DMAC_get_buffer( 2, data, count );
   331 	    if( rcount != count )
   332 		WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
   333 	    mem_copy_to_sh4( dest_addr, data, rcount );
   334 	    asic_event( EVENT_PVR_DMA );
   335 	    MMIO_WRITE( ASIC, PVRDMACTL, 0 );
   336 	    MMIO_WRITE( ASIC, PVRDMACNT, 0 );
   337 	}
   338 	break;
   339     case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:
   340 	MMIO_WRITE( ASIC, reg, val );
   341 	break;
   342     default:
   343 	MMIO_WRITE( ASIC, reg, val );
   344     }
   345 }
   347 int32_t mmio_region_ASIC_read( uint32_t reg )
   348 {
   349     int32_t val;
   350     switch( reg ) {
   351         /*
   352         case 0x89C:
   353             sh4_stop();
   354             return 0x000000B;
   355         */     
   356     case PIRQ0:
   357     case PIRQ1:
   358     case PIRQ2:
   359     case IRQA0:
   360     case IRQA1:
   361     case IRQA2:
   362     case IRQB0:
   363     case IRQB1:
   364     case IRQB2:
   365     case IRQC0:
   366     case IRQC1:
   367     case IRQC2:
   368     case MAPLE_STATE:
   369 	val = MMIO_READ(ASIC, reg);
   370 	return val;            
   371     case G2STATUS:
   372 	return g2_read_status();
   373     default:
   374 	val = MMIO_READ(ASIC, reg);
   375 	return val;
   376     }
   378 }
   380 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
   381 {
   382     if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
   383 	return; /* disabled */
   384     }
   386     switch( reg ) {
   387     case IDEALTSTATUS: /* Device control */
   388 	ide_write_control( val );
   389 	break;
   390     case IDEDATA:
   391 	ide_write_data_pio( val );
   392 	break;
   393     case IDEFEAT:
   394 	if( ide_can_write_regs() )
   395 	    idereg.feature = (uint8_t)val;
   396 	break;
   397     case IDECOUNT:
   398 	if( ide_can_write_regs() )
   399 	    idereg.count = (uint8_t)val;
   400 	break;
   401     case IDELBA0:
   402 	if( ide_can_write_regs() )
   403 	    idereg.lba0 = (uint8_t)val;
   404 	break;
   405     case IDELBA1:
   406 	if( ide_can_write_regs() )
   407 	    idereg.lba1 = (uint8_t)val;
   408 	break;
   409     case IDELBA2:
   410 	if( ide_can_write_regs() )
   411 	    idereg.lba2 = (uint8_t)val;
   412 	break;
   413     case IDEDEV:
   414 	if( ide_can_write_regs() )
   415 	    idereg.device = (uint8_t)val;
   416 	break;
   417     case IDECMD:
   418 	if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
   419 	    ide_write_command( (uint8_t)val );
   420 	}
   421 	break;
   422     case IDEDMACTL1:
   423     case IDEDMACTL2:
   424 	MMIO_WRITE( EXTDMA, reg, val );
   425 	asic_ide_dma_transfer( );
   426 	break;
   427     case IDEACTIVATE:
   428 	if( val == 0x001FFFFF ) {
   429 	    idereg.interface_enabled = TRUE;
   430 	    /* Conventional wisdom says that this is necessary but not
   431 	     * sufficient to enable the IDE interface.
   432 	     */
   433 	} else if( val == 0x000042FE ) {
   434 	    idereg.interface_enabled = FALSE;
   435 	}
   436 	break;
   437     case G2DMA0CTL1:
   438     case G2DMA0CTL2:
   439 	MMIO_WRITE( EXTDMA, reg, val );
   440 	g2_dma_transfer( 0 );
   441 	break;
   442     case G2DMA0STOP:
   443 	break;
   444     case G2DMA1CTL1:
   445     case G2DMA1CTL2:
   446 	MMIO_WRITE( EXTDMA, reg, val );
   447 	g2_dma_transfer( 1 );
   448 	break;
   450     case G2DMA1STOP:
   451 	break;
   452     case G2DMA2CTL1:
   453     case G2DMA2CTL2:
   454 	MMIO_WRITE( EXTDMA, reg, val );
   455 	g2_dma_transfer( 2 );
   456 	break;
   457     case G2DMA2STOP:
   458 	break;
   459     case G2DMA3CTL1:
   460     case G2DMA3CTL2:
   461 	MMIO_WRITE( EXTDMA, reg, val );
   462 	g2_dma_transfer( 3 );
   463 	break;
   464     case G2DMA3STOP:
   465 	break;
   466     case PVRDMA2CTL1:
   467     case PVRDMA2CTL2:
   468 	if( val != 0 ) {
   469 	    ERROR( "Write to unimplemented DMA control register %08X", reg );
   470 	    //dreamcast_stop();
   471 	    //sh4_stop();
   472 	}
   473 	break;
   474     default:
   475             MMIO_WRITE( EXTDMA, reg, val );
   476     }
   477 }
   479 MMIO_REGION_READ_FN( EXTDMA, reg )
   480 {
   481     uint32_t val;
   482     if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
   483 	return 0xFFFFFFFF; /* disabled */
   484     }
   486     switch( reg ) {
   487     case IDEALTSTATUS: 
   488 	val = idereg.status;
   489 	return val;
   490     case IDEDATA: return ide_read_data_pio( );
   491     case IDEFEAT: return idereg.error;
   492     case IDECOUNT:return idereg.count;
   493     case IDELBA0: return idereg.disc;
   494     case IDELBA1: return idereg.lba1;
   495     case IDELBA2: return idereg.lba2;
   496     case IDEDEV: return idereg.device;
   497     case IDECMD:
   498 	val = ide_read_status();
   499 	return val;
   500     default:
   501 	val = MMIO_READ( EXTDMA, reg );
   502 	return val;
   503     }
   504 }
.