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lxdream.org :: lxdream/src/sh4/sh4core.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.h
changeset 302:96b5cc24309c
prev265:5daf59b7f31b
next312:2c34bdc36cbd
author nkeynes
date Wed Jan 17 21:27:20 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Rename SPUDMA to G2DMA (following KOS's lead)
Remove sh4r.icount (obsolete)
Rewrite G2 fifo status in terms of slice cycles
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     1 /**
     2  * $Id: sh4core.h,v 1.17 2007-01-17 21:27:20 nkeynes Exp $
     3  * 
     4  * This file defines the internal functions exported/used by the SH4 core, 
     5  * except for disassembly functions defined in sh4dasm.h
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #ifndef sh4core_H
    21 #define sh4core_H 1
    23 #include <glib/gtypes.h>
    24 #include <stdint.h>
    25 #include <stdio.h>
    27 #ifdef __cplusplus
    28 extern "C" {
    29 #if 0
    30 }
    31 #endif
    32 #endif
    35 /**
    36  * SH4 is running normally 
    37  */
    38 #define SH4_STATE_RUNNING 1
    39 /**
    40  * SH4 is not executing instructions but all peripheral modules are still
    41  * running
    42  */
    43 #define SH4_STATE_SLEEP 2
    44 /**
    45  * SH4 is not executing instructions, DMAC is halted, but all other peripheral
    46  * modules are still running
    47  */
    48 #define SH4_STATE_DEEP_SLEEP 3
    49 /**
    50  * SH4 is not executing instructions and all peripheral modules are also
    51  * stopped. As close as you can get to powered-off without actually being
    52  * off.
    53  */
    54 #define SH4_STATE_STANDBY 4
    56 #define PENDING_IRQ 1
    57 #define PENDING_EVENT 2
    59 struct sh4_registers {
    60     uint32_t r[16];
    61     uint32_t r_bank[8]; /* hidden banked registers */
    62     uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
    63     uint32_t pr, pc, fpscr;
    64     int32_t fpul;
    65     uint64_t mac;
    66     uint32_t m, q, s, t; /* really boolean - 0 or 1 */
    67     float fr[2][16];
    69     int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
    71     uint32_t new_pc; /* Not a real register, but used to handle delay slots */
    72     uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
    73                              when no events are pending */
    74     uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
    75     int in_delay_slot; /* flag to indicate the current instruction is in
    76                              * a delay slot (certain rules apply) */
    77     uint32_t slice_cycle; /* Current nanosecond within the timeslice */
    78     int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
    79 };
    81 extern struct sh4_registers sh4r;
    83 /* Public functions */
    85 void sh4_init( void );
    86 void sh4_reset( void );
    87 void sh4_run( void );
    88 void sh4_runto( uint32_t pc, uint32_t count );
    89 void sh4_runfor( uint32_t count );
    90 int sh4_isrunning( void );
    91 void sh4_stop( void );
    92 void sh4_set_pc( int );
    93 gboolean sh4_execute_instruction( void );
    94 gboolean sh4_raise_exception( int );
    95 gboolean sh4_raise_slot_exception( int, int );
    96 gboolean sh4_raise_tlb_exception( int );
    97 void sh4_set_breakpoint( uint32_t pc, int type );
    98 gboolean sh4_clear_breakpoint( uint32_t pc, int type );
    99 int sh4_get_breakpoint( uint32_t pc );
   101 #define BREAK_ONESHOT 1
   102 #define BREAK_PERM 2
   104 /* SH4 Memory */
   105 int32_t sh4_read_long( uint32_t addr );
   106 int32_t sh4_read_word( uint32_t addr );
   107 int32_t sh4_read_byte( uint32_t addr );
   108 void sh4_write_long( uint32_t addr, uint32_t val );
   109 void sh4_write_word( uint32_t addr, uint32_t val );
   110 void sh4_write_byte( uint32_t addr, uint32_t val );
   111 int32_t sh4_read_phys_word( uint32_t addr );
   113 /* Peripheral functions */
   114 void CPG_reset( void );
   115 void TMU_run_slice( uint32_t );
   116 void TMU_update_clocks( void );
   117 void TMU_reset( void );
   118 void TMU_save_state( FILE * );
   119 int TMU_load_state( FILE * );
   120 void DMAC_reset( void );
   121 void DMAC_run_slice( uint32_t );
   122 void DMAC_save_state( FILE * );
   123 int DMAC_load_state( FILE * );
   124 void SCIF_reset( void );
   125 void SCIF_run_slice( uint32_t );
   126 void SCIF_save_state( FILE *f );
   127 int SCIF_load_state( FILE *f );
   128 void INTC_reset( void );
   129 void INTC_save_state( FILE *f );
   130 int INTC_load_state( FILE *f );
   132 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
   133 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
   134 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
   135 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
   136 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
   137 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
   139 /* Status Register (SR) bits */
   140 #define SR_MD    0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ 
   141 #define SR_RB    0x20000000 /* Register bank (priviledged mode only) */
   142 #define SR_BL    0x10000000 /* Exception/interupt block (1 = masked) */
   143 #define SR_FD    0x00008000 /* FPU disable */
   144 #define SR_M     0x00000200
   145 #define SR_Q     0x00000100
   146 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
   147 #define SR_S     0x00000002 /* Saturation operation for MAC instructions */
   148 #define SR_T     0x00000001 /* True/false or carry/borrow */
   149 #define SR_MASK  0x700083F3
   150 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
   152 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
   153 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
   154 #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
   156 #define FPSCR_FR     0x00200000 /* FPU register bank */
   157 #define FPSCR_SZ     0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
   158 #define FPSCR_PR     0x00080000 /* Precision (0=32 bites, 1=64 bits) */
   159 #define FPSCR_DN     0x00040000 /* Denormalization mode (1 = treat as 0) */
   160 #define FPSCR_CAUSE  0x0003F000
   161 #define FPSCR_ENABLE 0x00000F80
   162 #define FPSCR_FLAG   0x0000007C
   163 #define FPSCR_RM     0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
   165 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
   166 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
   167 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
   169 #define FR(x) sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][(x)^1]
   170 #define DR(x) ((double *)(sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]))[x]
   171 #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
   172 #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
   173 #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
   174 /* Exceptions (for use with sh4_raise_exception) */
   176 #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
   177 #define EX_SLOT_ILLEGAL        0x1A0, 0x100
   178 #define EX_TLB_MISS_READ       0x040, 0x400
   179 #define EX_TLB_MISS_WRITE      0x060, 0x400
   180 #define EX_INIT_PAGE_WRITE     0x080, 0x100
   181 #define EX_TLB_PROT_READ       0x0A0, 0x100
   182 #define EX_TLB_PROT_WRITE      0x0C0, 0x100
   183 #define EX_DATA_ADDR_READ      0x0E0, 0x100
   184 #define EX_DATA_ADDR_WRITE     0x100, 0x100
   185 #define EX_FPU_EXCEPTION       0x120, 0x100
   186 #define EX_TRAPA               0x160, 0x100
   187 #define EX_BREAKPOINT          0x1E0, 0x100
   188 #define EX_FPU_DISABLED        0x800, 0x100
   189 #define EX_SLOT_FPU_DISABLED   0x820, 0x100
   191 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
   193 #ifdef __cplusplus
   194 }
   195 #endif
   196 #endif
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