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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 246:98054d036a24
prev235:880bff11df92
next260:c82e26ec0cac
author nkeynes
date Tue Dec 19 09:54:03 2006 +0000 (13 years ago)
permissions -rw-r--r--
last change Add slot-illegal instruction checking
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     1 /**
     2  * $Id: sh4core.c,v 1.35 2006-12-19 09:54:03 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 /* CPU-generated exception code/vector pairs */
    38 #define EXC_POWER_RESET  0x000 /* vector special */
    39 #define EXC_MANUAL_RESET 0x020
    40 #define EXC_READ_ADDR_ERR 0x0E0
    41 #define EXC_WRITE_ADDR_ERR 0x100
    42 #define EXC_SLOT_ILLEGAL 0x1A0
    43 #define EXC_ILLEGAL      0x180
    44 #define EXC_TRAP         0x160
    45 #define EXC_FPDISABLE    0x800
    46 #define EXC_SLOT_FPDISABLE 0x820
    48 #define EXV_EXCEPTION    0x100  /* General exception vector */
    49 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    50 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    52 /********************** SH4 Module Definition ****************************/
    54 void sh4_init( void );
    55 void sh4_reset( void );
    56 uint32_t sh4_run_slice( uint32_t );
    57 void sh4_start( void );
    58 void sh4_stop( void );
    59 void sh4_save_state( FILE *f );
    60 int sh4_load_state( FILE *f );
    62 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    63 				       NULL, sh4_run_slice, sh4_stop,
    64 				       sh4_save_state, sh4_load_state };
    66 struct sh4_registers sh4r;
    68 void sh4_init(void)
    69 {
    70     register_io_regions( mmio_list_sh4mmio );
    71     mmu_init();
    72     sh4_reset();
    73 }
    75 void sh4_reset(void)
    76 {
    77     /* zero everything out, for the sake of having a consistent state. */
    78     memset( &sh4r, 0, sizeof(sh4r) );
    80     /* Resume running if we were halted */
    81     sh4r.sh4_state = SH4_STATE_RUNNING;
    83     sh4r.pc    = 0xA0000000;
    84     sh4r.new_pc= 0xA0000002;
    85     sh4r.vbr   = 0x00000000;
    86     sh4r.fpscr = 0x00040001;
    87     sh4r.sr    = 0x700000F0;
    89     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    90     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    92     /* Peripheral modules */
    93     INTC_reset();
    94     TMU_reset();
    95     SCIF_reset();
    96 }
    98 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    99 static int sh4_breakpoint_count = 0;
   100 static uint16_t *sh4_icache = NULL;
   101 static uint32_t sh4_icache_addr = 0;
   103 void sh4_set_breakpoint( uint32_t pc, int type )
   104 {
   105     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   106     sh4_breakpoints[sh4_breakpoint_count].type = type;
   107     sh4_breakpoint_count++;
   108 }
   110 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   111 {
   112     int i;
   114     for( i=0; i<sh4_breakpoint_count; i++ ) {
   115 	if( sh4_breakpoints[i].address == pc && 
   116 	    sh4_breakpoints[i].type == type ) {
   117 	    while( ++i < sh4_breakpoint_count ) {
   118 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   119 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   120 	    }
   121 	    sh4_breakpoint_count--;
   122 	    return TRUE;
   123 	}
   124     }
   125     return FALSE;
   126 }
   128 int sh4_get_breakpoint( uint32_t pc )
   129 {
   130     int i;
   131     for( i=0; i<sh4_breakpoint_count; i++ ) {
   132 	if( sh4_breakpoints[i].address == pc )
   133 	    return sh4_breakpoints[i].type;
   134     }
   135     return 0;
   136 }
   138 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   139 {
   140     int target = sh4r.icount + nanosecs / sh4_cpu_period;
   141     int start = sh4r.icount;
   142     int i;
   144     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   145 	if( sh4r.int_pending != 0 )
   146 	    sh4r.sh4_state = SH4_STATE_RUNNING;;
   147     }
   149     if( sh4_breakpoint_count == 0 ) {
   150 	for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   151 	    if( !sh4_execute_instruction() ) {
   152 		break;
   153 	    }
   154 	}
   155     } else {
   157 	for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   158 	    if( !sh4_execute_instruction() )
   159 		break;
   160 #ifdef ENABLE_DEBUG_MODE
   161 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
   162 		if( sh4_breakpoints[i].address == sh4r.pc ) {
   163 		    break;
   164 		}
   165 	    }
   166 	    if( i != sh4_breakpoint_count ) {
   167 		dreamcast_stop();
   168 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   169 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   170 		break;
   171 	    }
   172 #endif	
   173 	}
   174     }
   176     /* If we aborted early, but the cpu is still technically running,
   177      * we're doing a hard abort - cut the timeslice back to what we
   178      * actually executed
   179      */
   180     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   181 	nanosecs = sh4r.slice_cycle;
   182     }
   183     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   184 	TMU_run_slice( nanosecs );
   185 	SCIF_run_slice( nanosecs );
   186     }
   187     sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
   188     return nanosecs;
   189 }
   191 void sh4_stop(void)
   192 {
   194 }
   196 void sh4_save_state( FILE *f )
   197 {
   198     fwrite( &sh4r, sizeof(sh4r), 1, f );
   199     INTC_save_state( f );
   200     TMU_save_state( f );
   201     SCIF_save_state( f );
   202 }
   204 int sh4_load_state( FILE * f )
   205 {
   206     fread( &sh4r, sizeof(sh4r), 1, f );
   207     INTC_load_state( f );
   208     TMU_load_state( f );
   209     return SCIF_load_state( f );
   210 }
   212 /********************** SH4 emulation core  ****************************/
   214 void sh4_set_pc( int pc )
   215 {
   216     sh4r.pc = pc;
   217     sh4r.new_pc = pc+2;
   218 }
   220 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   221 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   223 #if(SH4_CALLTRACE == 1)
   224 #define MAX_CALLSTACK 32
   225 static struct call_stack {
   226     sh4addr_t call_addr;
   227     sh4addr_t target_addr;
   228     sh4addr_t stack_pointer;
   229 } call_stack[MAX_CALLSTACK];
   231 static int call_stack_depth = 0;
   232 int sh4_call_trace_on = 0;
   234 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   235 {
   236     if( call_stack_depth < MAX_CALLSTACK ) {
   237 	call_stack[call_stack_depth].call_addr = source;
   238 	call_stack[call_stack_depth].target_addr = dest;
   239 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   240     }
   241     call_stack_depth++;
   242 }
   244 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   245 {
   246     if( call_stack_depth > 0 ) {
   247 	call_stack_depth--;
   248     }
   249 }
   251 void fprint_stack_trace( FILE *f )
   252 {
   253     int i = call_stack_depth -1;
   254     if( i >= MAX_CALLSTACK )
   255 	i = MAX_CALLSTACK - 1;
   256     for( ; i >= 0; i-- ) {
   257 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   258 		 (call_stack_depth - i), call_stack[i].call_addr,
   259 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   260     }
   261 }
   263 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   264 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   265 #else
   266 #define TRACE_CALL( dest, rts ) 
   267 #define TRACE_RETURN( source, dest )
   268 #endif
   270 #define RAISE( x, v ) do{			\
   271     if( sh4r.vbr == 0 ) { \
   272         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   273         dreamcast_stop(); return FALSE;	\
   274     } else { \
   275         sh4r.spc = sh4r.pc;	\
   276         sh4r.ssr = sh4_read_sr(); \
   277         sh4r.sgr = sh4r.r[15]; \
   278         MMIO_WRITE(MMU,EXPEVT,x); \
   279         sh4r.pc = sh4r.vbr + v; \
   280         sh4r.new_pc = sh4r.pc + 2; \
   281         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   282 	if( sh4r.in_delay_slot ) { \
   283 	    sh4r.in_delay_slot = 0; \
   284 	    sh4r.spc -= 2; \
   285 	} \
   286     } \
   287     return TRUE; } while(0)
   289 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   290 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   291 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   292 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   293 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   294 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   296 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   298 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   299 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   301 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   302 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
   303 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
   304 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
   305 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
   307 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE )
   308 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   309 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   311 static void sh4_switch_banks( )
   312 {
   313     uint32_t tmp[8];
   315     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   316     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   317     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   318 }
   320 static void sh4_load_sr( uint32_t newval )
   321 {
   322     if( (newval ^ sh4r.sr) & SR_RB )
   323         sh4_switch_banks();
   324     sh4r.sr = newval;
   325     sh4r.t = (newval&SR_T) ? 1 : 0;
   326     sh4r.s = (newval&SR_S) ? 1 : 0;
   327     sh4r.m = (newval&SR_M) ? 1 : 0;
   328     sh4r.q = (newval&SR_Q) ? 1 : 0;
   329     intc_mask_changed();
   330 }
   332 static void sh4_write_float( uint32_t addr, int reg )
   333 {
   334     if( IS_FPU_DOUBLESIZE() ) {
   335 	if( reg & 1 ) {
   336 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   337 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   338 	} else {
   339 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   340 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   341 	}
   342     } else {
   343 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   344     }
   345 }
   347 static void sh4_read_float( uint32_t addr, int reg )
   348 {
   349     if( IS_FPU_DOUBLESIZE() ) {
   350 	if( reg & 1 ) {
   351 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   352 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   353 	} else {
   354 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   355 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   356 	}
   357     } else {
   358 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   359     }
   360 }
   362 static uint32_t sh4_read_sr( void )
   363 {
   364     /* synchronize sh4r.sr with the various bitflags */
   365     sh4r.sr &= SR_MQSTMASK;
   366     if( sh4r.t ) sh4r.sr |= SR_T;
   367     if( sh4r.s ) sh4r.sr |= SR_S;
   368     if( sh4r.m ) sh4r.sr |= SR_M;
   369     if( sh4r.q ) sh4r.sr |= SR_Q;
   370     return sh4r.sr;
   371 }
   373 /**
   374  * Raise a general CPU exception for the specified exception code.
   375  * (NOT for TRAPA or TLB exceptions)
   376  */
   377 gboolean sh4_raise_exception( int code )
   378 {
   379     RAISE( code, EXV_EXCEPTION );
   380 }
   382 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   383     if( sh4r.in_delay_slot ) {
   384 	return sh4_raise_exception(slot_code);
   385     } else {
   386 	return sh4_raise_exception(normal_code);
   387     }
   388 }
   390 gboolean sh4_raise_tlb_exception( int code )
   391 {
   392     RAISE( code, EXV_TLBMISS );
   393 }
   395 static void sh4_accept_interrupt( void )
   396 {
   397     uint32_t code = intc_accept_interrupt();
   398     sh4r.ssr = sh4_read_sr();
   399     sh4r.spc = sh4r.pc;
   400     sh4r.sgr = sh4r.r[15];
   401     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   402     MMIO_WRITE( MMU, INTEVT, code );
   403     sh4r.pc = sh4r.vbr + 0x600;
   404     sh4r.new_pc = sh4r.pc + 2;
   405     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   406 }
   408 gboolean sh4_execute_instruction( void )
   409 {
   410     uint32_t pc;
   411     unsigned short ir;
   412     uint32_t tmp;
   413     uint64_t tmpl;
   414     float ftmp;
   415     double dtmp;
   417 #define R0 sh4r.r[0]
   418 #define FR0 FR(0)
   419 #define DR0 DR(0)
   420 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   421 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   422 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   423 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   424 #define DISP8(ir) (ir&0x00FF)
   425 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   426 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   427 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   428 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   429 #define FRNn(ir) ((ir&0x0F00)>>8)
   430 #define FRMn(ir) ((ir&0x00F0)>>4)
   431 #define DRNn(ir) ((ir&0x0E00)>>9)
   432 #define DRMn(ir) ((ir&0x00E0)>>5)
   433 #define FVN(ir) ((ir&0x0C00)>>8)
   434 #define FVM(ir) ((ir&0x0300)>>6)
   435 #define FRN(ir) FR(FRNn(ir))
   436 #define FRM(ir) FR(FRMn(ir))
   437 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
   438 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
   439 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
   440 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
   441 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
   442 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
   443 #define FPULf   *((float *)&sh4r.fpul)
   444 #define FPULi    (sh4r.fpul)
   446     if( SH4_INT_PENDING() ) 
   447         sh4_accept_interrupt();
   449     pc = sh4r.pc;
   450     if( pc > 0xFFFFFF00 ) {
   451 	/* SYSCALL Magic */
   452 	syscall_invoke( pc );
   453 	sh4r.in_delay_slot = 0;
   454 	pc = sh4r.pc = sh4r.pr;
   455 	sh4r.new_pc = sh4r.pc + 2;
   456     }
   457     CHECKRALIGN16(pc);
   459     /* Read instruction */
   460     uint32_t pageaddr = pc >> 12;
   461     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   462 	ir = sh4_icache[(pc&0xFFF)>>1];
   463     } else {
   464 	sh4_icache = (uint16_t *)mem_get_page(pc);
   465 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   466 	    /* If someone's actually been so daft as to try to execute out of an IO
   467 	     * region, fallback on the full-blown memory read
   468 	     */
   469 	    sh4_icache = NULL;
   470 	    ir = MEM_READ_WORD(pc);
   471 	} else {
   472 	    sh4_icache_addr = pageaddr;
   473 	    ir = sh4_icache[(pc&0xFFF)>>1];
   474 	}
   475     }
   476     sh4r.icount++;
   478     switch( (ir&0xF000)>>12 ) {
   479         case 0: /* 0000nnnnmmmmxxxx */
   480             switch( ir&0x000F ) {
   481                 case 2:
   482                     switch( (ir&0x00F0)>>4 ) {
   483                         case 0: /* STC     SR, Rn */
   484                             CHECKPRIV();
   485                             RN(ir) = sh4_read_sr();
   486                             break;
   487                         case 1: /* STC     GBR, Rn */
   488                             RN(ir) = sh4r.gbr;
   489                             break;
   490                         case 2: /* STC     VBR, Rn */
   491                             CHECKPRIV();
   492                             RN(ir) = sh4r.vbr;
   493                             break;
   494                         case 3: /* STC     SSR, Rn */
   495                             CHECKPRIV();
   496                             RN(ir) = sh4r.ssr;
   497                             break;
   498                         case 4: /* STC     SPC, Rn */
   499                             CHECKPRIV();
   500                             RN(ir) = sh4r.spc;
   501                             break;
   502                         case 8: case 9: case 10: case 11: case 12: case 13:
   503                         case 14: case 15:/* STC     Rm_bank, Rn */
   504                             CHECKPRIV();
   505                             RN(ir) = RN_BANK(ir);
   506                             break;
   507                         default: UNDEF(ir);
   508                     }
   509                     break;
   510                 case 3:
   511                     switch( (ir&0x00F0)>>4 ) {
   512                         case 0: /* BSRF    Rn */
   513                             CHECKSLOTILLEGAL();
   514                             CHECKDEST( pc + 4 + RN(ir) );
   515                             sh4r.in_delay_slot = 1;
   516                             sh4r.pr = sh4r.pc + 4;
   517                             sh4r.pc = sh4r.new_pc;
   518                             sh4r.new_pc = pc + 4 + RN(ir);
   519 			    TRACE_CALL( pc, sh4r.new_pc );
   520                             return TRUE;
   521                         case 2: /* BRAF    Rn */
   522                             CHECKSLOTILLEGAL();
   523                             CHECKDEST( pc + 4 + RN(ir) );
   524                             sh4r.in_delay_slot = 1;
   525                             sh4r.pc = sh4r.new_pc;
   526                             sh4r.new_pc = pc + 4 + RN(ir);
   527                             return TRUE;
   528                         case 8: /* PREF    [Rn] */
   529                             tmp = RN(ir);
   530                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   531                                 /* Store queue operation */
   532                                 int queue = (tmp&0x20)>>2;
   533                                 int32_t *src = &sh4r.store_queue[queue];
   534                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   535                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   536                                 mem_copy_to_sh4( target, src, 32 );
   537                             }
   538                             break;
   539                         case 9: /* OCBI    [Rn] */
   540                         case 10:/* OCBP    [Rn] */
   541                         case 11:/* OCBWB   [Rn] */
   542                             /* anything? */
   543                             break;
   544                         case 12:/* MOVCA.L R0, [Rn] */
   545 			    tmp = RN(ir);
   546 			    CHECKWALIGN32(tmp);
   547 			    MEM_WRITE_LONG( tmp, R0 );
   548 			    break;
   549                         default: UNDEF(ir);
   550                     }
   551                     break;
   552                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   553                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   554                     break;
   555                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   556 		    CHECKWALIGN16( R0 + RN(ir) );
   557                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   558                     break;
   559                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   560 		    CHECKWALIGN32( R0 + RN(ir) );
   561                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   562                     break;
   563                 case 7: /* MUL.L   Rm, Rn */
   564                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   565                         (RM(ir) * RN(ir));
   566                     break;
   567                 case 8: 
   568                     switch( (ir&0x0FF0)>>4 ) {
   569                         case 0: /* CLRT    */
   570                             sh4r.t = 0;
   571                             break;
   572                         case 1: /* SETT    */
   573                             sh4r.t = 1;
   574                             break;
   575                         case 2: /* CLRMAC  */
   576                             sh4r.mac = 0;
   577                             break;
   578                         case 3: /* LDTLB   */
   579                             break;
   580                         case 4: /* CLRS    */
   581                             sh4r.s = 0;
   582                             break;
   583                         case 5: /* SETS    */
   584                             sh4r.s = 1;
   585                             break;
   586                         default: UNDEF(ir);
   587                     }
   588                     break;
   589                 case 9: 
   590                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   591                         RN(ir) = sh4r.t;
   592                     else if( ir == 0x0019 ) /* DIV0U   */
   593                         sh4r.m = sh4r.q = sh4r.t = 0;
   594                     else if( ir == 0x0009 )
   595                         /* NOP     */;
   596                     else UNDEF(ir);
   597                     break;
   598                 case 10:
   599                     switch( (ir&0x00F0) >> 4 ) {
   600                         case 0: /* STS     MACH, Rn */
   601                             RN(ir) = sh4r.mac >> 32;
   602                             break;
   603                         case 1: /* STS     MACL, Rn */
   604                             RN(ir) = (uint32_t)sh4r.mac;
   605                             break;
   606                         case 2: /* STS     PR, Rn */
   607                             RN(ir) = sh4r.pr;
   608                             break;
   609                         case 3: /* STC     SGR, Rn */
   610                             CHECKPRIV();
   611                             RN(ir) = sh4r.sgr;
   612                             break;
   613                         case 5:/* STS      FPUL, Rn */
   614                             RN(ir) = sh4r.fpul;
   615                             break;
   616                         case 6: /* STS     FPSCR, Rn */
   617                             RN(ir) = sh4r.fpscr;
   618                             break;
   619                         case 15:/* STC     DBR, Rn */
   620                             CHECKPRIV();
   621                             RN(ir) = sh4r.dbr;
   622                             break;
   623                         default: UNDEF(ir);
   624                     }
   625                     break;
   626                 case 11:
   627                     switch( (ir&0x0FF0)>>4 ) {
   628                         case 0: /* RTS     */
   629                             CHECKSLOTILLEGAL();
   630                             CHECKDEST( sh4r.pr );
   631                             sh4r.in_delay_slot = 1;
   632                             sh4r.pc = sh4r.new_pc;
   633                             sh4r.new_pc = sh4r.pr;
   634                             TRACE_RETURN( pc, sh4r.new_pc );
   635                             return TRUE;
   636                         case 1: /* SLEEP   */
   637 			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   638 				sh4r.sh4_state = SH4_STATE_STANDBY;
   639 			    } else {
   640 				sh4r.sh4_state = SH4_STATE_SLEEP;
   641 			    }
   642 			    return FALSE; /* Halt CPU */
   643                         case 2: /* RTE     */
   644                             CHECKPRIV();
   645                             CHECKDEST( sh4r.spc );
   646                             CHECKSLOTILLEGAL();
   647                             sh4r.in_delay_slot = 1;
   648                             sh4r.pc = sh4r.new_pc;
   649                             sh4r.new_pc = sh4r.spc;
   650                             sh4_load_sr( sh4r.ssr );
   651                             return TRUE;
   652                         default:UNDEF(ir);
   653                     }
   654                     break;
   655                 case 12:/* MOV.B   [R0+R%d], R%d */
   656                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   657                     break;
   658                 case 13:/* MOV.W   [R0+R%d], R%d */
   659 		    CHECKRALIGN16( R0 + RM(ir) );
   660                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   661                     break;
   662                 case 14:/* MOV.L   [R0+R%d], R%d */
   663 		    CHECKRALIGN32( R0 + RM(ir) );
   664                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   665                     break;
   666                 case 15:/* MAC.L   [Rm++], [Rn++] */
   667 		    CHECKRALIGN32( RM(ir) );
   668 		    CHECKRALIGN32( RN(ir) );
   669                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   670                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   671                     if( sh4r.s ) {
   672                         /* 48-bit Saturation. Yuch */
   673                         tmpl += SIGNEXT48(sh4r.mac);
   674                         if( tmpl < 0xFFFF800000000000LL )
   675                             tmpl = 0xFFFF800000000000LL;
   676                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   677                             tmpl = 0x00007FFFFFFFFFFFLL;
   678                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   679                             (tmpl&0x0000FFFFFFFFFFFFLL);
   680                     } else sh4r.mac = tmpl;
   682                     RM(ir) += 4;
   683                     RN(ir) += 4;
   685                     break;
   686                 default: UNDEF(ir);
   687             }
   688             break;
   689         case 1: /* 0001nnnnmmmmdddd */
   690             /* MOV.L   Rm, [Rn + disp4*4] */
   691 	    tmp = RN(ir) + (DISP4(ir)<<2);
   692 	    CHECKWALIGN32( tmp );
   693             MEM_WRITE_LONG( tmp, RM(ir) );
   694             break;
   695         case 2: /* 0010nnnnmmmmxxxx */
   696             switch( ir&0x000F ) {
   697                 case 0: /* MOV.B   Rm, [Rn] */
   698                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   699                     break;
   700                 case 1: /* MOV.W   Rm, [Rn] */
   701                	    CHECKWALIGN16( RN(ir) );
   702 		    MEM_WRITE_WORD( RN(ir), RM(ir) );
   703                     break;
   704                 case 2: /* MOV.L   Rm, [Rn] */
   705 		    CHECKWALIGN32( RN(ir) );
   706                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   707                     break;
   708                 case 3: UNDEF(ir);
   709                     break;
   710                 case 4: /* MOV.B   Rm, [--Rn] */
   711                     RN(ir) --;
   712                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   713                     break;
   714                 case 5: /* MOV.W   Rm, [--Rn] */
   715                     RN(ir) -= 2;
   716 		    CHECKWALIGN16( RN(ir) );
   717                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   718                     break;
   719                 case 6: /* MOV.L   Rm, [--Rn] */
   720                     RN(ir) -= 4;
   721 		    CHECKWALIGN32( RN(ir) );
   722                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   723                     break;
   724                 case 7: /* DIV0S   Rm, Rn */
   725                     sh4r.q = RN(ir)>>31;
   726                     sh4r.m = RM(ir)>>31;
   727                     sh4r.t = sh4r.q ^ sh4r.m;
   728                     break;
   729                 case 8: /* TST     Rm, Rn */
   730                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   731                     break;
   732                 case 9: /* AND     Rm, Rn */
   733                     RN(ir) &= RM(ir);
   734                     break;
   735                 case 10:/* XOR     Rm, Rn */
   736                     RN(ir) ^= RM(ir);
   737                     break;
   738                 case 11:/* OR      Rm, Rn */
   739                     RN(ir) |= RM(ir);
   740                     break;
   741                 case 12:/* CMP/STR Rm, Rn */
   742                     /* set T = 1 if any byte in RM & RN is the same */
   743                     tmp = RM(ir) ^ RN(ir);
   744                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   745                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   746                     break;
   747                 case 13:/* XTRCT   Rm, Rn */
   748                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   749                     break;
   750                 case 14:/* MULU.W  Rm, Rn */
   751                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   752                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   753                     break;
   754                 case 15:/* MULS.W  Rm, Rn */
   755                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   756                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   757                     break;
   758             }
   759             break;
   760         case 3: /* 0011nnnnmmmmxxxx */
   761             switch( ir&0x000F ) {
   762                 case 0: /* CMP/EQ  Rm, Rn */
   763                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   764                     break;
   765                 case 2: /* CMP/HS  Rm, Rn */
   766                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   767                     break;
   768                 case 3: /* CMP/GE  Rm, Rn */
   769                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   770                     break;
   771                 case 4: { /* DIV1    Rm, Rn */
   772                     /* This is just from the sh4p manual with some
   773                      * simplifications (someone want to check it's correct? :)
   774                      * Why they couldn't just provide a real DIV instruction...
   775                      * Please oh please let the translator batch these things
   776                      * up into a single DIV... */
   777                     uint32_t tmp0, tmp1, tmp2, dir;
   779                     dir = sh4r.q ^ sh4r.m;
   780                     sh4r.q = (RN(ir) >> 31);
   781                     tmp2 = RM(ir);
   782                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   783                     tmp0 = RN(ir);
   784                     if( dir ) {
   785                         RN(ir) += tmp2;
   786                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   787                     } else {
   788                         RN(ir) -= tmp2;
   789                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   790                     }
   791                     sh4r.q ^= sh4r.m ^ tmp1;
   792                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   793                     break; }
   794                 case 5: /* DMULU.L Rm, Rn */
   795                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   796                     break;
   797                 case 6: /* CMP/HI  Rm, Rn */
   798                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   799                     break;
   800                 case 7: /* CMP/GT  Rm, Rn */
   801                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   802                     break;
   803                 case 8: /* SUB     Rm, Rn */
   804                     RN(ir) -= RM(ir);
   805                     break;
   806                 case 10:/* SUBC    Rm, Rn */
   807                     tmp = RN(ir);
   808                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   809                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   810                     break;
   811                 case 11:/* SUBV    Rm, Rn */
   812                     UNIMP(ir);
   813                     break;
   814                 case 12:/* ADD     Rm, Rn */
   815                     RN(ir) += RM(ir);
   816                     break;
   817                 case 13:/* DMULS.L Rm, Rn */
   818                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   819                     break;
   820                 case 14:/* ADDC    Rm, Rn */
   821                     tmp = RN(ir);
   822                     RN(ir) += RM(ir) + sh4r.t;
   823                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   824                     break;
   825                 case 15:/* ADDV    Rm, Rn */
   826 		    tmp = RN(ir) + RM(ir);
   827 		    sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
   828 		    RN(ir) = tmp;
   829                     break;
   830                 default: UNDEF(ir);
   831             }
   832             break;
   833         case 4: /* 0100nnnnxxxxxxxx */
   834             switch( ir&0x00FF ) {
   835                 case 0x00: /* SHLL    Rn */
   836                     sh4r.t = RN(ir) >> 31;
   837                     RN(ir) <<= 1;
   838                     break;
   839                 case 0x01: /* SHLR    Rn */
   840                     sh4r.t = RN(ir) & 0x00000001;
   841                     RN(ir) >>= 1;
   842                     break;
   843                 case 0x02: /* STS.L   MACH, [--Rn] */
   844                     RN(ir) -= 4;
   845 		    CHECKWALIGN32( RN(ir) );
   846                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   847                     break;
   848                 case 0x03: /* STC.L   SR, [--Rn] */
   849                     CHECKPRIV();
   850                     RN(ir) -= 4;
   851 		    CHECKWALIGN32( RN(ir) );
   852                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   853                     break;
   854                 case 0x04: /* ROTL    Rn */
   855                     sh4r.t = RN(ir) >> 31;
   856                     RN(ir) <<= 1;
   857                     RN(ir) |= sh4r.t;
   858                     break;
   859                 case 0x05: /* ROTR    Rn */
   860                     sh4r.t = RN(ir) & 0x00000001;
   861                     RN(ir) >>= 1;
   862                     RN(ir) |= (sh4r.t << 31);
   863                     break;
   864                 case 0x06: /* LDS.L   [Rn++], MACH */
   865 		    CHECKRALIGN32( RN(ir) );
   866                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   867                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   868                     RN(ir) += 4;
   869                     break;
   870                 case 0x07: /* LDC.L   [Rn++], SR */
   871 		    CHECKSLOTILLEGAL();
   872                     CHECKPRIV();
   873 		    CHECKWALIGN32( RN(ir) );
   874                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   875                     RN(ir) +=4;
   876                     break;
   877                 case 0x08: /* SHLL2   Rn */
   878                     RN(ir) <<= 2;
   879                     break;
   880                 case 0x09: /* SHLR2   Rn */
   881                     RN(ir) >>= 2;
   882                     break;
   883                 case 0x0A: /* LDS     Rn, MACH */
   884                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   885                         (((uint64_t)RN(ir))<<32);
   886                     break;
   887                 case 0x0B: /* JSR     [Rn] */
   888                     CHECKDEST( RN(ir) );
   889                     CHECKSLOTILLEGAL();
   890                     sh4r.in_delay_slot = 1;
   891                     sh4r.pc = sh4r.new_pc;
   892                     sh4r.new_pc = RN(ir);
   893                     sh4r.pr = pc + 4;
   894 		    TRACE_CALL( pc, sh4r.new_pc );
   895                     return TRUE;
   896                 case 0x0E: /* LDC     Rn, SR */
   897 		    CHECKSLOTILLEGAL();
   898                     CHECKPRIV();
   899                     sh4_load_sr( RN(ir) );
   900                     break;
   901                 case 0x10: /* DT      Rn */
   902                     RN(ir) --;
   903                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   904                     break;
   905                 case 0x11: /* CMP/PZ  Rn */
   906                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   907                     break;
   908                 case 0x12: /* STS.L   MACL, [--Rn] */
   909                     RN(ir) -= 4;
   910 		    CHECKWALIGN32( RN(ir) );
   911                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   912                     break;
   913                 case 0x13: /* STC.L   GBR, [--Rn] */
   914                     RN(ir) -= 4;
   915 		    CHECKWALIGN32( RN(ir) );
   916                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   917                     break;
   918                 case 0x15: /* CMP/PL  Rn */
   919                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   920                     break;
   921                 case 0x16: /* LDS.L   [Rn++], MACL */
   922 		    CHECKRALIGN32( RN(ir) );
   923                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   924                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   925                     RN(ir) += 4;
   926                     break;
   927                 case 0x17: /* LDC.L   [Rn++], GBR */
   928 		    CHECKRALIGN32( RN(ir) );
   929                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   930                     RN(ir) +=4;
   931                     break;
   932                 case 0x18: /* SHLL8   Rn */
   933                     RN(ir) <<= 8;
   934                     break;
   935                 case 0x19: /* SHLR8   Rn */
   936                     RN(ir) >>= 8;
   937                     break;
   938                 case 0x1A: /* LDS     Rn, MACL */
   939                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   940                         (uint64_t)((uint32_t)(RN(ir)));
   941                     break;
   942                 case 0x1B: /* TAS.B   [Rn] */
   943                     tmp = MEM_READ_BYTE( RN(ir) );
   944                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   945                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   946                     break;
   947                 case 0x1E: /* LDC     Rn, GBR */
   948                     sh4r.gbr = RN(ir);
   949                     break;
   950                 case 0x20: /* SHAL    Rn */
   951                     sh4r.t = RN(ir) >> 31;
   952                     RN(ir) <<= 1;
   953                     break;
   954                 case 0x21: /* SHAR    Rn */
   955                     sh4r.t = RN(ir) & 0x00000001;
   956                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   957                     break;
   958                 case 0x22: /* STS.L   PR, [--Rn] */
   959                     RN(ir) -= 4;
   960 		    CHECKWALIGN32( RN(ir) );
   961                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   962                     break;
   963                 case 0x23: /* STC.L   VBR, [--Rn] */
   964                     CHECKPRIV();
   965                     RN(ir) -= 4;
   966 		    CHECKWALIGN32( RN(ir) );
   967                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   968                     break;
   969                 case 0x24: /* ROTCL   Rn */
   970                     tmp = RN(ir) >> 31;
   971                     RN(ir) <<= 1;
   972                     RN(ir) |= sh4r.t;
   973                     sh4r.t = tmp;
   974                     break;
   975                 case 0x25: /* ROTCR   Rn */
   976                     tmp = RN(ir) & 0x00000001;
   977                     RN(ir) >>= 1;
   978                     RN(ir) |= (sh4r.t << 31 );
   979                     sh4r.t = tmp;
   980                     break;
   981                 case 0x26: /* LDS.L   [Rn++], PR */
   982 		    CHECKRALIGN32( RN(ir) );
   983                     sh4r.pr = MEM_READ_LONG( RN(ir) );
   984                     RN(ir) += 4;
   985                     break;
   986                 case 0x27: /* LDC.L   [Rn++], VBR */
   987                     CHECKPRIV();
   988 		    CHECKRALIGN32( RN(ir) );
   989                     sh4r.vbr = MEM_READ_LONG(RN(ir));
   990                     RN(ir) +=4;
   991                     break;
   992                 case 0x28: /* SHLL16  Rn */
   993                     RN(ir) <<= 16;
   994                     break;
   995                 case 0x29: /* SHLR16  Rn */
   996                     RN(ir) >>= 16;
   997                     break;
   998                 case 0x2A: /* LDS     Rn, PR */
   999                     sh4r.pr = RN(ir);
  1000                     break;
  1001                 case 0x2B: /* JMP     [Rn] */
  1002                     CHECKDEST( RN(ir) );
  1003                     CHECKSLOTILLEGAL();
  1004                     sh4r.in_delay_slot = 1;
  1005                     sh4r.pc = sh4r.new_pc;
  1006                     sh4r.new_pc = RN(ir);
  1007                     return TRUE;
  1008                 case 0x2E: /* LDC     Rn, VBR */
  1009                     CHECKPRIV();
  1010                     sh4r.vbr = RN(ir);
  1011                     break;
  1012                 case 0x32: /* STC.L   SGR, [--Rn] */
  1013                     CHECKPRIV();
  1014                     RN(ir) -= 4;
  1015 		    CHECKWALIGN32( RN(ir) );
  1016                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
  1017                     break;
  1018                 case 0x33: /* STC.L   SSR, [--Rn] */
  1019                     CHECKPRIV();
  1020                     RN(ir) -= 4;
  1021 		    CHECKWALIGN32( RN(ir) );
  1022                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
  1023                     break;
  1024                 case 0x37: /* LDC.L   [Rn++], SSR */
  1025                     CHECKPRIV();
  1026 		    CHECKRALIGN32( RN(ir) );
  1027                     sh4r.ssr = MEM_READ_LONG(RN(ir));
  1028                     RN(ir) +=4;
  1029                     break;
  1030                 case 0x3E: /* LDC     Rn, SSR */
  1031                     CHECKPRIV();
  1032                     sh4r.ssr = RN(ir);
  1033                     break;
  1034                 case 0x43: /* STC.L   SPC, [--Rn] */
  1035                     CHECKPRIV();
  1036                     RN(ir) -= 4;
  1037 		    CHECKWALIGN32( RN(ir) );
  1038                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
  1039                     break;
  1040                 case 0x47: /* LDC.L   [Rn++], SPC */
  1041                     CHECKPRIV();
  1042 		    CHECKRALIGN32( RN(ir) );
  1043                     sh4r.spc = MEM_READ_LONG(RN(ir));
  1044                     RN(ir) +=4;
  1045                     break;
  1046                 case 0x4E: /* LDC     Rn, SPC */
  1047                     CHECKPRIV();
  1048                     sh4r.spc = RN(ir);
  1049                     break;
  1050                 case 0x52: /* STS.L   FPUL, [--Rn] */
  1051                     RN(ir) -= 4;
  1052 		    CHECKWALIGN32( RN(ir) );
  1053                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
  1054                     break;
  1055                 case 0x56: /* LDS.L   [Rn++], FPUL */
  1056 		    CHECKRALIGN32( RN(ir) );
  1057                     sh4r.fpul = MEM_READ_LONG(RN(ir));
  1058                     RN(ir) +=4;
  1059                     break;
  1060                 case 0x5A: /* LDS     Rn, FPUL */
  1061                     sh4r.fpul = RN(ir);
  1062                     break;
  1063                 case 0x62: /* STS.L   FPSCR, [--Rn] */
  1064                     RN(ir) -= 4;
  1065 		    CHECKWALIGN32( RN(ir) );
  1066                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
  1067                     break;
  1068                 case 0x66: /* LDS.L   [Rn++], FPSCR */
  1069 		    CHECKRALIGN32( RN(ir) );
  1070                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
  1071                     RN(ir) +=4;
  1072                     break;
  1073                 case 0x6A: /* LDS     Rn, FPSCR */
  1074                     sh4r.fpscr = RN(ir);
  1075                     break;
  1076                 case 0xF2: /* STC.L   DBR, [--Rn] */
  1077                     CHECKPRIV();
  1078                     RN(ir) -= 4;
  1079 		    CHECKWALIGN32( RN(ir) );
  1080                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
  1081                     break;
  1082                 case 0xF6: /* LDC.L   [Rn++], DBR */
  1083                     CHECKPRIV();
  1084 		    CHECKRALIGN32( RN(ir) );
  1085                     sh4r.dbr = MEM_READ_LONG(RN(ir));
  1086                     RN(ir) +=4;
  1087                     break;
  1088                 case 0xFA: /* LDC     Rn, DBR */
  1089                     CHECKPRIV();
  1090                     sh4r.dbr = RN(ir);
  1091                     break;
  1092                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
  1093                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
  1094                     CHECKPRIV();
  1095                     RN(ir) -= 4;
  1096 		    CHECKWALIGN32( RN(ir) );
  1097                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
  1098                     break;
  1099                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
  1100                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
  1101                     CHECKPRIV();
  1102 		    CHECKRALIGN32( RN(ir) );
  1103                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
  1104                     RN(ir) += 4;
  1105                     break;
  1106                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
  1107                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
  1108                     CHECKPRIV();
  1109                     RN_BANK(ir) = RM(ir);
  1110                     break;
  1111                 default:
  1112                     if( (ir&0x000F) == 0x0F ) {
  1113                         /* MAC.W   [Rm++], [Rn++] */
  1114 			CHECKRALIGN16( RN(ir) );
  1115 			CHECKRALIGN16( RM(ir) );
  1116                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
  1117                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
  1118                         if( sh4r.s ) {
  1119                             /* FIXME */
  1120                             UNIMP(ir);
  1121                         } else sh4r.mac += SIGNEXT32(tmp);
  1122                         RM(ir) += 2;
  1123                         RN(ir) += 2;
  1124                     } else if( (ir&0x000F) == 0x0C ) {
  1125                         /* SHAD    Rm, Rn */
  1126                         tmp = RM(ir);
  1127                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1128                         else if( (tmp & 0x1F) == 0 )  
  1129 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
  1130                         else 
  1131 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
  1132                     } else if( (ir&0x000F) == 0x0D ) {
  1133                         /* SHLD    Rm, Rn */
  1134                         tmp = RM(ir);
  1135                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1136                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
  1137                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
  1138                     } else UNDEF(ir);
  1140             break;
  1141         case 5: /* 0101nnnnmmmmdddd */
  1142             /* MOV.L   [Rm + disp4*4], Rn */
  1143 	    tmp = RM(ir) + (DISP4(ir)<<2);
  1144 	    CHECKRALIGN32( tmp );
  1145             RN(ir) = MEM_READ_LONG( tmp );
  1146             break;
  1147         case 6: /* 0110xxxxxxxxxxxx */
  1148             switch( ir&0x000f ) {
  1149                 case 0: /* MOV.B   [Rm], Rn */
  1150                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1151                     break;
  1152                 case 1: /* MOV.W   [Rm], Rn */
  1153 		    CHECKRALIGN16( RM(ir) );
  1154                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1155                     break;
  1156                 case 2: /* MOV.L   [Rm], Rn */
  1157 		    CHECKRALIGN32( RM(ir) );
  1158                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1159                     break;
  1160                 case 3: /* MOV     Rm, Rn */
  1161                     RN(ir) = RM(ir);
  1162                     break;
  1163                 case 4: /* MOV.B   [Rm++], Rn */
  1164                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1165                     RM(ir) ++;
  1166                     break;
  1167                 case 5: /* MOV.W   [Rm++], Rn */
  1168 		    CHECKRALIGN16( RM(ir) );
  1169                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1170                     RM(ir) += 2;
  1171                     break;
  1172                 case 6: /* MOV.L   [Rm++], Rn */
  1173 		    CHECKRALIGN32( RM(ir) );
  1174                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1175                     RM(ir) += 4;
  1176                     break;
  1177                 case 7: /* NOT     Rm, Rn */
  1178                     RN(ir) = ~RM(ir);
  1179                     break;
  1180                 case 8: /* SWAP.B  Rm, Rn */
  1181                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
  1182                         ((RM(ir)&0x000000FF)<<8);
  1183                     break;
  1184                 case 9: /* SWAP.W  Rm, Rn */
  1185                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
  1186                     break;
  1187                 case 10:/* NEGC    Rm, Rn */
  1188                     tmp = 0 - RM(ir);
  1189                     RN(ir) = tmp - sh4r.t;
  1190                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
  1191                     break;
  1192                 case 11:/* NEG     Rm, Rn */
  1193                     RN(ir) = 0 - RM(ir);
  1194                     break;
  1195                 case 12:/* EXTU.B  Rm, Rn */
  1196                     RN(ir) = RM(ir)&0x000000FF;
  1197                     break;
  1198                 case 13:/* EXTU.W  Rm, Rn */
  1199                     RN(ir) = RM(ir)&0x0000FFFF;
  1200                     break;
  1201                 case 14:/* EXTS.B  Rm, Rn */
  1202                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
  1203                     break;
  1204                 case 15:/* EXTS.W  Rm, Rn */
  1205                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
  1206                     break;
  1208             break;
  1209         case 7: /* 0111nnnniiiiiiii */
  1210             /* ADD    imm8, Rn */
  1211             RN(ir) += IMM8(ir);
  1212             break;
  1213         case 8: /* 1000xxxxxxxxxxxx */
  1214             switch( (ir&0x0F00) >> 8 ) {
  1215                 case 0: /* MOV.B   R0, [Rm + disp4] */
  1216                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
  1217                     break;
  1218                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
  1219 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1220 		    CHECKWALIGN16( tmp );
  1221                     MEM_WRITE_WORD( tmp, R0 );
  1222                     break;
  1223                 case 4: /* MOV.B   [Rm + disp4], R0 */
  1224                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
  1225                     break;
  1226                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
  1227 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1228 		    CHECKRALIGN16( tmp );
  1229                     R0 = MEM_READ_WORD( tmp );
  1230                     break;
  1231                 case 8: /* CMP/EQ  imm, R0 */
  1232                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
  1233                     break;
  1234                 case 9: /* BT      disp8 */
  1235                     CHECKSLOTILLEGAL();
  1236                     if( sh4r.t ) {
  1237                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1238                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1239                         sh4r.new_pc = sh4r.pc + 2;
  1240                         return TRUE;
  1242                     break;
  1243                 case 11:/* BF      disp8 */
  1244                     CHECKSLOTILLEGAL();
  1245                     if( !sh4r.t ) {
  1246                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1247                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1248                         sh4r.new_pc = sh4r.pc + 2;
  1249                         return TRUE;
  1251                     break;
  1252                 case 13:/* BT/S    disp8 */
  1253                     CHECKSLOTILLEGAL();
  1254                     if( sh4r.t ) {
  1255                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1256                         sh4r.in_delay_slot = 1;
  1257                         sh4r.pc = sh4r.new_pc;
  1258                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1259                         sh4r.in_delay_slot = 1;
  1260                         return TRUE;
  1262                     break;
  1263                 case 15:/* BF/S    disp8 */
  1264                     CHECKSLOTILLEGAL();
  1265                     if( !sh4r.t ) {
  1266                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1267                         sh4r.in_delay_slot = 1;
  1268                         sh4r.pc = sh4r.new_pc;
  1269                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1270                         return TRUE;
  1272                     break;
  1273                 default: UNDEF(ir);
  1275             break;
  1276         case 9: /* 1001xxxxxxxxxxxx */
  1277             /* MOV.W   [disp8*2 + pc + 4], Rn */
  1278 	    CHECKSLOTILLEGAL();
  1279 	    tmp = pc + 4 + (DISP8(ir)<<1);
  1280             RN(ir) = MEM_READ_WORD( tmp );
  1281             break;
  1282         case 10:/* 1010dddddddddddd */
  1283             /* BRA     disp12 */
  1284             CHECKSLOTILLEGAL();
  1285             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
  1286             sh4r.in_delay_slot = 1;
  1287             sh4r.pc = sh4r.new_pc;
  1288             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1289             return TRUE;
  1290         case 11:/* 1011dddddddddddd */
  1291             /* BSR     disp12 */
  1292             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
  1293 	    CHECKSLOTILLEGAL();
  1294             sh4r.in_delay_slot = 1;
  1295             sh4r.pr = pc + 4;
  1296             sh4r.pc = sh4r.new_pc;
  1297             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1298 	    TRACE_CALL( pc, sh4r.new_pc );
  1299             return TRUE;
  1300         case 12:/* 1100xxxxdddddddd */
  1301         switch( (ir&0x0F00)>>8 ) {
  1302                 case 0: /* MOV.B  R0, [GBR + disp8] */
  1303                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
  1304                     break;
  1305                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
  1306 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1307 		    CHECKWALIGN16( tmp );
  1308                     MEM_WRITE_WORD( tmp, R0 );
  1309                     break;
  1310                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
  1311 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1312 		    CHECKWALIGN32( tmp );
  1313                     MEM_WRITE_LONG( tmp, R0 );
  1314                     break;
  1315                 case 3: /* TRAPA   imm8 */
  1316                     CHECKSLOTILLEGAL();
  1317                     MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
  1318 		    sh4r.pc += 2;
  1319                     sh4_raise_exception( EXC_TRAP );
  1320                     break;
  1321                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1322                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1323                     break;
  1324                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1325 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1326 		    CHECKRALIGN16( tmp );
  1327                     R0 = MEM_READ_WORD( tmp );
  1328                     break;
  1329                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1330 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1331 		    CHECKRALIGN32( tmp );
  1332                     R0 = MEM_READ_LONG( tmp );
  1333                     break;
  1334                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1335 		    CHECKSLOTILLEGAL();
  1336                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1337                     break;
  1338                 case 8: /* TST     imm8, R0 */
  1339                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1340                     break;
  1341                 case 9: /* AND     imm8, R0 */
  1342                     R0 &= UIMM8(ir);
  1343                     break;
  1344                 case 10:/* XOR     imm8, R0 */
  1345                     R0 ^= UIMM8(ir);
  1346                     break;
  1347                 case 11:/* OR      imm8, R0 */
  1348                     R0 |= UIMM8(ir);
  1349                     break;
  1350                 case 12:/* TST.B   imm8, [R0+GBR] */		    
  1351                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1352                     break;
  1353                 case 13:/* AND.B   imm8, [R0+GBR] */
  1354                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1355                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1356                     break;
  1357                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1358                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1359                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1360                     break;
  1361                 case 15:/* OR.B    imm8, [R0+GBR] */
  1362                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1363                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1364                     break;
  1366             break;
  1367         case 13:/* 1101nnnndddddddd */
  1368             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1369 	    CHECKSLOTILLEGAL();
  1370 	    tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1371             RN(ir) = MEM_READ_LONG( tmp );
  1372             break;
  1373         case 14:/* 1110nnnniiiiiiii */
  1374             /* MOV     imm8, Rn */
  1375             RN(ir) = IMM8(ir);
  1376             break;
  1377         case 15:/* 1111xxxxxxxxxxxx */
  1378             CHECKFPUEN();
  1379 	    if( IS_FPU_DOUBLEPREC() ) {
  1380 		switch( ir&0x000F ) {
  1381                 case 0: /* FADD    FRm, FRn */
  1382                     DRN(ir) += DRM(ir);
  1383                     break;
  1384                 case 1: /* FSUB    FRm, FRn */
  1385                     DRN(ir) -= DRM(ir);
  1386                     break;
  1387                 case 2: /* FMUL    FRm, FRn */
  1388                     DRN(ir) = DRN(ir) * DRM(ir);
  1389                     break;
  1390                 case 3: /* FDIV    FRm, FRn */
  1391                     DRN(ir) = DRN(ir) / DRM(ir);
  1392                     break;
  1393                 case 4: /* FCMP/EQ FRm, FRn */
  1394                     sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
  1395                     break;
  1396                 case 5: /* FCMP/GT FRm, FRn */
  1397                     sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
  1398                     break;
  1399                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1400                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1401                     break;
  1402                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1403                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1404                     break;
  1405                 case 8: /* FMOV.S  [Rm], FRn */
  1406                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1407                     break;
  1408                 case 9: /* FMOV.S  [Rm++], FRn */
  1409                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1410                     RM(ir) += FP_WIDTH;
  1411                     break;
  1412                 case 10:/* FMOV.S  FRm, [Rn] */
  1413                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1414                     break;
  1415                 case 11:/* FMOV.S  FRm, [--Rn] */
  1416                     RN(ir) -= FP_WIDTH;
  1417                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1418                     break;
  1419                 case 12:/* FMOV    FRm, FRn */
  1420 		    if( IS_FPU_DOUBLESIZE() )
  1421 			DRN(ir) = DRM(ir);
  1422 		    else
  1423 			FRN(ir) = FRM(ir);
  1424                     break;
  1425                 case 13:
  1426                     switch( (ir&0x00F0) >> 4 ) {
  1427 		    case 0: /* FSTS    FPUL, FRn */
  1428 			FRN(ir) = FPULf;
  1429 			break;
  1430 		    case 1: /* FLDS    FRn,FPUL */
  1431 			FPULf = FRN(ir);
  1432 			break;
  1433 		    case 2: /* FLOAT   FPUL, FRn */
  1434 			DRN(ir) = (float)FPULi;
  1435 			break;
  1436 		    case 3: /* FTRC    FRn, FPUL */
  1437 			dtmp = DRN(ir);
  1438 			if( dtmp >= MAX_INTF )
  1439 			    FPULi = MAX_INT;
  1440 			else if( dtmp <= MIN_INTF )
  1441 			    FPULi = MIN_INT;
  1442 			else 
  1443 			    FPULi = (int32_t)dtmp;
  1444 			break;
  1445 		    case 4: /* FNEG    FRn */
  1446 			DRN(ir) = -DRN(ir);
  1447 			break;
  1448 		    case 5: /* FABS    FRn */
  1449 			DRN(ir) = fabs(DRN(ir));
  1450 			break;
  1451 		    case 6: /* FSQRT   FRn */
  1452 			DRN(ir) = sqrt(DRN(ir));
  1453 			break;
  1454 		    case 7: /* FSRRA FRn */
  1455 			/* NO-OP when PR=1 */
  1456 			break;
  1457 		    case 8: /* FLDI0   FRn */
  1458 			DRN(ir) = 0.0;
  1459 			break;
  1460 		    case 9: /* FLDI1   FRn */
  1461 			DRN(ir) = 1.0;
  1462 			break;
  1463 		    case 10: /* FCNVSD FPUL, DRn */
  1464 			if( ! IS_FPU_DOUBLESIZE() )
  1465 			    DRN(ir) = (double)FPULf;
  1466 			break;
  1467 		    case 11: /* FCNVDS DRn, FPUL */
  1468 			if( ! IS_FPU_DOUBLESIZE() )
  1469 			    FPULf = (float)DRN(ir);
  1470 			break;
  1471 		    case 14:/* FIPR    FVm, FVn */
  1472 			/* NO-OP when PR=1 */
  1473 			break;
  1474 		    case 15:
  1475 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1476 			    /* NO-OP when PR=1 */
  1477 			    break;
  1479 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */	
  1480 			    /* NO-OP when PR=1 */
  1481 			    break;
  1483 			else if( ir == 0xFBFD ) {
  1484 			    /* FRCHG   */
  1485 			    sh4r.fpscr ^= FPSCR_FR;
  1486 			    break;
  1488 			else if( ir == 0xF3FD ) {
  1489 			    /* FSCHG   */
  1490 			    sh4r.fpscr ^= FPSCR_SZ;
  1491 			    break;
  1493 		    default: UNDEF(ir);
  1495                     break;
  1496                 case 14:/* FMAC    FR0, FRm, FRn */
  1497                     DRN(ir) += DRM(ir)*DR0;
  1498                     break;
  1499                 default: UNDEF(ir);
  1501 	    } else { /* Single precision */
  1502 		switch( ir&0x000F ) {
  1503                 case 0: /* FADD    FRm, FRn */
  1504                     FRN(ir) += FRM(ir);
  1505                     break;
  1506                 case 1: /* FSUB    FRm, FRn */
  1507                     FRN(ir) -= FRM(ir);
  1508                     break;
  1509                 case 2: /* FMUL    FRm, FRn */
  1510                     FRN(ir) = FRN(ir) * FRM(ir);
  1511                     break;
  1512                 case 3: /* FDIV    FRm, FRn */
  1513                     FRN(ir) = FRN(ir) / FRM(ir);
  1514                     break;
  1515                 case 4: /* FCMP/EQ FRm, FRn */
  1516                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1517                     break;
  1518                 case 5: /* FCMP/GT FRm, FRn */
  1519                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1520                     break;
  1521                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1522                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1523                     break;
  1524                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1525                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1526                     break;
  1527                 case 8: /* FMOV.S  [Rm], FRn */
  1528                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1529                     break;
  1530                 case 9: /* FMOV.S  [Rm++], FRn */
  1531                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1532                     RM(ir) += FP_WIDTH;
  1533                     break;
  1534                 case 10:/* FMOV.S  FRm, [Rn] */
  1535                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1536                     break;
  1537                 case 11:/* FMOV.S  FRm, [--Rn] */
  1538                     RN(ir) -= FP_WIDTH;
  1539                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1540                     break;
  1541                 case 12:/* FMOV    FRm, FRn */
  1542 		    if( IS_FPU_DOUBLESIZE() )
  1543 			DRN(ir) = DRM(ir);
  1544 		    else
  1545 			FRN(ir) = FRM(ir);
  1546                     break;
  1547                 case 13:
  1548                     switch( (ir&0x00F0) >> 4 ) {
  1549 		    case 0: /* FSTS    FPUL, FRn */
  1550 			FRN(ir) = FPULf;
  1551 			break;
  1552 		    case 1: /* FLDS    FRn,FPUL */
  1553 			FPULf = FRN(ir);
  1554 			break;
  1555 		    case 2: /* FLOAT   FPUL, FRn */
  1556 			FRN(ir) = (float)FPULi;
  1557 			break;
  1558 		    case 3: /* FTRC    FRn, FPUL */
  1559 			ftmp = FRN(ir);
  1560 			if( ftmp >= MAX_INTF )
  1561 			    FPULi = MAX_INT;
  1562 			else if( ftmp <= MIN_INTF )
  1563 			    FPULi = MIN_INT;
  1564 			else
  1565 			    FPULi = (int32_t)ftmp;
  1566 			break;
  1567 		    case 4: /* FNEG    FRn */
  1568 			FRN(ir) = -FRN(ir);
  1569 			break;
  1570 		    case 5: /* FABS    FRn */
  1571 			FRN(ir) = fabsf(FRN(ir));
  1572 			break;
  1573 		    case 6: /* FSQRT   FRn */
  1574 			FRN(ir) = sqrtf(FRN(ir));
  1575 			break;
  1576 		    case 7: /* FSRRA FRn */
  1577 			FRN(ir) = 1.0/sqrtf(FRN(ir));
  1578 			break;
  1579 		    case 8: /* FLDI0   FRn */
  1580 			FRN(ir) = 0.0;
  1581 			break;
  1582 		    case 9: /* FLDI1   FRn */
  1583 			FRN(ir) = 1.0;
  1584 			break;
  1585 		    case 10: /* FCNVSD FPUL, DRn */
  1586 			break;
  1587 		    case 11: /* FCNVDS DRn, FPUL */
  1588 			break;
  1589 		    case 14:/* FIPR    FVm, FVn */
  1590                             /* FIXME: This is not going to be entirely accurate
  1591                              * as the SH4 instruction is less precise. Also
  1592                              * need to check for 0s and infinities.
  1593                              */
  1595                             int tmp2 = FVN(ir);
  1596                             tmp = FVM(ir);
  1597                             FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1598                                 FR(tmp+1)*FR(tmp2+1) +
  1599                                 FR(tmp+2)*FR(tmp2+2) +
  1600                                 FR(tmp+3)*FR(tmp2+3);
  1601                             break;
  1603 		    case 15:
  1604 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1605 			    tmp = FVN(ir);
  1606 			    float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  1607 			    FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
  1608 				XF(8)*fv[2] + XF(12)*fv[3];
  1609 			    FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
  1610 				XF(9)*fv[2] + XF(13)*fv[3];
  1611 			    FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
  1612 				XF(10)*fv[2] + XF(14)*fv[3];
  1613 			    FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
  1614 				XF(11)*fv[2] + XF(15)*fv[3];
  1615 			    break;
  1617 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1618 			    float angle = (((float)(short)(FPULi>>16)) +
  1619 					   (((float)(FPULi&0xFFFF))/65536.0)) *
  1620 				2 * M_PI;
  1621 			    int reg = FRNn(ir);
  1622 			    FR(reg) = sinf(angle);
  1623 			    FR(reg+1) = cosf(angle);
  1624 			    break;
  1626 			else if( ir == 0xFBFD ) {
  1627 			    /* FRCHG   */
  1628 			    sh4r.fpscr ^= FPSCR_FR;
  1629 			    break;
  1631 			else if( ir == 0xF3FD ) {
  1632 			    /* FSCHG   */
  1633 			    sh4r.fpscr ^= FPSCR_SZ;
  1634 			    break;
  1636 		    default: UNDEF(ir);
  1638                     break;
  1639                 case 14:/* FMAC    FR0, FRm, FRn */
  1640                     FRN(ir) += FRM(ir)*FR0;
  1641                     break;
  1642                 default: UNDEF(ir);
  1645 	    break;
  1647     sh4r.pc = sh4r.new_pc;
  1648     sh4r.new_pc += 2;
  1649     sh4r.in_delay_slot = 0;
.