2 * $Id: sh4core.c,v 1.35 2006-12-19 09:54:03 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 /* CPU-generated exception code/vector pairs */
38 #define EXC_POWER_RESET 0x000 /* vector special */
39 #define EXC_MANUAL_RESET 0x020
40 #define EXC_READ_ADDR_ERR 0x0E0
41 #define EXC_WRITE_ADDR_ERR 0x100
42 #define EXC_SLOT_ILLEGAL 0x1A0
43 #define EXC_ILLEGAL 0x180
44 #define EXC_TRAP 0x160
45 #define EXC_FPDISABLE 0x800
46 #define EXC_SLOT_FPDISABLE 0x820
48 #define EXV_EXCEPTION 0x100 /* General exception vector */
49 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
50 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
52 /********************** SH4 Module Definition ****************************/
54 void sh4_init( void );
55 void sh4_reset( void );
56 uint32_t sh4_run_slice( uint32_t );
57 void sh4_start( void );
58 void sh4_stop( void );
59 void sh4_save_state( FILE *f );
60 int sh4_load_state( FILE *f );
62 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
63 NULL, sh4_run_slice, sh4_stop,
64 sh4_save_state, sh4_load_state };
66 struct sh4_registers sh4r;
70 register_io_regions( mmio_list_sh4mmio );
77 /* zero everything out, for the sake of having a consistent state. */
78 memset( &sh4r, 0, sizeof(sh4r) );
80 /* Resume running if we were halted */
81 sh4r.sh4_state = SH4_STATE_RUNNING;
84 sh4r.new_pc= 0xA0000002;
85 sh4r.vbr = 0x00000000;
86 sh4r.fpscr = 0x00040001;
89 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
90 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
92 /* Peripheral modules */
98 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
99 static int sh4_breakpoint_count = 0;
100 static uint16_t *sh4_icache = NULL;
101 static uint32_t sh4_icache_addr = 0;
103 void sh4_set_breakpoint( uint32_t pc, int type )
105 sh4_breakpoints[sh4_breakpoint_count].address = pc;
106 sh4_breakpoints[sh4_breakpoint_count].type = type;
107 sh4_breakpoint_count++;
110 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
114 for( i=0; i<sh4_breakpoint_count; i++ ) {
115 if( sh4_breakpoints[i].address == pc &&
116 sh4_breakpoints[i].type == type ) {
117 while( ++i < sh4_breakpoint_count ) {
118 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
119 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
121 sh4_breakpoint_count--;
128 int sh4_get_breakpoint( uint32_t pc )
131 for( i=0; i<sh4_breakpoint_count; i++ ) {
132 if( sh4_breakpoints[i].address == pc )
133 return sh4_breakpoints[i].type;
138 uint32_t sh4_run_slice( uint32_t nanosecs )
140 int target = sh4r.icount + nanosecs / sh4_cpu_period;
141 int start = sh4r.icount;
144 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
145 if( sh4r.int_pending != 0 )
146 sh4r.sh4_state = SH4_STATE_RUNNING;;
149 if( sh4_breakpoint_count == 0 ) {
150 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
151 if( !sh4_execute_instruction() ) {
157 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
158 if( !sh4_execute_instruction() )
160 #ifdef ENABLE_DEBUG_MODE
161 for( i=0; i<sh4_breakpoint_count; i++ ) {
162 if( sh4_breakpoints[i].address == sh4r.pc ) {
166 if( i != sh4_breakpoint_count ) {
168 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
169 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
176 /* If we aborted early, but the cpu is still technically running,
177 * we're doing a hard abort - cut the timeslice back to what we
180 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
181 nanosecs = sh4r.slice_cycle;
183 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
184 TMU_run_slice( nanosecs );
185 SCIF_run_slice( nanosecs );
187 sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
196 void sh4_save_state( FILE *f )
198 fwrite( &sh4r, sizeof(sh4r), 1, f );
199 INTC_save_state( f );
201 SCIF_save_state( f );
204 int sh4_load_state( FILE * f )
206 fread( &sh4r, sizeof(sh4r), 1, f );
207 INTC_load_state( f );
209 return SCIF_load_state( f );
212 /********************** SH4 emulation core ****************************/
214 void sh4_set_pc( int pc )
220 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
221 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
223 #if(SH4_CALLTRACE == 1)
224 #define MAX_CALLSTACK 32
225 static struct call_stack {
227 sh4addr_t target_addr;
228 sh4addr_t stack_pointer;
229 } call_stack[MAX_CALLSTACK];
231 static int call_stack_depth = 0;
232 int sh4_call_trace_on = 0;
234 static inline trace_call( sh4addr_t source, sh4addr_t dest )
236 if( call_stack_depth < MAX_CALLSTACK ) {
237 call_stack[call_stack_depth].call_addr = source;
238 call_stack[call_stack_depth].target_addr = dest;
239 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
244 static inline trace_return( sh4addr_t source, sh4addr_t dest )
246 if( call_stack_depth > 0 ) {
251 void fprint_stack_trace( FILE *f )
253 int i = call_stack_depth -1;
254 if( i >= MAX_CALLSTACK )
255 i = MAX_CALLSTACK - 1;
256 for( ; i >= 0; i-- ) {
257 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
258 (call_stack_depth - i), call_stack[i].call_addr,
259 call_stack[i].target_addr, call_stack[i].stack_pointer );
263 #define TRACE_CALL( source, dest ) trace_call(source, dest)
264 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
266 #define TRACE_CALL( dest, rts )
267 #define TRACE_RETURN( source, dest )
270 #define RAISE( x, v ) do{ \
271 if( sh4r.vbr == 0 ) { \
272 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
273 dreamcast_stop(); return FALSE; \
275 sh4r.spc = sh4r.pc; \
276 sh4r.ssr = sh4_read_sr(); \
277 sh4r.sgr = sh4r.r[15]; \
278 MMIO_WRITE(MMU,EXPEVT,x); \
279 sh4r.pc = sh4r.vbr + v; \
280 sh4r.new_pc = sh4r.pc + 2; \
281 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
282 if( sh4r.in_delay_slot ) { \
283 sh4r.in_delay_slot = 0; \
287 return TRUE; } while(0)
289 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
290 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
291 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
292 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
293 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
294 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
296 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
298 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
299 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
301 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
302 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
303 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
304 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
305 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
307 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE )
308 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
309 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
311 static void sh4_switch_banks( )
315 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
316 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
317 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
320 static void sh4_load_sr( uint32_t newval )
322 if( (newval ^ sh4r.sr) & SR_RB )
325 sh4r.t = (newval&SR_T) ? 1 : 0;
326 sh4r.s = (newval&SR_S) ? 1 : 0;
327 sh4r.m = (newval&SR_M) ? 1 : 0;
328 sh4r.q = (newval&SR_Q) ? 1 : 0;
332 static void sh4_write_float( uint32_t addr, int reg )
334 if( IS_FPU_DOUBLESIZE() ) {
336 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
337 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
339 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
340 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
343 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
347 static void sh4_read_float( uint32_t addr, int reg )
349 if( IS_FPU_DOUBLESIZE() ) {
351 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
352 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
354 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
355 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
358 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
362 static uint32_t sh4_read_sr( void )
364 /* synchronize sh4r.sr with the various bitflags */
365 sh4r.sr &= SR_MQSTMASK;
366 if( sh4r.t ) sh4r.sr |= SR_T;
367 if( sh4r.s ) sh4r.sr |= SR_S;
368 if( sh4r.m ) sh4r.sr |= SR_M;
369 if( sh4r.q ) sh4r.sr |= SR_Q;
374 * Raise a general CPU exception for the specified exception code.
375 * (NOT for TRAPA or TLB exceptions)
377 gboolean sh4_raise_exception( int code )
379 RAISE( code, EXV_EXCEPTION );
382 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
383 if( sh4r.in_delay_slot ) {
384 return sh4_raise_exception(slot_code);
386 return sh4_raise_exception(normal_code);
390 gboolean sh4_raise_tlb_exception( int code )
392 RAISE( code, EXV_TLBMISS );
395 static void sh4_accept_interrupt( void )
397 uint32_t code = intc_accept_interrupt();
398 sh4r.ssr = sh4_read_sr();
400 sh4r.sgr = sh4r.r[15];
401 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
402 MMIO_WRITE( MMU, INTEVT, code );
403 sh4r.pc = sh4r.vbr + 0x600;
404 sh4r.new_pc = sh4r.pc + 2;
405 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
408 gboolean sh4_execute_instruction( void )
420 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
421 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
422 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
423 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
424 #define DISP8(ir) (ir&0x00FF)
425 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
426 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
427 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
428 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
429 #define FRNn(ir) ((ir&0x0F00)>>8)
430 #define FRMn(ir) ((ir&0x00F0)>>4)
431 #define DRNn(ir) ((ir&0x0E00)>>9)
432 #define DRMn(ir) ((ir&0x00E0)>>5)
433 #define FVN(ir) ((ir&0x0C00)>>8)
434 #define FVM(ir) ((ir&0x0300)>>6)
435 #define FRN(ir) FR(FRNn(ir))
436 #define FRM(ir) FR(FRMn(ir))
437 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
438 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
439 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
440 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
441 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
442 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
443 #define FPULf *((float *)&sh4r.fpul)
444 #define FPULi (sh4r.fpul)
446 if( SH4_INT_PENDING() )
447 sh4_accept_interrupt();
450 if( pc > 0xFFFFFF00 ) {
452 syscall_invoke( pc );
453 sh4r.in_delay_slot = 0;
454 pc = sh4r.pc = sh4r.pr;
455 sh4r.new_pc = sh4r.pc + 2;
459 /* Read instruction */
460 uint32_t pageaddr = pc >> 12;
461 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
462 ir = sh4_icache[(pc&0xFFF)>>1];
464 sh4_icache = (uint16_t *)mem_get_page(pc);
465 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
466 /* If someone's actually been so daft as to try to execute out of an IO
467 * region, fallback on the full-blown memory read
470 ir = MEM_READ_WORD(pc);
472 sh4_icache_addr = pageaddr;
473 ir = sh4_icache[(pc&0xFFF)>>1];
478 switch( (ir&0xF000)>>12 ) {
479 case 0: /* 0000nnnnmmmmxxxx */
480 switch( ir&0x000F ) {
482 switch( (ir&0x00F0)>>4 ) {
483 case 0: /* STC SR, Rn */
485 RN(ir) = sh4_read_sr();
487 case 1: /* STC GBR, Rn */
490 case 2: /* STC VBR, Rn */
494 case 3: /* STC SSR, Rn */
498 case 4: /* STC SPC, Rn */
502 case 8: case 9: case 10: case 11: case 12: case 13:
503 case 14: case 15:/* STC Rm_bank, Rn */
505 RN(ir) = RN_BANK(ir);
511 switch( (ir&0x00F0)>>4 ) {
512 case 0: /* BSRF Rn */
514 CHECKDEST( pc + 4 + RN(ir) );
515 sh4r.in_delay_slot = 1;
516 sh4r.pr = sh4r.pc + 4;
517 sh4r.pc = sh4r.new_pc;
518 sh4r.new_pc = pc + 4 + RN(ir);
519 TRACE_CALL( pc, sh4r.new_pc );
521 case 2: /* BRAF Rn */
523 CHECKDEST( pc + 4 + RN(ir) );
524 sh4r.in_delay_slot = 1;
525 sh4r.pc = sh4r.new_pc;
526 sh4r.new_pc = pc + 4 + RN(ir);
528 case 8: /* PREF [Rn] */
530 if( (tmp & 0xFC000000) == 0xE0000000 ) {
531 /* Store queue operation */
532 int queue = (tmp&0x20)>>2;
533 int32_t *src = &sh4r.store_queue[queue];
534 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
535 uint32_t target = tmp&0x03FFFFE0 | hi;
536 mem_copy_to_sh4( target, src, 32 );
539 case 9: /* OCBI [Rn] */
540 case 10:/* OCBP [Rn] */
541 case 11:/* OCBWB [Rn] */
544 case 12:/* MOVCA.L R0, [Rn] */
547 MEM_WRITE_LONG( tmp, R0 );
552 case 4: /* MOV.B Rm, [R0 + Rn] */
553 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
555 case 5: /* MOV.W Rm, [R0 + Rn] */
556 CHECKWALIGN16( R0 + RN(ir) );
557 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
559 case 6: /* MOV.L Rm, [R0 + Rn] */
560 CHECKWALIGN32( R0 + RN(ir) );
561 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
563 case 7: /* MUL.L Rm, Rn */
564 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
568 switch( (ir&0x0FF0)>>4 ) {
590 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
592 else if( ir == 0x0019 ) /* DIV0U */
593 sh4r.m = sh4r.q = sh4r.t = 0;
594 else if( ir == 0x0009 )
599 switch( (ir&0x00F0) >> 4 ) {
600 case 0: /* STS MACH, Rn */
601 RN(ir) = sh4r.mac >> 32;
603 case 1: /* STS MACL, Rn */
604 RN(ir) = (uint32_t)sh4r.mac;
606 case 2: /* STS PR, Rn */
609 case 3: /* STC SGR, Rn */
613 case 5:/* STS FPUL, Rn */
616 case 6: /* STS FPSCR, Rn */
619 case 15:/* STC DBR, Rn */
627 switch( (ir&0x0FF0)>>4 ) {
630 CHECKDEST( sh4r.pr );
631 sh4r.in_delay_slot = 1;
632 sh4r.pc = sh4r.new_pc;
633 sh4r.new_pc = sh4r.pr;
634 TRACE_RETURN( pc, sh4r.new_pc );
637 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
638 sh4r.sh4_state = SH4_STATE_STANDBY;
640 sh4r.sh4_state = SH4_STATE_SLEEP;
642 return FALSE; /* Halt CPU */
645 CHECKDEST( sh4r.spc );
647 sh4r.in_delay_slot = 1;
648 sh4r.pc = sh4r.new_pc;
649 sh4r.new_pc = sh4r.spc;
650 sh4_load_sr( sh4r.ssr );
655 case 12:/* MOV.B [R0+R%d], R%d */
656 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
658 case 13:/* MOV.W [R0+R%d], R%d */
659 CHECKRALIGN16( R0 + RM(ir) );
660 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
662 case 14:/* MOV.L [R0+R%d], R%d */
663 CHECKRALIGN32( R0 + RM(ir) );
664 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
666 case 15:/* MAC.L [Rm++], [Rn++] */
667 CHECKRALIGN32( RM(ir) );
668 CHECKRALIGN32( RN(ir) );
669 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
670 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
672 /* 48-bit Saturation. Yuch */
673 tmpl += SIGNEXT48(sh4r.mac);
674 if( tmpl < 0xFFFF800000000000LL )
675 tmpl = 0xFFFF800000000000LL;
676 else if( tmpl > 0x00007FFFFFFFFFFFLL )
677 tmpl = 0x00007FFFFFFFFFFFLL;
678 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
679 (tmpl&0x0000FFFFFFFFFFFFLL);
680 } else sh4r.mac = tmpl;
689 case 1: /* 0001nnnnmmmmdddd */
690 /* MOV.L Rm, [Rn + disp4*4] */
691 tmp = RN(ir) + (DISP4(ir)<<2);
692 CHECKWALIGN32( tmp );
693 MEM_WRITE_LONG( tmp, RM(ir) );
695 case 2: /* 0010nnnnmmmmxxxx */
696 switch( ir&0x000F ) {
697 case 0: /* MOV.B Rm, [Rn] */
698 MEM_WRITE_BYTE( RN(ir), RM(ir) );
700 case 1: /* MOV.W Rm, [Rn] */
701 CHECKWALIGN16( RN(ir) );
702 MEM_WRITE_WORD( RN(ir), RM(ir) );
704 case 2: /* MOV.L Rm, [Rn] */
705 CHECKWALIGN32( RN(ir) );
706 MEM_WRITE_LONG( RN(ir), RM(ir) );
710 case 4: /* MOV.B Rm, [--Rn] */
712 MEM_WRITE_BYTE( RN(ir), RM(ir) );
714 case 5: /* MOV.W Rm, [--Rn] */
716 CHECKWALIGN16( RN(ir) );
717 MEM_WRITE_WORD( RN(ir), RM(ir) );
719 case 6: /* MOV.L Rm, [--Rn] */
721 CHECKWALIGN32( RN(ir) );
722 MEM_WRITE_LONG( RN(ir), RM(ir) );
724 case 7: /* DIV0S Rm, Rn */
727 sh4r.t = sh4r.q ^ sh4r.m;
729 case 8: /* TST Rm, Rn */
730 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
732 case 9: /* AND Rm, Rn */
735 case 10:/* XOR Rm, Rn */
738 case 11:/* OR Rm, Rn */
741 case 12:/* CMP/STR Rm, Rn */
742 /* set T = 1 if any byte in RM & RN is the same */
743 tmp = RM(ir) ^ RN(ir);
744 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
745 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
747 case 13:/* XTRCT Rm, Rn */
748 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
750 case 14:/* MULU.W Rm, Rn */
751 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
752 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
754 case 15:/* MULS.W Rm, Rn */
755 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
756 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
760 case 3: /* 0011nnnnmmmmxxxx */
761 switch( ir&0x000F ) {
762 case 0: /* CMP/EQ Rm, Rn */
763 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
765 case 2: /* CMP/HS Rm, Rn */
766 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
768 case 3: /* CMP/GE Rm, Rn */
769 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
771 case 4: { /* DIV1 Rm, Rn */
772 /* This is just from the sh4p manual with some
773 * simplifications (someone want to check it's correct? :)
774 * Why they couldn't just provide a real DIV instruction...
775 * Please oh please let the translator batch these things
776 * up into a single DIV... */
777 uint32_t tmp0, tmp1, tmp2, dir;
779 dir = sh4r.q ^ sh4r.m;
780 sh4r.q = (RN(ir) >> 31);
782 RN(ir) = (RN(ir) << 1) | sh4r.t;
786 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
789 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
791 sh4r.q ^= sh4r.m ^ tmp1;
792 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
794 case 5: /* DMULU.L Rm, Rn */
795 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
797 case 6: /* CMP/HI Rm, Rn */
798 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
800 case 7: /* CMP/GT Rm, Rn */
801 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
803 case 8: /* SUB Rm, Rn */
806 case 10:/* SUBC Rm, Rn */
808 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
809 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
811 case 11:/* SUBV Rm, Rn */
814 case 12:/* ADD Rm, Rn */
817 case 13:/* DMULS.L Rm, Rn */
818 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
820 case 14:/* ADDC Rm, Rn */
822 RN(ir) += RM(ir) + sh4r.t;
823 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
825 case 15:/* ADDV Rm, Rn */
826 tmp = RN(ir) + RM(ir);
827 sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
833 case 4: /* 0100nnnnxxxxxxxx */
834 switch( ir&0x00FF ) {
835 case 0x00: /* SHLL Rn */
836 sh4r.t = RN(ir) >> 31;
839 case 0x01: /* SHLR Rn */
840 sh4r.t = RN(ir) & 0x00000001;
843 case 0x02: /* STS.L MACH, [--Rn] */
845 CHECKWALIGN32( RN(ir) );
846 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
848 case 0x03: /* STC.L SR, [--Rn] */
851 CHECKWALIGN32( RN(ir) );
852 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
854 case 0x04: /* ROTL Rn */
855 sh4r.t = RN(ir) >> 31;
859 case 0x05: /* ROTR Rn */
860 sh4r.t = RN(ir) & 0x00000001;
862 RN(ir) |= (sh4r.t << 31);
864 case 0x06: /* LDS.L [Rn++], MACH */
865 CHECKRALIGN32( RN(ir) );
866 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
867 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
870 case 0x07: /* LDC.L [Rn++], SR */
873 CHECKWALIGN32( RN(ir) );
874 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
877 case 0x08: /* SHLL2 Rn */
880 case 0x09: /* SHLR2 Rn */
883 case 0x0A: /* LDS Rn, MACH */
884 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
885 (((uint64_t)RN(ir))<<32);
887 case 0x0B: /* JSR [Rn] */
890 sh4r.in_delay_slot = 1;
891 sh4r.pc = sh4r.new_pc;
892 sh4r.new_pc = RN(ir);
894 TRACE_CALL( pc, sh4r.new_pc );
896 case 0x0E: /* LDC Rn, SR */
899 sh4_load_sr( RN(ir) );
901 case 0x10: /* DT Rn */
903 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
905 case 0x11: /* CMP/PZ Rn */
906 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
908 case 0x12: /* STS.L MACL, [--Rn] */
910 CHECKWALIGN32( RN(ir) );
911 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
913 case 0x13: /* STC.L GBR, [--Rn] */
915 CHECKWALIGN32( RN(ir) );
916 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
918 case 0x15: /* CMP/PL Rn */
919 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
921 case 0x16: /* LDS.L [Rn++], MACL */
922 CHECKRALIGN32( RN(ir) );
923 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
924 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
927 case 0x17: /* LDC.L [Rn++], GBR */
928 CHECKRALIGN32( RN(ir) );
929 sh4r.gbr = MEM_READ_LONG(RN(ir));
932 case 0x18: /* SHLL8 Rn */
935 case 0x19: /* SHLR8 Rn */
938 case 0x1A: /* LDS Rn, MACL */
939 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
940 (uint64_t)((uint32_t)(RN(ir)));
942 case 0x1B: /* TAS.B [Rn] */
943 tmp = MEM_READ_BYTE( RN(ir) );
944 sh4r.t = ( tmp == 0 ? 1 : 0 );
945 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
947 case 0x1E: /* LDC Rn, GBR */
950 case 0x20: /* SHAL Rn */
951 sh4r.t = RN(ir) >> 31;
954 case 0x21: /* SHAR Rn */
955 sh4r.t = RN(ir) & 0x00000001;
956 RN(ir) = ((int32_t)RN(ir)) >> 1;
958 case 0x22: /* STS.L PR, [--Rn] */
960 CHECKWALIGN32( RN(ir) );
961 MEM_WRITE_LONG( RN(ir), sh4r.pr );
963 case 0x23: /* STC.L VBR, [--Rn] */
966 CHECKWALIGN32( RN(ir) );
967 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
969 case 0x24: /* ROTCL Rn */
975 case 0x25: /* ROTCR Rn */
976 tmp = RN(ir) & 0x00000001;
978 RN(ir) |= (sh4r.t << 31 );
981 case 0x26: /* LDS.L [Rn++], PR */
982 CHECKRALIGN32( RN(ir) );
983 sh4r.pr = MEM_READ_LONG( RN(ir) );
986 case 0x27: /* LDC.L [Rn++], VBR */
988 CHECKRALIGN32( RN(ir) );
989 sh4r.vbr = MEM_READ_LONG(RN(ir));
992 case 0x28: /* SHLL16 Rn */
995 case 0x29: /* SHLR16 Rn */
998 case 0x2A: /* LDS Rn, PR */
1001 case 0x2B: /* JMP [Rn] */
1002 CHECKDEST( RN(ir) );
1004 sh4r.in_delay_slot = 1;
1005 sh4r.pc = sh4r.new_pc;
1006 sh4r.new_pc = RN(ir);
1008 case 0x2E: /* LDC Rn, VBR */
1012 case 0x32: /* STC.L SGR, [--Rn] */
1015 CHECKWALIGN32( RN(ir) );
1016 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
1018 case 0x33: /* STC.L SSR, [--Rn] */
1021 CHECKWALIGN32( RN(ir) );
1022 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
1024 case 0x37: /* LDC.L [Rn++], SSR */
1026 CHECKRALIGN32( RN(ir) );
1027 sh4r.ssr = MEM_READ_LONG(RN(ir));
1030 case 0x3E: /* LDC Rn, SSR */
1034 case 0x43: /* STC.L SPC, [--Rn] */
1037 CHECKWALIGN32( RN(ir) );
1038 MEM_WRITE_LONG( RN(ir), sh4r.spc );
1040 case 0x47: /* LDC.L [Rn++], SPC */
1042 CHECKRALIGN32( RN(ir) );
1043 sh4r.spc = MEM_READ_LONG(RN(ir));
1046 case 0x4E: /* LDC Rn, SPC */
1050 case 0x52: /* STS.L FPUL, [--Rn] */
1052 CHECKWALIGN32( RN(ir) );
1053 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
1055 case 0x56: /* LDS.L [Rn++], FPUL */
1056 CHECKRALIGN32( RN(ir) );
1057 sh4r.fpul = MEM_READ_LONG(RN(ir));
1060 case 0x5A: /* LDS Rn, FPUL */
1063 case 0x62: /* STS.L FPSCR, [--Rn] */
1065 CHECKWALIGN32( RN(ir) );
1066 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
1068 case 0x66: /* LDS.L [Rn++], FPSCR */
1069 CHECKRALIGN32( RN(ir) );
1070 sh4r.fpscr = MEM_READ_LONG(RN(ir));
1073 case 0x6A: /* LDS Rn, FPSCR */
1074 sh4r.fpscr = RN(ir);
1076 case 0xF2: /* STC.L DBR, [--Rn] */
1079 CHECKWALIGN32( RN(ir) );
1080 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
1082 case 0xF6: /* LDC.L [Rn++], DBR */
1084 CHECKRALIGN32( RN(ir) );
1085 sh4r.dbr = MEM_READ_LONG(RN(ir));
1088 case 0xFA: /* LDC Rn, DBR */
1092 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
1093 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
1096 CHECKWALIGN32( RN(ir) );
1097 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
1099 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
1100 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
1102 CHECKRALIGN32( RN(ir) );
1103 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
1106 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
1107 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
1109 RN_BANK(ir) = RM(ir);
1112 if( (ir&0x000F) == 0x0F ) {
1113 /* MAC.W [Rm++], [Rn++] */
1114 CHECKRALIGN16( RN(ir) );
1115 CHECKRALIGN16( RM(ir) );
1116 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
1117 SIGNEXT16(MEM_READ_WORD(RN(ir)));
1121 } else sh4r.mac += SIGNEXT32(tmp);
1124 } else if( (ir&0x000F) == 0x0C ) {
1127 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1128 else if( (tmp & 0x1F) == 0 )
1129 RN(ir) = ((int32_t)RN(ir)) >> 31;
1131 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
1132 } else if( (ir&0x000F) == 0x0D ) {
1135 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1136 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
1137 else RN(ir) >>= (((~tmp) & 0x1F)+1);
1141 case 5: /* 0101nnnnmmmmdddd */
1142 /* MOV.L [Rm + disp4*4], Rn */
1143 tmp = RM(ir) + (DISP4(ir)<<2);
1144 CHECKRALIGN32( tmp );
1145 RN(ir) = MEM_READ_LONG( tmp );
1147 case 6: /* 0110xxxxxxxxxxxx */
1148 switch( ir&0x000f ) {
1149 case 0: /* MOV.B [Rm], Rn */
1150 RN(ir) = MEM_READ_BYTE( RM(ir) );
1152 case 1: /* MOV.W [Rm], Rn */
1153 CHECKRALIGN16( RM(ir) );
1154 RN(ir) = MEM_READ_WORD( RM(ir) );
1156 case 2: /* MOV.L [Rm], Rn */
1157 CHECKRALIGN32( RM(ir) );
1158 RN(ir) = MEM_READ_LONG( RM(ir) );
1160 case 3: /* MOV Rm, Rn */
1163 case 4: /* MOV.B [Rm++], Rn */
1164 RN(ir) = MEM_READ_BYTE( RM(ir) );
1167 case 5: /* MOV.W [Rm++], Rn */
1168 CHECKRALIGN16( RM(ir) );
1169 RN(ir) = MEM_READ_WORD( RM(ir) );
1172 case 6: /* MOV.L [Rm++], Rn */
1173 CHECKRALIGN32( RM(ir) );
1174 RN(ir) = MEM_READ_LONG( RM(ir) );
1177 case 7: /* NOT Rm, Rn */
1180 case 8: /* SWAP.B Rm, Rn */
1181 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
1182 ((RM(ir)&0x000000FF)<<8);
1184 case 9: /* SWAP.W Rm, Rn */
1185 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
1187 case 10:/* NEGC Rm, Rn */
1189 RN(ir) = tmp - sh4r.t;
1190 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
1192 case 11:/* NEG Rm, Rn */
1193 RN(ir) = 0 - RM(ir);
1195 case 12:/* EXTU.B Rm, Rn */
1196 RN(ir) = RM(ir)&0x000000FF;
1198 case 13:/* EXTU.W Rm, Rn */
1199 RN(ir) = RM(ir)&0x0000FFFF;
1201 case 14:/* EXTS.B Rm, Rn */
1202 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
1204 case 15:/* EXTS.W Rm, Rn */
1205 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
1209 case 7: /* 0111nnnniiiiiiii */
1213 case 8: /* 1000xxxxxxxxxxxx */
1214 switch( (ir&0x0F00) >> 8 ) {
1215 case 0: /* MOV.B R0, [Rm + disp4] */
1216 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
1218 case 1: /* MOV.W R0, [Rm + disp4*2] */
1219 tmp = RM(ir) + (DISP4(ir)<<1);
1220 CHECKWALIGN16( tmp );
1221 MEM_WRITE_WORD( tmp, R0 );
1223 case 4: /* MOV.B [Rm + disp4], R0 */
1224 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
1226 case 5: /* MOV.W [Rm + disp4*2], R0 */
1227 tmp = RM(ir) + (DISP4(ir)<<1);
1228 CHECKRALIGN16( tmp );
1229 R0 = MEM_READ_WORD( tmp );
1231 case 8: /* CMP/EQ imm, R0 */
1232 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
1234 case 9: /* BT disp8 */
1237 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1238 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1239 sh4r.new_pc = sh4r.pc + 2;
1243 case 11:/* BF disp8 */
1246 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1247 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1248 sh4r.new_pc = sh4r.pc + 2;
1252 case 13:/* BT/S disp8 */
1255 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1256 sh4r.in_delay_slot = 1;
1257 sh4r.pc = sh4r.new_pc;
1258 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1259 sh4r.in_delay_slot = 1;
1263 case 15:/* BF/S disp8 */
1266 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1267 sh4r.in_delay_slot = 1;
1268 sh4r.pc = sh4r.new_pc;
1269 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1276 case 9: /* 1001xxxxxxxxxxxx */
1277 /* MOV.W [disp8*2 + pc + 4], Rn */
1279 tmp = pc + 4 + (DISP8(ir)<<1);
1280 RN(ir) = MEM_READ_WORD( tmp );
1282 case 10:/* 1010dddddddddddd */
1285 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
1286 sh4r.in_delay_slot = 1;
1287 sh4r.pc = sh4r.new_pc;
1288 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1290 case 11:/* 1011dddddddddddd */
1292 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
1294 sh4r.in_delay_slot = 1;
1296 sh4r.pc = sh4r.new_pc;
1297 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1298 TRACE_CALL( pc, sh4r.new_pc );
1300 case 12:/* 1100xxxxdddddddd */
1301 switch( (ir&0x0F00)>>8 ) {
1302 case 0: /* MOV.B R0, [GBR + disp8] */
1303 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1305 case 1: /* MOV.W R0, [GBR + disp8*2] */
1306 tmp = sh4r.gbr + (DISP8(ir)<<1);
1307 CHECKWALIGN16( tmp );
1308 MEM_WRITE_WORD( tmp, R0 );
1310 case 2: /*MOV.L R0, [GBR + disp8*4] */
1311 tmp = sh4r.gbr + (DISP8(ir)<<2);
1312 CHECKWALIGN32( tmp );
1313 MEM_WRITE_LONG( tmp, R0 );
1315 case 3: /* TRAPA imm8 */
1317 MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
1319 sh4_raise_exception( EXC_TRAP );
1321 case 4: /* MOV.B [GBR + disp8], R0 */
1322 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1324 case 5: /* MOV.W [GBR + disp8*2], R0 */
1325 tmp = sh4r.gbr + (DISP8(ir)<<1);
1326 CHECKRALIGN16( tmp );
1327 R0 = MEM_READ_WORD( tmp );
1329 case 6: /* MOV.L [GBR + disp8*4], R0 */
1330 tmp = sh4r.gbr + (DISP8(ir)<<2);
1331 CHECKRALIGN32( tmp );
1332 R0 = MEM_READ_LONG( tmp );
1334 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1336 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1338 case 8: /* TST imm8, R0 */
1339 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1341 case 9: /* AND imm8, R0 */
1344 case 10:/* XOR imm8, R0 */
1347 case 11:/* OR imm8, R0 */
1350 case 12:/* TST.B imm8, [R0+GBR] */
1351 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1353 case 13:/* AND.B imm8, [R0+GBR] */
1354 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1355 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1357 case 14:/* XOR.B imm8, [R0+GBR] */
1358 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1359 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1361 case 15:/* OR.B imm8, [R0+GBR] */
1362 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1363 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1367 case 13:/* 1101nnnndddddddd */
1368 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1370 tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1371 RN(ir) = MEM_READ_LONG( tmp );
1373 case 14:/* 1110nnnniiiiiiii */
1377 case 15:/* 1111xxxxxxxxxxxx */
1379 if( IS_FPU_DOUBLEPREC() ) {
1380 switch( ir&0x000F ) {
1381 case 0: /* FADD FRm, FRn */
1384 case 1: /* FSUB FRm, FRn */
1387 case 2: /* FMUL FRm, FRn */
1388 DRN(ir) = DRN(ir) * DRM(ir);
1390 case 3: /* FDIV FRm, FRn */
1391 DRN(ir) = DRN(ir) / DRM(ir);
1393 case 4: /* FCMP/EQ FRm, FRn */
1394 sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
1396 case 5: /* FCMP/GT FRm, FRn */
1397 sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
1399 case 6: /* FMOV.S [Rm+R0], FRn */
1400 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1402 case 7: /* FMOV.S FRm, [Rn+R0] */
1403 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1405 case 8: /* FMOV.S [Rm], FRn */
1406 MEM_FP_READ( RM(ir), FRNn(ir) );
1408 case 9: /* FMOV.S [Rm++], FRn */
1409 MEM_FP_READ( RM(ir), FRNn(ir) );
1412 case 10:/* FMOV.S FRm, [Rn] */
1413 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1415 case 11:/* FMOV.S FRm, [--Rn] */
1417 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1419 case 12:/* FMOV FRm, FRn */
1420 if( IS_FPU_DOUBLESIZE() )
1426 switch( (ir&0x00F0) >> 4 ) {
1427 case 0: /* FSTS FPUL, FRn */
1430 case 1: /* FLDS FRn,FPUL */
1433 case 2: /* FLOAT FPUL, FRn */
1434 DRN(ir) = (float)FPULi;
1436 case 3: /* FTRC FRn, FPUL */
1438 if( dtmp >= MAX_INTF )
1440 else if( dtmp <= MIN_INTF )
1443 FPULi = (int32_t)dtmp;
1445 case 4: /* FNEG FRn */
1448 case 5: /* FABS FRn */
1449 DRN(ir) = fabs(DRN(ir));
1451 case 6: /* FSQRT FRn */
1452 DRN(ir) = sqrt(DRN(ir));
1454 case 7: /* FSRRA FRn */
1455 /* NO-OP when PR=1 */
1457 case 8: /* FLDI0 FRn */
1460 case 9: /* FLDI1 FRn */
1463 case 10: /* FCNVSD FPUL, DRn */
1464 if( ! IS_FPU_DOUBLESIZE() )
1465 DRN(ir) = (double)FPULf;
1467 case 11: /* FCNVDS DRn, FPUL */
1468 if( ! IS_FPU_DOUBLESIZE() )
1469 FPULf = (float)DRN(ir);
1471 case 14:/* FIPR FVm, FVn */
1472 /* NO-OP when PR=1 */
1475 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1476 /* NO-OP when PR=1 */
1479 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1480 /* NO-OP when PR=1 */
1483 else if( ir == 0xFBFD ) {
1485 sh4r.fpscr ^= FPSCR_FR;
1488 else if( ir == 0xF3FD ) {
1490 sh4r.fpscr ^= FPSCR_SZ;
1496 case 14:/* FMAC FR0, FRm, FRn */
1497 DRN(ir) += DRM(ir)*DR0;
1501 } else { /* Single precision */
1502 switch( ir&0x000F ) {
1503 case 0: /* FADD FRm, FRn */
1506 case 1: /* FSUB FRm, FRn */
1509 case 2: /* FMUL FRm, FRn */
1510 FRN(ir) = FRN(ir) * FRM(ir);
1512 case 3: /* FDIV FRm, FRn */
1513 FRN(ir) = FRN(ir) / FRM(ir);
1515 case 4: /* FCMP/EQ FRm, FRn */
1516 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1518 case 5: /* FCMP/GT FRm, FRn */
1519 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1521 case 6: /* FMOV.S [Rm+R0], FRn */
1522 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1524 case 7: /* FMOV.S FRm, [Rn+R0] */
1525 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1527 case 8: /* FMOV.S [Rm], FRn */
1528 MEM_FP_READ( RM(ir), FRNn(ir) );
1530 case 9: /* FMOV.S [Rm++], FRn */
1531 MEM_FP_READ( RM(ir), FRNn(ir) );
1534 case 10:/* FMOV.S FRm, [Rn] */
1535 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1537 case 11:/* FMOV.S FRm, [--Rn] */
1539 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1541 case 12:/* FMOV FRm, FRn */
1542 if( IS_FPU_DOUBLESIZE() )
1548 switch( (ir&0x00F0) >> 4 ) {
1549 case 0: /* FSTS FPUL, FRn */
1552 case 1: /* FLDS FRn,FPUL */
1555 case 2: /* FLOAT FPUL, FRn */
1556 FRN(ir) = (float)FPULi;
1558 case 3: /* FTRC FRn, FPUL */
1560 if( ftmp >= MAX_INTF )
1562 else if( ftmp <= MIN_INTF )
1565 FPULi = (int32_t)ftmp;
1567 case 4: /* FNEG FRn */
1570 case 5: /* FABS FRn */
1571 FRN(ir) = fabsf(FRN(ir));
1573 case 6: /* FSQRT FRn */
1574 FRN(ir) = sqrtf(FRN(ir));
1576 case 7: /* FSRRA FRn */
1577 FRN(ir) = 1.0/sqrtf(FRN(ir));
1579 case 8: /* FLDI0 FRn */
1582 case 9: /* FLDI1 FRn */
1585 case 10: /* FCNVSD FPUL, DRn */
1587 case 11: /* FCNVDS DRn, FPUL */
1589 case 14:/* FIPR FVm, FVn */
1590 /* FIXME: This is not going to be entirely accurate
1591 * as the SH4 instruction is less precise. Also
1592 * need to check for 0s and infinities.
1597 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1598 FR(tmp+1)*FR(tmp2+1) +
1599 FR(tmp+2)*FR(tmp2+2) +
1600 FR(tmp+3)*FR(tmp2+3);
1604 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1606 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1607 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1608 XF(8)*fv[2] + XF(12)*fv[3];
1609 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1610 XF(9)*fv[2] + XF(13)*fv[3];
1611 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1612 XF(10)*fv[2] + XF(14)*fv[3];
1613 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1614 XF(11)*fv[2] + XF(15)*fv[3];
1617 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1618 float angle = (((float)(short)(FPULi>>16)) +
1619 (((float)(FPULi&0xFFFF))/65536.0)) *
1622 FR(reg) = sinf(angle);
1623 FR(reg+1) = cosf(angle);
1626 else if( ir == 0xFBFD ) {
1628 sh4r.fpscr ^= FPSCR_FR;
1631 else if( ir == 0xF3FD ) {
1633 sh4r.fpscr ^= FPSCR_SZ;
1639 case 14:/* FMAC FR0, FRm, FRn */
1640 FRN(ir) += FRM(ir)*FR0;
1647 sh4r.pc = sh4r.new_pc;
1649 sh4r.in_delay_slot = 0;
.