lxdream 0.9.1| filename | src/asic.c |
| changeset | 100:995e42e96cc9 |
| prev | 94:8d80d9c7cc7d |
| next | 125:49bf45f8210a |
| author | nkeynes |
| date | Wed Feb 15 13:11:50 2006 +0000 (17 years ago) |
| permissions | -rw-r--r-- |
| last change | Split pvr2.c out to separate files for TA and renderer, minor renames change pvrdma to use mem_copy_to_sh4 |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: asic.c,v 1.12 2006-02-15 13:11:42 nkeynes Exp $
3 *
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
5 * and DMA).
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE asic_module
22 #include <assert.h>
23 #include "dream.h"
24 #include "mem.h"
25 #include "sh4/intc.h"
26 #include "sh4/dmac.h"
27 #include "dreamcast.h"
28 #include "maple/maple.h"
29 #include "gdrom/ide.h"
30 #include "asic.h"
31 #define MMIO_IMPL
32 #include "asic.h"
33 /*
34 * Open questions:
35 * 1) Does changing the mask after event occurance result in the
36 * interrupt being delivered immediately?
37 * TODO: Logic diagram of ASIC event/interrupt logic.
38 *
39 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
40 * practically nothing is publicly known...
41 */
43 struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
44 NULL, NULL, NULL };
46 void asic_check_cleared_events( void );
48 void asic_init( void )
49 {
50 register_io_region( &mmio_region_ASIC );
51 register_io_region( &mmio_region_EXTDMA );
52 mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
53 asic_event( EVENT_GDROM_CMD );
54 }
56 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
57 {
58 switch( reg ) {
59 case PIRQ0:
60 case PIRQ1:
61 case PIRQ2:
62 /* Clear any interrupts */
63 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
64 asic_check_cleared_events();
65 break;
66 case MAPLE_STATE:
67 MMIO_WRITE( ASIC, reg, val );
68 if( val & 1 ) {
69 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
70 WARN( "Maple request initiated at %08X, halting", maple_addr );
71 maple_handle_buffer( maple_addr );
72 MMIO_WRITE( ASIC, reg, 0 );
73 }
74 break;
75 case PVRDMACTL: /* Initiate PVR DMA transfer */
76 MMIO_WRITE( ASIC, reg, val );
77 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
78 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
79 if( val & 1 ) {
80 uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
81 uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
82 char *data = alloca( count );
83 uint32_t rcount = DMAC_get_buffer( 2, data, count );
84 if( rcount != count )
85 WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
86 mem_copy_to_sh4( dest_addr, data, rcount );
87 asic_event( EVENT_PVR_DMA );
88 }
89 break;
90 default:
91 MMIO_WRITE( ASIC, reg, val );
92 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
93 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
94 }
95 }
97 int32_t mmio_region_ASIC_read( uint32_t reg )
98 {
99 int32_t val;
100 switch( reg ) {
101 /*
102 case 0x89C:
103 sh4_stop();
104 return 0x000000B;
105 */
106 case PIRQ0:
107 case PIRQ1:
108 case PIRQ2:
109 case IRQA0:
110 case IRQA1:
111 case IRQA2:
112 case IRQB0:
113 case IRQB1:
114 case IRQB2:
115 case IRQC0:
116 case IRQC1:
117 case IRQC2:
118 val = MMIO_READ(ASIC, reg);
119 // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
120 // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
121 return val;
122 case G2STATUS:
123 return 0; /* find out later if there's any cases we actually need to care about */
124 default:
125 val = MMIO_READ(ASIC, reg);
126 WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
127 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
128 return val;
129 }
131 }
133 void asic_event( int event )
134 {
135 int offset = ((event&0x60)>>3);
136 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
138 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
139 intc_raise_interrupt( INT_IRQ13 );
140 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
141 intc_raise_interrupt( INT_IRQ11 );
142 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
143 intc_raise_interrupt( INT_IRQ9 );
144 }
146 void asic_check_cleared_events( )
147 {
148 int i, setA = 0, setB = 0, setC = 0;
149 uint32_t bits;
150 for( i=0; i<3; i++ ) {
151 bits = MMIO_READ( ASIC, PIRQ0 + i );
152 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
153 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
154 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
155 }
156 if( setA == 0 )
157 intc_clear_interrupt( INT_IRQ13 );
158 if( setB == 0 )
159 intc_clear_interrupt( INT_IRQ11 );
160 if( setC == 0 )
161 intc_clear_interrupt( INT_IRQ9 );
162 }
165 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
166 {
167 switch( reg ) {
168 case IDEALTSTATUS: /* Device control */
169 ide_write_control( val );
170 break;
171 case IDEDATA:
172 ide_write_data_pio( val );
173 break;
174 case IDEFEAT:
175 if( ide_can_write_regs() )
176 idereg.feature = (uint8_t)val;
177 break;
178 case IDECOUNT:
179 if( ide_can_write_regs() )
180 idereg.count = (uint8_t)val;
181 break;
182 case IDELBA0:
183 if( ide_can_write_regs() )
184 idereg.lba0 = (uint8_t)val;
185 break;
186 case IDELBA1:
187 if( ide_can_write_regs() )
188 idereg.lba1 = (uint8_t)val;
189 break;
190 case IDELBA2:
191 if( ide_can_write_regs() )
192 idereg.lba2 = (uint8_t)val;
193 break;
194 case IDEDEV:
195 if( ide_can_write_regs() )
196 idereg.device = (uint8_t)val;
197 break;
198 case IDECMD:
199 if( ide_can_write_regs() ) {
200 ide_clear_interrupt();
201 ide_write_command( (uint8_t)val );
202 }
203 break;
204 default:
205 WARN( "EXTDMA write %08X <= %08X", reg, val );
207 MMIO_WRITE( EXTDMA, reg, val );
208 }
209 }
211 MMIO_REGION_READ_FN( EXTDMA, reg )
212 {
213 uint32_t val;
214 switch( reg ) {
215 case IDEALTSTATUS: return idereg.status;
216 case IDEDATA: return ide_read_data_pio( );
217 case IDEFEAT: return idereg.error;
218 case IDECOUNT:return idereg.count;
219 case IDELBA0: return idereg.disc;
220 case IDELBA1: return idereg.lba1;
221 case IDELBA2: return idereg.lba2;
222 case IDEDEV: return idereg.device;
223 case IDECMD:
224 ide_clear_interrupt();
225 return idereg.status;
226 default:
227 val = MMIO_READ( EXTDMA, reg );
228 //DEBUG( "EXTDMA read %08X => %08X", reg, val );
229 return val;
230 }
231 }
.