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filename src/sh4/sh4core.c
changeset 18:9a1b5d75703f
prev16:f383e7640da4
next19:9da7a8e38f9d
author nkeynes
date Thu Dec 15 13:33:14 2005 +0000 (17 years ago)
permissions -rw-r--r--
last change Implement save states
view annotate diff log raw 
     1 #include <math.h>

     2 #include "dream.h"

     3 #include "modules.h"

     4 #include "sh4core.h"

     5 #include "sh4mmio.h"

     6 #include "mem.h"

     7 #include "intc.h"

     8 

     9 void sh4_save( FILE *f );

    10 int sh4_load( FILE *f );

    11 

    12 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 

    13 				       NULL, sh4_stop,

    14 				       sh4_save, sh4_load };

    15 

    16 struct sh4_registers sh4r;

    17 static int running = 0;

    18 

    19 void sh4_init(void)

    20 {

    21     register_io_regions( mmio_list_sh4mmio );

    22     mmu_init();

    23 }

    24 

    25 void sh4_reset(void)

    26 {

    27     sh4r.pc    = 0xA0000000;

    28     sh4r.new_pc= 0xA0000002;

    29     sh4r.vbr   = 0x00000000;

    30     sh4r.fpscr = 0x00040001;

    31     sh4r.sr    = 0x700000F0;

    32     sh4r.icount= 0;

    33     /* Everything else is undefined anyway, so don't bother setting it */

    34     intc_reset();

    35 }

    36 

    37 void sh4_set_pc( int pc )

    38 {

    39     sh4r.pc = pc;

    40     sh4r.new_pc = pc+2;

    41 }

    42 

    43 void sh4_stop(void)

    44 {

    45     running = 0;

    46 }

    47 

    48 void sh4_save( FILE *f )

    49 {

    50     fwrite( &sh4r, sizeof(sh4r), 1, f );

    51     /* Save all additional on-board MMIO state */

    52 }

    53 

    54 int sh4_load( FILE * f )

    55 {

    56     fread( &sh4r, sizeof(sh4r), 1, f );

    57     return 0;

    58 }

    59 

    60 void sh4_run(void)

    61 {

    62     running = 1;

    63     while( running ) {

    64         sh4_execute_instruction();

    65     }

    66 }

    67 

    68 void sh4_runfor(uint32_t count)

    69 {

    70     running = 1;

    71     while( running && count--) {

    72         int pc = sh4r.pc;

    73         sh4_execute_instruction();

    74         /*

    75         if( sh4r.pc == 0x8C0C1636 ||

    76             sh4r.pc == 0x8C0C1634 ) {

    77             WARN( "Branching to %08X from %08X", sh4r.pc, pc );

    78             sh4_stop();

    79             }*/

    80     }

    81 }

    82 

    83 int sh4_isrunning(void)

    84 {

    85     return running;

    86 }

    87 

    88 void sh4_runto( uint32_t target_pc, uint32_t count )

    89 {

    90     running = 1;

    91     while( running && count--) {

    92         sh4_execute_instruction();

    93         if( sh4r.pc == target_pc ) {

    94             running = 0;

    95             break;

    96         }

    97     }

    98 }

    99 

   100 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)

   101 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); return; }while(0)

   102 

   103 #define RAISE( x, v ) do{ \

   104     if( sh4r.vbr == 0 ) { \

   105         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \

   106         sh4_stop(); \

   107     } else { \

   108         sh4r.spc = sh4r.pc + 2; \

   109         sh4r.ssr = sh4_read_sr(); \

   110         sh4r.sgr = sh4r.r[15]; \

   111         MMIO_WRITE(MMU,EXPEVT,x); \

   112         sh4r.pc = sh4r.vbr + v; \

   113         sh4r.new_pc = sh4r.pc + 2; \

   114         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \

   115     } \

   116     return; } while(0)

   117 

   118 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)

   119 #define MEM_READ_WORD( addr ) sh4_read_word(addr)

   120 #define MEM_READ_LONG( addr ) sh4_read_long(addr)

   121 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)

   122 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)

   123 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)

   124 

   125 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \

   126     ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \

   127     ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \

   128 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)

   129 

   130 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \

   131     sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \

   132     sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \

   133 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )

   134 

   135 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)

   136 

   137 #define EXC_POWER_RESET  0x000 /* vector special */

   138 #define EXC_MANUAL_RESET 0x020

   139 #define EXC_SLOT_ILLEGAL 0x1A0

   140 #define EXC_ILLEGAL      0x180

   141 #define EXV_ILLEGAL      0x100

   142 #define EXC_TRAP         0x160

   143 #define EXV_TRAP         0x100

   144 #define EXC_FPDISABLE    0x800

   145 #define EXV_FPDISABLE    0x100

   146 

   147 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )

   148 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )

   149 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )

   150 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }

   151 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }

   152 

   153 static void sh4_switch_banks( )

   154 {

   155     uint32_t tmp[8];

   156 

   157     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );

   158     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );

   159     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );

   160 }

   161 

   162 static void sh4_load_sr( uint32_t newval )

   163 {

   164     if( (newval ^ sh4r.sr) & SR_RB )

   165         sh4_switch_banks();

   166     sh4r.sr = newval;

   167     sh4r.t = (newval&SR_T) ? 1 : 0;

   168     sh4r.s = (newval&SR_S) ? 1 : 0;

   169     sh4r.m = (newval&SR_M) ? 1 : 0;

   170     sh4r.q = (newval&SR_Q) ? 1 : 0;

   171     intc_mask_changed();

   172 }

   173 

   174 static uint32_t sh4_read_sr( void )

   175 {

   176     /* synchronize sh4r.sr with the various bitflags */

   177     sh4r.sr &= SR_MQSTMASK;

   178     if( sh4r.t ) sh4r.sr |= SR_T;

   179     if( sh4r.s ) sh4r.sr |= SR_S;

   180     if( sh4r.m ) sh4r.sr |= SR_M;

   181     if( sh4r.q ) sh4r.sr |= SR_Q;

   182     return sh4r.sr;

   183 }

   184 /* function for external use */

   185 void sh4_raise_exception( int code, int vector )

   186 {

   187     RAISE(code, vector);

   188 }

   189 

   190 static void sh4_accept_interrupt( void )

   191 {

   192     uint32_t code = intc_accept_interrupt();

   193     sh4r.ssr = sh4_read_sr();

   194     sh4r.spc = sh4r.pc;

   195     sh4r.sgr = sh4r.r[15];

   196     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );

   197     MMIO_WRITE( MMU, INTEVT, code );

   198     sh4r.pc = sh4r.vbr + 0x600;

   199     sh4r.new_pc = sh4r.pc + 2;

   200     WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );

   201 }

   202 

   203 void sh4_execute_instruction( void )

   204 {

   205     int pc;

   206     unsigned short ir;

   207     uint32_t tmp;

   208     uint64_t tmpl;

   209     

   210 #define R0 sh4r.r[0]

   211 #define FR0 (FR[0])

   212 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]

   213 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]

   214 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]

   215 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */

   216 #define DISP8(ir) (ir&0x00FF)

   217 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)

   218 #define IMM8(ir) SIGNEXT8(ir&0x00FF)

   219 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */

   220 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)

   221 #define FVN(ir) ((ir&0x0C00)>>8)

   222 #define FVM(ir) ((ir&0x0300)>>6)

   223 #define FRN(ir) (FR[(ir&0x0F00)>>8])

   224 #define FRM(ir) (FR[(ir&0x00F0)>>4])

   225 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])

   226 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])

   227 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])

   228 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])

   229 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])

   230 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])

   231 #define FRNn(ir) ((ir&0x0F00)>>8)

   232 #define FRMn(ir) ((ir&0x00F0)>>4)

   233 #define FPULf   *((float *)&sh4r.fpul)

   234 #define FPULi    (sh4r.fpul)

   235 

   236     if( SH4_INT_PENDING() ) 

   237         sh4_accept_interrupt();

   238                  

   239     pc = sh4r.pc;

   240     ir = MEM_READ_WORD(pc);

   241     sh4r.icount++;

   242     

   243     switch( (ir&0xF000)>>12 ) {

   244         case 0: /* 0000nnnnmmmmxxxx */

   245             switch( ir&0x000F ) {

   246                 case 2:

   247                     switch( (ir&0x00F0)>>4 ) {

   248                         case 0: /* STC     SR, Rn */

   249                             CHECKPRIV();

   250                             RN(ir) = sh4_read_sr();

   251                             break;

   252                         case 1: /* STC     GBR, Rn */

   253                             RN(ir) = sh4r.gbr;

   254                             break;

   255                         case 2: /* STC     VBR, Rn */

   256                             CHECKPRIV();

   257                             RN(ir) = sh4r.vbr;

   258                             break;

   259                         case 3: /* STC     SSR, Rn */

   260                             CHECKPRIV();

   261                             RN(ir) = sh4r.ssr;

   262                             break;

   263                         case 4: /* STC     SPC, Rn */

   264                             CHECKPRIV();

   265                             RN(ir) = sh4r.spc;

   266                             break;

   267                         case 8: case 9: case 10: case 11: case 12: case 13:

   268                         case 14: case 15:/* STC     Rm_bank, Rn */

   269                             CHECKPRIV();

   270                             RN(ir) = RN_BANK(ir);

   271                             break;

   272                         default: UNDEF(ir);

   273                     }

   274                     break;

   275                 case 3:

   276                     switch( (ir&0x00F0)>>4 ) {

   277                         case 0: /* BSRF    Rn */

   278                             CHECKDEST( pc + 4 + RN(ir) );

   279                             CHECKSLOTILLEGAL();

   280                             sh4r.in_delay_slot = 1;

   281                             sh4r.pr = sh4r.pc + 4;

   282                             sh4r.pc = sh4r.new_pc;

   283                             sh4r.new_pc = pc + 4 + RN(ir);

   284                             return;

   285                         case 2: /* BRAF    Rn */

   286                             CHECKDEST( pc + 4 + RN(ir) );

   287                             CHECKSLOTILLEGAL();

   288                             sh4r.in_delay_slot = 1;

   289                             sh4r.pc = sh4r.new_pc;

   290                             sh4r.new_pc = pc + 4 + RN(ir);

   291                             return;

   292                         case 8: /* PREF    [Rn] */

   293                             tmp = RN(ir);

   294                             if( (tmp & 0xFC000000) == 0xE0000000 ) {

   295                                 /* Store queue operation */

   296                                 int queue = (tmp&0x20)>>2;

   297                                 int32_t *src = &sh4r.store_queue[queue];

   298                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;

   299                                 uint32_t target = tmp&0x03FFFFE0 | hi;

   300                                 mem_copy_to_sh4( target, src, 32 );

   301                                 WARN( "Executed SQ%c => %08X",

   302                                       (queue == 0 ? '0' : '1'), target );

   303                             }

   304                             break;

   305                         case 9: /* OCBI    [Rn] */

   306                         case 10:/* OCBP    [Rn] */

   307                         case 11:/* OCBWB   [Rn] */

   308                             /* anything? */

   309                             break;

   310                         case 12:/* MOVCA.L R0, [Rn] */

   311                             UNIMP(ir);

   312                         default: UNDEF(ir);

   313                     }

   314                     break;

   315                 case 4: /* MOV.B   Rm, [R0 + Rn] */

   316                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );

   317                     break;

   318                 case 5: /* MOV.W   Rm, [R0 + Rn] */

   319                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );

   320                     break;

   321                 case 6: /* MOV.L   Rm, [R0 + Rn] */

   322                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );

   323                     break;

   324                 case 7: /* MUL.L   Rm, Rn */

   325                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   326                         (RM(ir) * RN(ir));

   327                     break;

   328                 case 8: 

   329                     switch( (ir&0x0FF0)>>4 ) {

   330                         case 0: /* CLRT    */

   331                             sh4r.t = 0;

   332                             break;

   333                         case 1: /* SETT    */

   334                             sh4r.t = 1;

   335                             break;

   336                         case 2: /* CLRMAC  */

   337                             sh4r.mac = 0;

   338                             break;

   339                         case 3: /* LDTLB   */

   340                             break;

   341                         case 4: /* CLRS    */

   342                             sh4r.s = 0;

   343                             break;

   344                         case 5: /* SETS    */

   345                             sh4r.s = 1;

   346                             break;

   347                         default: UNDEF(ir);

   348                     }

   349                     break;

   350                 case 9: 

   351                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */

   352                         RN(ir) = sh4r.t;

   353                     else if( ir == 0x0019 ) /* DIV0U   */

   354                         sh4r.m = sh4r.q = sh4r.t = 0;

   355                     else if( ir == 0x0009 )

   356                         /* NOP     */;

   357                     else UNDEF(ir);

   358                     break;

   359                 case 10:

   360                     switch( (ir&0x00F0) >> 4 ) {

   361                         case 0: /* STS     MACH, Rn */

   362                             RN(ir) = sh4r.mac >> 32;

   363                             break;

   364                         case 1: /* STS     MACL, Rn */

   365                             RN(ir) = (uint32_t)sh4r.mac;

   366                             break;

   367                         case 2: /* STS     PR, Rn */

   368                             RN(ir) = sh4r.pr;

   369                             break;

   370                         case 3: /* STC     SGR, Rn */

   371                             CHECKPRIV();

   372                             RN(ir) = sh4r.sgr;

   373                             break;

   374                         case 5:/* STS      FPUL, Rn */

   375                             RN(ir) = sh4r.fpul;

   376                             break;

   377                         case 6: /* STS     FPSCR, Rn */

   378                             RN(ir) = sh4r.fpscr;

   379                             break;

   380                         case 15:/* STC     DBR, Rn */

   381                             CHECKPRIV();

   382                             RN(ir) = sh4r.dbr;

   383                             break;

   384                         default: UNDEF(ir);

   385                     }

   386                     break;

   387                 case 11:

   388                     switch( (ir&0x0FF0)>>4 ) {

   389                         case 0: /* RTS     */

   390                             CHECKDEST( sh4r.pr );

   391                             CHECKSLOTILLEGAL();

   392                             sh4r.in_delay_slot = 1;

   393                             sh4r.pc = sh4r.new_pc;

   394                             sh4r.new_pc = sh4r.pr;

   395                             return;

   396                         case 1: /* SLEEP   */

   397                             running = 0;

   398                             break;

   399                         case 2: /* RTE     */

   400                             CHECKPRIV();

   401                             CHECKDEST( sh4r.spc );

   402                             CHECKSLOTILLEGAL();

   403                             sh4r.in_delay_slot = 1;

   404                             sh4r.pc = sh4r.new_pc;

   405                             sh4r.new_pc = sh4r.spc;

   406                             sh4_load_sr( sh4r.ssr );

   407                             WARN( "RTE => %08X", sh4r.new_pc );

   408                             return;

   409                         default:UNDEF(ir);

   410                     }

   411                     break;

   412                 case 12:/* MOV.B   [R0+R%d], R%d */

   413                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );

   414                     break;

   415                 case 13:/* MOV.W   [R0+R%d], R%d */

   416                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );

   417                     break;

   418                 case 14:/* MOV.L   [R0+R%d], R%d */

   419                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );

   420                     break;

   421                 case 15:/* MAC.L   [Rm++], [Rn++] */

   422                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *

   423                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );

   424                     if( sh4r.s ) {

   425                         /* 48-bit Saturation. Yuch */

   426                         tmpl += SIGNEXT48(sh4r.mac);

   427                         if( tmpl < 0xFFFF800000000000LL )

   428                             tmpl = 0xFFFF800000000000LL;

   429                         else if( tmpl > 0x00007FFFFFFFFFFFLL )

   430                             tmpl = 0x00007FFFFFFFFFFFLL;

   431                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |

   432                             (tmpl&0x0000FFFFFFFFFFFFLL);

   433                     } else sh4r.mac = tmpl;

   434                     

   435                     RM(ir) += 4;

   436                     RN(ir) += 4;

   437                     

   438                     break;

   439                 default: UNDEF(ir);

   440             }

   441             break;

   442         case 1: /* 0001nnnnmmmmdddd */

   443             /* MOV.L   Rm, [Rn + disp4*4] */

   444             MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );

   445             break;

   446         case 2: /* 0010nnnnmmmmxxxx */

   447             switch( ir&0x000F ) {

   448                 case 0: /* MOV.B   Rm, [Rn] */

   449                     MEM_WRITE_BYTE( RN(ir), RM(ir) );

   450                     break;

   451                 case 1: /* MOV.W   Rm, [Rn] */

   452                     MEM_WRITE_WORD( RN(ir), RM(ir) );

   453                     break;

   454                 case 2: /* MOV.L   Rm, [Rn] */

   455                     MEM_WRITE_LONG( RN(ir), RM(ir) );

   456                     break;

   457                 case 3: UNDEF(ir);

   458                     break;

   459                 case 4: /* MOV.B   Rm, [--Rn] */

   460                     RN(ir) --;

   461                     MEM_WRITE_BYTE( RN(ir), RM(ir) );

   462                     break;

   463                 case 5: /* MOV.W   Rm, [--Rn] */

   464                     RN(ir) -= 2;

   465                     MEM_WRITE_WORD( RN(ir), RM(ir) );

   466                     break;

   467                 case 6: /* MOV.L   Rm, [--Rn] */

   468                     RN(ir) -= 4;

   469                     MEM_WRITE_LONG( RN(ir), RM(ir) );

   470                     break;

   471                 case 7: /* DIV0S   Rm, Rn */

   472                     sh4r.q = RN(ir)>>31;

   473                     sh4r.m = RM(ir)>>31;

   474                     sh4r.t = sh4r.q ^ sh4r.m;

   475                     break;

   476                 case 8: /* TST     Rm, Rn */

   477                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);

   478                     break;

   479                 case 9: /* AND     Rm, Rn */

   480                     RN(ir) &= RM(ir);

   481                     break;

   482                 case 10:/* XOR     Rm, Rn */

   483                     RN(ir) ^= RM(ir);

   484                     break;

   485                 case 11:/* OR      Rm, Rn */

   486                     RN(ir) |= RM(ir);

   487                     break;

   488                 case 12:/* CMP/STR Rm, Rn */

   489                     /* set T = 1 if any byte in RM & RN is the same */

   490                     tmp = RM(ir) ^ RN(ir);

   491                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||

   492                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;

   493                     break;

   494                 case 13:/* XTRCT   Rm, Rn */

   495                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);

   496                     break;

   497                 case 14:/* MULU.W  Rm, Rn */

   498                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   499                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));

   500                     break;

   501                 case 15:/* MULS.W  Rm, Rn */

   502                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   503                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));

   504                     break;

   505             }

   506             break;

   507         case 3: /* 0011nnnnmmmmxxxx */

   508             switch( ir&0x000F ) {

   509                 case 0: /* CMP/EQ  Rm, Rn */

   510                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );

   511                     break;

   512                 case 2: /* CMP/HS  Rm, Rn */

   513                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );

   514                     break;

   515                 case 3: /* CMP/GE  Rm, Rn */

   516                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );

   517                     break;

   518                 case 4: { /* DIV1    Rm, Rn */

   519                     /* This is just from the sh4p manual with some

   520                      * simplifications (someone want to check it's correct? :)

   521                      * Why they couldn't just provide a real DIV instruction...

   522                      * Please oh please let the translator batch these things

   523                      * up into a single DIV... */

   524                     uint32_t tmp0, tmp1, tmp2, dir;

   525 

   526                     dir = sh4r.q ^ sh4r.m;

   527                     sh4r.q = (RN(ir) >> 31);

   528                     tmp2 = RM(ir);

   529                     RN(ir) = (RN(ir) << 1) | sh4r.t;

   530                     tmp0 = RN(ir);

   531                     if( dir ) {

   532                         RN(ir) += tmp2;

   533                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );

   534                     } else {

   535                         RN(ir) -= tmp2;

   536                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );

   537                     }

   538                     sh4r.q ^= sh4r.m ^ tmp1;

   539                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );

   540                     break; }

   541                 case 5: /* DMULU.L Rm, Rn */

   542                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));

   543                     break;

   544                 case 6: /* CMP/HI  Rm, Rn */

   545                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );

   546                     break;

   547                 case 7: /* CMP/GT  Rm, Rn */

   548                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );

   549                     break;

   550                 case 8: /* SUB     Rm, Rn */

   551                     RN(ir) -= RM(ir);

   552                     break;

   553                 case 10:/* SUBC    Rm, Rn */

   554                     tmp = RN(ir);

   555                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;

   556                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));

   557                     break;

   558                 case 11:/* SUBV    Rm, Rn */

   559                     UNIMP(ir);

   560                     break;

   561                 case 12:/* ADD     Rm, Rn */

   562                     RN(ir) += RM(ir);

   563                     break;

   564                 case 13:/* DMULS.L Rm, Rn */

   565                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));

   566                     break;

   567                 case 14:/* ADDC    Rm, Rn */

   568                     tmp = RN(ir);

   569                     RN(ir) += RM(ir) + sh4r.t;

   570                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );

   571                     break;

   572                 case 15:/* ADDV    Rm, Rn */

   573                     UNIMP(ir);

   574                     break;

   575                 default: UNDEF(ir);

   576             }

   577             break;

   578         case 4: /* 0100nnnnxxxxxxxx */

   579             switch( ir&0x00FF ) {

   580                 case 0x00: /* SHLL    Rn */

   581                     sh4r.t = RN(ir) >> 31;

   582                     RN(ir) <<= 1;

   583                     break;

   584                 case 0x01: /* SHLR    Rn */

   585                     sh4r.t = RN(ir) & 0x00000001;

   586                     RN(ir) >>= 1;

   587                     break;

   588                 case 0x02: /* STS.L   MACH, [--Rn] */

   589                     RN(ir) -= 4;

   590                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );

   591                     break;

   592                 case 0x03: /* STC.L   SR, [--Rn] */

   593                     CHECKPRIV();

   594                     RN(ir) -= 4;

   595                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );

   596                     break;

   597                 case 0x04: /* ROTL    Rn */

   598                     sh4r.t = RN(ir) >> 31;

   599                     RN(ir) <<= 1;

   600                     RN(ir) |= sh4r.t;

   601                     break;

   602                 case 0x05: /* ROTR    Rn */

   603                     sh4r.t = RN(ir) & 0x00000001;

   604                     RN(ir) >>= 1;

   605                     RN(ir) |= (sh4r.t << 31);

   606                     break;

   607                 case 0x06: /* LDS.L   [Rn++], MACH */

   608                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

   609                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);

   610                     RN(ir) += 4;

   611                     break;

   612                 case 0x07: /* LDC.L   [Rn++], SR */

   613                     CHECKPRIV();

   614                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );

   615                     RN(ir) +=4;

   616                     break;

   617                 case 0x08: /* SHLL2   Rn */

   618                     RN(ir) <<= 2;

   619                     break;

   620                 case 0x09: /* SHLR2   Rn */

   621                     RN(ir) >>= 2;

   622                     break;

   623                 case 0x0A: /* LDS     Rn, MACH */

   624                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

   625                         (((uint64_t)RN(ir))<<32);

   626                     break;

   627                 case 0x0B: /* JSR     [Rn] */

   628                     CHECKDEST( RN(ir) );

   629                     CHECKSLOTILLEGAL();

   630                     sh4r.in_delay_slot = 1;

   631                     sh4r.pc = sh4r.new_pc;

   632                     sh4r.new_pc = RN(ir);

   633                     sh4r.pr = pc + 4;

   634                     return;

   635                 case 0x0E: /* LDC     Rn, SR */

   636                     CHECKPRIV();

   637                     sh4_load_sr( RN(ir) );

   638                     break;

   639                 case 0x10: /* DT      Rn */

   640                     RN(ir) --;

   641                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );

   642                     break;

   643                 case 0x11: /* CMP/PZ  Rn */

   644                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );

   645                     break;

   646                 case 0x12: /* STS.L   MACL, [--Rn] */

   647                     RN(ir) -= 4;

   648                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );

   649                     break;

   650                 case 0x13: /* STC.L   GBR, [--Rn] */

   651                     RN(ir) -= 4;

   652                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );

   653                     break;

   654                 case 0x15: /* CMP/PL  Rn */

   655                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );

   656                     break;

   657                 case 0x16: /* LDS.L   [Rn++], MACL */

   658                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

   659                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));

   660                     RN(ir) += 4;

   661                     break;

   662                 case 0x17: /* LDC.L   [Rn++], GBR */

   663                     sh4r.gbr = MEM_READ_LONG(RN(ir));

   664                     RN(ir) +=4;

   665                     break;

   666                 case 0x18: /* SHLL8   Rn */

   667                     RN(ir) <<= 8;

   668                     break;

   669                 case 0x19: /* SHLR8   Rn */

   670                     RN(ir) >>= 8;

   671                     break;

   672                 case 0x1A: /* LDS     Rn, MACL */

   673                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

   674                         (uint64_t)((uint32_t)(RN(ir)));

   675                     break;

   676                 case 0x1B: /* TAS.B   [Rn] */

   677                     tmp = MEM_READ_BYTE( RN(ir) );

   678                     sh4r.t = ( tmp == 0 ? 1 : 0 );

   679                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );

   680                     break;

   681                 case 0x1E: /* LDC     Rn, GBR */

   682                     sh4r.gbr = RN(ir);

   683                     break;

   684                 case 0x20: /* SHAL    Rn */

   685                     sh4r.t = RN(ir) >> 31;

   686                     RN(ir) <<= 1;

   687                     break;

   688                 case 0x21: /* SHAR    Rn */

   689                     sh4r.t = RN(ir) & 0x00000001;

   690                     RN(ir) = ((int32_t)RN(ir)) >> 1;

   691                     break;

   692                 case 0x22: /* STS.L   PR, [--Rn] */

   693                     RN(ir) -= 4;

   694                     MEM_WRITE_LONG( RN(ir), sh4r.pr );

   695                     break;

   696                 case 0x23: /* STC.L   VBR, [--Rn] */

   697                     CHECKPRIV();

   698                     RN(ir) -= 4;

   699                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );

   700                     break;

   701                 case 0x24: /* ROTCL   Rn */

   702                     tmp = RN(ir) >> 31;

   703                     RN(ir) <<= 1;

   704                     RN(ir) |= sh4r.t;

   705                     sh4r.t = tmp;

   706                     break;

   707                 case 0x25: /* ROTCR   Rn */

   708                     tmp = RN(ir) & 0x00000001;

   709                     RN(ir) >>= 1;

   710                     RN(ir) |= (sh4r.t << 31 );

   711                     sh4r.t = tmp;

   712                     break;

   713                 case 0x26: /* LDS.L   [Rn++], PR */

   714                     sh4r.pr = MEM_READ_LONG( RN(ir) );

   715                     RN(ir) += 4;

   716                     break;

   717                 case 0x27: /* LDC.L   [Rn++], VBR */

   718                     CHECKPRIV();

   719                     sh4r.vbr = MEM_READ_LONG(RN(ir));

   720                     RN(ir) +=4;

   721                     break;

   722                 case 0x28: /* SHLL16  Rn */

   723                     RN(ir) <<= 16;

   724                     break;

   725                 case 0x29: /* SHLR16  Rn */

   726                     RN(ir) >>= 16;

   727                     break;

   728                 case 0x2A: /* LDS     Rn, PR */

   729                     sh4r.pr = RN(ir);

   730                     break;

   731                 case 0x2B: /* JMP     [Rn] */

   732                     CHECKDEST( RN(ir) );

   733                     CHECKSLOTILLEGAL();

   734                     sh4r.in_delay_slot = 1;

   735                     sh4r.pc = sh4r.new_pc;

   736                     sh4r.new_pc = RN(ir);

   737                     return;

   738                 case 0x2E: /* LDC     Rn, VBR */

   739                     CHECKPRIV();

   740                     sh4r.vbr = RN(ir);

   741                     break;

   742                 case 0x32: /* STC.L   SGR, [--Rn] */

   743                     CHECKPRIV();

   744                     RN(ir) -= 4;

   745                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );

   746                     break;

   747                 case 0x33: /* STC.L   SSR, [--Rn] */

   748                     CHECKPRIV();

   749                     RN(ir) -= 4;

   750                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );

   751                     break;

   752                 case 0x37: /* LDC.L   [Rn++], SSR */

   753                     CHECKPRIV();

   754                     sh4r.ssr = MEM_READ_LONG(RN(ir));

   755                     RN(ir) +=4;

   756                     break;

   757                 case 0x3E: /* LDC     Rn, SSR */

   758                     CHECKPRIV();

   759                     sh4r.ssr = RN(ir);

   760                     break;

   761                 case 0x43: /* STC.L   SPC, [--Rn] */

   762                     CHECKPRIV();

   763                     RN(ir) -= 4;

   764                     MEM_WRITE_LONG( RN(ir), sh4r.spc );

   765                     break;

   766                 case 0x47: /* LDC.L   [Rn++], SPC */

   767                     CHECKPRIV();

   768                     sh4r.spc = MEM_READ_LONG(RN(ir));

   769                     RN(ir) +=4;

   770                     break;

   771                 case 0x4E: /* LDC     Rn, SPC */

   772                     CHECKPRIV();

   773                     sh4r.spc = RN(ir);

   774                     break;

   775                 case 0x52: /* STS.L   FPUL, [--Rn] */

   776                     RN(ir) -= 4;

   777                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );

   778                     break;

   779                 case 0x56: /* LDS.L   [Rn++], FPUL */

   780                     sh4r.fpul = MEM_READ_LONG(RN(ir));

   781                     RN(ir) +=4;

   782                     break;

   783                 case 0x5A: /* LDS     Rn, FPUL */

   784                     sh4r.fpul = RN(ir);

   785                     break;

   786                 case 0x62: /* STS.L   FPSCR, [--Rn] */

   787                     RN(ir) -= 4;

   788                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );

   789                     break;

   790                 case 0x66: /* LDS.L   [Rn++], FPSCR */

   791                     sh4r.fpscr = MEM_READ_LONG(RN(ir));

   792                     RN(ir) +=4;

   793                     break;

   794                 case 0x6A: /* LDS     Rn, FPSCR */

   795                     sh4r.fpscr = RN(ir);

   796                     break;

   797                 case 0xF2: /* STC.L   DBR, [--Rn] */

   798                     CHECKPRIV();

   799                     RN(ir) -= 4;

   800                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );

   801                     break;

   802                 case 0xF6: /* LDC.L   [Rn++], DBR */

   803                     CHECKPRIV();

   804                     sh4r.dbr = MEM_READ_LONG(RN(ir));

   805                     RN(ir) +=4;

   806                     break;

   807                 case 0xFA: /* LDC     Rn, DBR */

   808                     CHECKPRIV();

   809                     sh4r.dbr = RN(ir);

   810                     break;

   811                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:

   812                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */

   813                     CHECKPRIV();

   814                     RN(ir) -= 4;

   815                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );

   816                     break;

   817                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:

   818                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */

   819                     CHECKPRIV();

   820                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );

   821                     RN(ir) += 4;

   822                     break;

   823                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:

   824                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */

   825                     CHECKPRIV();

   826                     RN_BANK(ir) = RM(ir);

   827                     break;

   828                 default:

   829                     if( (ir&0x000F) == 0x0F ) {

   830                         /* MAC.W   [Rm++], [Rn++] */

   831                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *

   832                             SIGNEXT16(MEM_READ_WORD(RN(ir)));

   833                         if( sh4r.s ) {

   834                             /* FIXME */

   835                             UNIMP(ir);

   836                         } else sh4r.mac += SIGNEXT32(tmp);

   837                         RM(ir) += 2;

   838                         RN(ir) += 2;

   839                     } else if( (ir&0x000F) == 0x0C ) {

   840                         /* SHAD    Rm, Rn */

   841                         tmp = RM(ir);

   842                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);

   843                         else if( (tmp & 0x1F) == 0 )  

   844 			  RN(ir) = ((int32_t)RN(ir)) >> 31;

   845                         else 

   846 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);

   847                     } else if( (ir&0x000F) == 0x0D ) {

   848                         /* SHLD    Rm, Rn */

   849                         tmp = RM(ir);

   850                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);

   851                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;

   852                         else RN(ir) >>= (((~tmp) & 0x1F)+1);

   853                     } else UNDEF(ir);

   854             }

   855             break;

   856         case 5: /* 0101nnnnmmmmdddd */

   857             /* MOV.L   [Rm + disp4*4], Rn */

   858             RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );

   859             break;

   860         case 6: /* 0110xxxxxxxxxxxx */

   861             switch( ir&0x000f ) {

   862                 case 0: /* MOV.B   [Rm], Rn */

   863                     RN(ir) = MEM_READ_BYTE( RM(ir) );

   864                     break;

   865                 case 1: /* MOV.W   [Rm], Rn */

   866                     RN(ir) = MEM_READ_WORD( RM(ir) );

   867                     break;

   868                 case 2: /* MOV.L   [Rm], Rn */

   869                     RN(ir) = MEM_READ_LONG( RM(ir) );

   870                     break;

   871                 case 3: /* MOV     Rm, Rn */

   872                     RN(ir) = RM(ir);

   873                     break;

   874                 case 4: /* MOV.B   [Rm++], Rn */

   875                     RN(ir) = MEM_READ_BYTE( RM(ir) );

   876                     RM(ir) ++;

   877                     break;

   878                 case 5: /* MOV.W   [Rm++], Rn */

   879                     RN(ir) = MEM_READ_WORD( RM(ir) );

   880                     RM(ir) += 2;

   881                     break;

   882                 case 6: /* MOV.L   [Rm++], Rn */

   883                     RN(ir) = MEM_READ_LONG( RM(ir) );

   884                     RM(ir) += 4;

   885                     break;

   886                 case 7: /* NOT     Rm, Rn */

   887                     RN(ir) = ~RM(ir);

   888                     break;

   889                 case 8: /* SWAP.B  Rm, Rn */

   890                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |

   891                         ((RM(ir)&0x000000FF)<<8);

   892                     break;

   893                 case 9: /* SWAP.W  Rm, Rn */

   894                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);

   895                     break;

   896                 case 10:/* NEGC    Rm, Rn */

   897                     tmp = 0 - RM(ir);

   898                     RN(ir) = tmp - sh4r.t;

   899                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );

   900                     break;

   901                 case 11:/* NEG     Rm, Rn */

   902                     RN(ir) = 0 - RM(ir);

   903                     break;

   904                 case 12:/* EXTU.B  Rm, Rn */

   905                     RN(ir) = RM(ir)&0x000000FF;

   906                     break;

   907                 case 13:/* EXTU.W  Rm, Rn */

   908                     RN(ir) = RM(ir)&0x0000FFFF;

   909                     break;

   910                 case 14:/* EXTS.B  Rm, Rn */

   911                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );

   912                     break;

   913                 case 15:/* EXTS.W  Rm, Rn */

   914                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );

   915                     break;

   916             }

   917             break;

   918         case 7: /* 0111nnnniiiiiiii */

   919             /* ADD    imm8, Rn */

   920             RN(ir) += IMM8(ir);

   921             break;

   922         case 8: /* 1000xxxxxxxxxxxx */

   923             switch( (ir&0x0F00) >> 8 ) {

   924                 case 0: /* MOV.B   R0, [Rm + disp4] */

   925                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );

   926                     break;

   927                 case 1: /* MOV.W   R0, [Rm + disp4*2] */

   928                     MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );

   929                     break;

   930                 case 4: /* MOV.B   [Rm + disp4], R0 */

   931                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );

   932                     break;

   933                 case 5: /* MOV.W   [Rm + disp4*2], R0 */

   934                     R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );

   935                     break;

   936                 case 8: /* CMP/EQ  imm, R0 */

   937                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );

   938                     break;

   939                 case 9: /* BT      disp8 */

   940                     CHECKSLOTILLEGAL()

   941                     if( sh4r.t ) {

   942                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )

   943                         sh4r.pc += (PCDISP8(ir)<<1) + 4;

   944                         sh4r.new_pc = sh4r.pc + 2;

   945                         return;

   946                     }

   947                     break;

   948                 case 11:/* BF      disp8 */

   949                     CHECKSLOTILLEGAL()

   950                     if( !sh4r.t ) {

   951                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )

   952                         sh4r.pc += (PCDISP8(ir)<<1) + 4;

   953                         sh4r.new_pc = sh4r.pc + 2;

   954                         return;

   955                     }

   956                     break;

   957                 case 13:/* BT/S    disp8 */

   958                     CHECKSLOTILLEGAL()

   959                     if( sh4r.t ) {

   960                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )

   961                         sh4r.in_delay_slot = 1;

   962                         sh4r.pc = sh4r.new_pc;

   963                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;

   964                         sh4r.in_delay_slot = 1;

   965                         return;

   966                     }

   967                     break;

   968                 case 15:/* BF/S    disp8 */

   969                     CHECKSLOTILLEGAL()

   970                     if( !sh4r.t ) {

   971                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )

   972                         sh4r.in_delay_slot = 1;

   973                         sh4r.pc = sh4r.new_pc;

   974                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;

   975                         return;

   976                     }

   977                     break;

   978                 default: UNDEF(ir);

   979             }

   980             break;

   981         case 9: /* 1001xxxxxxxxxxxx */

   982             /* MOV.W   [disp8*2 + pc + 4], Rn */

   983             RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );

   984             break;

   985         case 10:/* 1010dddddddddddd */

   986             /* BRA     disp12 */

   987             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )

   988             CHECKSLOTILLEGAL()

   989             sh4r.in_delay_slot = 1;

   990             sh4r.pc = sh4r.new_pc;

   991             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);

   992             return;

   993         case 11:/* 1011dddddddddddd */

   994             /* BSR     disp12 */

   995             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )

   996             CHECKSLOTILLEGAL()

   997             sh4r.in_delay_slot = 1;

   998             sh4r.pr = pc + 4;

   999             sh4r.pc = sh4r.new_pc;

  1000             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);

  1001             return;

  1002         case 12:/* 1100xxxxdddddddd */

  1003         switch( (ir&0x0F00)>>8 ) {

  1004                 case 0: /* MOV.B  R0, [GBR + disp8] */

  1005                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );

  1006                     break;

  1007                 case 1: /* MOV.W  R0, [GBR + disp8*2] */

  1008                     MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );

  1009                     break;

  1010                 case  2: /*MOV.L   R0, [GBR + disp8*4] */

  1011                     MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );

  1012                     break;

  1013                 case 3: /* TRAPA   imm8 */

  1014                     CHECKSLOTILLEGAL()

  1015                     sh4r.in_delay_slot = 1;

  1016                     MMIO_WRITE( MMU, TRA, UIMM8(ir) );

  1017                     sh4r.pc = sh4r.new_pc;  /* RAISE ends the instruction */

  1018                     sh4r.new_pc += 2;

  1019                     RAISE( EXC_TRAP, EXV_TRAP );

  1020                     break;

  1021                 case 4: /* MOV.B   [GBR + disp8], R0 */

  1022                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );

  1023                     break;

  1024                 case 5: /* MOV.W   [GBR + disp8*2], R0 */

  1025                     R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );

  1026                     break;

  1027                 case 6: /* MOV.L   [GBR + disp8*4], R0 */

  1028                     R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );

  1029                     break;

  1030                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */

  1031                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;

  1032                     break;

  1033                 case 8: /* TST     imm8, R0 */

  1034                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);

  1035                     break;

  1036                 case 9: /* AND     imm8, R0 */

  1037                     R0 &= UIMM8(ir);

  1038                     break;

  1039                 case 10:/* XOR     imm8, R0 */

  1040                     R0 ^= UIMM8(ir);

  1041                     break;

  1042                 case 11:/* OR      imm8, R0 */

  1043                     R0 |= UIMM8(ir);

  1044                     break;

  1045                 case 12:/* TST.B   imm8, [R0+GBR] */

  1046                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );

  1047                     break;

  1048                 case 13:/* AND.B   imm8, [R0+GBR] */

  1049                     MEM_WRITE_BYTE( R0 + sh4r.gbr,

  1050                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );

  1051                     break;

  1052                 case 14:/* XOR.B   imm8, [R0+GBR] */

  1053                     MEM_WRITE_BYTE( R0 + sh4r.gbr,

  1054                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );

  1055                     break;

  1056                 case 15:/* OR.B    imm8, [R0+GBR] */

  1057                     MEM_WRITE_BYTE( R0 + sh4r.gbr,

  1058                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );

  1059                     break;

  1060             }

  1061             break;

  1062         case 13:/* 1101nnnndddddddd */

  1063             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */

  1064             RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );

  1065             break;

  1066         case 14:/* 1110nnnniiiiiiii */

  1067             /* MOV     imm8, Rn */

  1068             RN(ir) = IMM8(ir);

  1069             break;

  1070         case 15:/* 1111xxxxxxxxxxxx */

  1071             CHECKFPUEN();

  1072             switch( ir&0x000F ) {

  1073                 case 0: /* FADD    FRm, FRn */

  1074                     FRN(ir) += FRM(ir);

  1075                     break;

  1076                 case 1: /* FSUB    FRm, FRn */

  1077                     FRN(ir) -= FRM(ir);

  1078                     break;

  1079                 case 2: /* FMUL    FRm, FRn */

  1080                     FRN(ir) = FRN(ir) * FRM(ir);

  1081                     break;

  1082                 case 3: /* FDIV    FRm, FRn */

  1083                     FRN(ir) = FRN(ir) / FRM(ir);

  1084                     break;

  1085                 case 4: /* FCMP/EQ FRm, FRn */

  1086                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );

  1087                     break;

  1088                 case 5: /* FCMP/GT FRm, FRn */

  1089                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );

  1090                     break;

  1091                 case 6: /* FMOV.S  [Rm+R0], FRn */

  1092                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );

  1093                     break;

  1094                 case 7: /* FMOV.S  FRm, [Rn+R0] */

  1095                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );

  1096                     break;

  1097                 case 8: /* FMOV.S  [Rm], FRn */

  1098                     MEM_FP_READ( RM(ir), FRNn(ir) );

  1099                     break;

  1100                 case 9: /* FMOV.S  [Rm++], FRn */

  1101                     MEM_FP_READ( RM(ir), FRNn(ir) );

  1102                     RM(ir) += FP_WIDTH;

  1103                     break;

  1104                 case 10:/* FMOV.S  FRm, [Rn] */

  1105                     MEM_FP_WRITE( RN(ir), FRMn(ir) );

  1106                     break;

  1107                 case 11:/* FMOV.S  FRm, [--Rn] */

  1108                     RN(ir) -= FP_WIDTH;

  1109                     MEM_FP_WRITE( RN(ir), FRMn(ir) );

  1110                     break;

  1111                 case 12:/* FMOV    FRm, FRn */

  1112                     if( IS_FPU_DOUBLESIZE() ) {

  1113                         DRN(ir) = DRM(ir);

  1114                     } else {

  1115                         FRN(ir) = FRM(ir);

  1116                     }

  1117                     break;

  1118                 case 13:

  1119                     switch( (ir&0x00F0) >> 4 ) {

  1120                         case 0: /* FSTS    FPUL, FRn */

  1121                             FRN(ir) = FPULf;

  1122                             break;

  1123                         case 1: /* FLDS    FRn, FPUL */

  1124                             FPULf = FRN(ir);

  1125                             break;

  1126                         case 2: /* FLOAT   FPUL, FRn */

  1127                             FRN(ir) = (float)FPULi;

  1128                             break;

  1129                         case 3: /* FTRC    FRn, FPUL */

  1130                             FPULi = (uint32_t)FRN(ir);

  1131                             /* FIXME: is this sufficient? */

  1132                             break;

  1133                         case 4: /* FNEG    FRn */

  1134                             FRN(ir) = -FRN(ir);

  1135                             break;

  1136                         case 5: /* FABS    FRn */

  1137                             FRN(ir) = fabsf(FRN(ir));

  1138                             break;

  1139                         case 6: /* FSQRT   FRn */

  1140                             FRN(ir) = sqrtf(FRN(ir));

  1141                             break;

  1142                         case 7: /* FSRRA FRn */

  1143                             FRN(ir) = 1.0/sqrtf(FRN(ir));

  1144                             break;

  1145                         case 8: /* FLDI0   FRn */

  1146                             FRN(ir) = 0.0;

  1147                             break;

  1148                         case 9: /* FLDI1   FRn */

  1149                             FRN(ir) = 1.0;

  1150                             break;

  1151                         case 10: /* FCNVSD FPUL, DRn */

  1152                             if( IS_FPU_DOUBLEPREC() )

  1153                                 DRN(ir) = (double)FPULf;

  1154                             else UNDEF(ir);

  1155                             break;

  1156                         case 11: /* FCNVDS DRn, FPUL */

  1157                             if( IS_FPU_DOUBLEPREC() ) 

  1158                                 FPULf = (float)DRN(ir);

  1159                             else UNDEF(ir);

  1160                             break;

  1161                         case 14:/* FIPR    FVm, FVn */

  1162                             /* FIXME: This is not going to be entirely accurate

  1163                              * as the SH4 instruction is less precise. Also

  1164                              * need to check for 0s and infinities.

  1165                              */

  1166                         {

  1167                             float *fr_bank = FR;

  1168                             int tmp2 = FVN(ir);

  1169                             tmp = FVM(ir);

  1170                             fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +

  1171                                 fr_bank[tmp+1]*fr_bank[tmp2+1] +

  1172                                 fr_bank[tmp+2]*fr_bank[tmp2+2] +

  1173                                 fr_bank[tmp+3]*fr_bank[tmp2+3];

  1174                             break;

  1175                         }

  1176                         case 15:

  1177                             if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */

  1178                                 float *fvout = FR+FVN(ir);

  1179                                 float *xm = XF;

  1180                                 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };

  1181                                 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +

  1182                                     xm[8]*fv[2] + xm[12]*fv[3];

  1183                                 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +

  1184                                     xm[9]*fv[2] + xm[13]*fv[3];

  1185                                 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +

  1186                                     xm[10]*fv[2] + xm[14]*fv[3];

  1187                                 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +

  1188                                     xm[11]*fv[2] + xm[15]*fv[3];

  1189                                 break;

  1190                             }

  1191                             else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */

  1192                                 float angle = (((float)(short)(FPULi>>16)) +

  1193                                                ((float)(FPULi&16)/65536.0)) *

  1194                                     2 * M_PI;

  1195                                 int reg = FRNn(ir);

  1196                                 FR[reg] = sinf(angle);

  1197                                 FR[reg+1] = cosf(angle);

  1198                                 break;

  1199                             }

  1200                             else if( ir == 0xFBFD ) {

  1201                                 /* FRCHG   */

  1202                                 sh4r.fpscr ^= FPSCR_FR;

  1203                                 break;

  1204                             }

  1205                             else if( ir == 0xF3FD ) {

  1206                                 /* FSCHG   */

  1207                                 sh4r.fpscr ^= FPSCR_SZ;

  1208                                 break;

  1209                             }

  1210                         default: UNDEF(ir);

  1211                     }

  1212                     break;

  1213                 case 14:/* FMAC    FR0, FRm, FRn */

  1214                     FRN(ir) += FRM(ir)*FR0;

  1215                     break;

  1216                 default: UNDEF(ir);

  1217             }

  1218             break;

  1219     }

  1220     sh4r.pc = sh4r.new_pc;

  1221     sh4r.new_pc += 2;

  1222     sh4r.in_delay_slot = 0;

  1223 }
.