2 * $Id: pvr2.c,v 1.17 2006-03-13 12:39:07 nkeynes Exp $
4 * PVR2 (Video) Core MMIO registers.
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #define MODULE pvr2_module
24 #include "pvr2/pvr2.h"
25 #include "sh4/sh4core.h"
27 #include "pvr2/pvr2mmio.h"
31 void pvr2_init( void );
32 uint32_t pvr2_run_slice( uint32_t );
33 void pvr2_display_frame( void );
36 * Current PVR2 ram address of the data (if any) currently held in the
40 video_driver_t video_driver = NULL;
41 struct video_buffer video_buffer[2];
42 int video_buffer_idx = 0;
45 int fields_per_second;
51 struct video_timing pal_timing = { 50, 625, 575, 32000 };
52 struct video_timing ntsc_timing= { 60, 525, 480, 31746 };
54 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL,
58 void pvr2_init( void )
60 register_io_region( &mmio_region_PVR2 );
61 register_io_region( &mmio_region_PVR2PAL );
62 register_io_region( &mmio_region_PVR2TA );
63 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
64 video_driver = &video_gtk_driver;
65 video_driver->set_display_format( 640, 480, COLFMT_RGB32 );
68 uint32_t pvr2_line_count = 0;
69 uint32_t pvr2_line_remainder = 0;
70 uint32_t pvr2_irq_vpos1 = 0;
71 uint32_t pvr2_irq_vpos2 = 0;
72 struct video_timing *pvr2_timing = &ntsc_timing;
73 uint32_t pvr2_time_counter = 0;
74 uint32_t pvr2_frame_counter = 0;
75 uint32_t pvr2_time_per_frame = 20000000;
77 uint32_t pvr2_run_slice( uint32_t nanosecs )
79 pvr2_line_remainder += nanosecs;
80 while( pvr2_line_remainder >= pvr2_timing->line_time_ns ) {
81 pvr2_line_remainder -= pvr2_timing->line_time_ns;
83 if( pvr2_line_count == pvr2_irq_vpos1 ) {
84 asic_event( EVENT_SCANLINE1 );
86 if( pvr2_line_count == pvr2_irq_vpos2 ) {
87 asic_event( EVENT_SCANLINE2 );
89 if( pvr2_line_count == pvr2_timing->display_lines ) {
90 asic_event( EVENT_RETRACE );
91 } else if( pvr2_line_count == pvr2_timing->total_lines ) {
99 uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
100 int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
101 char *frame_start; /* current video start address (in real memory) */
104 * Display the next frame, copying the current contents of video ram to
105 * the window. If the video configuration has changed, first recompute the
106 * new frame size/depth.
108 void pvr2_display_frame( void )
110 uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
112 int dispsize = MMIO_READ( PVR2, DISPSIZE );
113 int dispmode = MMIO_READ( PVR2, DISPMODE );
114 int vidcfg = MMIO_READ( PVR2, DISPCFG );
115 int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
116 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
117 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
118 gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
119 gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
121 video_buffer_t buffer = &video_buffer[video_buffer_idx];
122 video_buffer_idx = !video_buffer_idx;
123 video_buffer_t last = &video_buffer[video_buffer_idx];
124 buffer->rowstride = (vid_ppl + vid_stride) << 2;
125 buffer->data = frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
126 buffer->vres = vid_lpf;
127 if( interlaced ) buffer->vres <<= 1;
128 switch( (dispmode & DISPMODE_COL) >> 2 ) {
130 buffer->colour_format = COLFMT_ARGB1555;
131 buffer->hres = vid_ppl << 1;
134 buffer->colour_format = COLFMT_RGB565;
135 buffer->hres = vid_ppl << 1;
138 buffer->colour_format = COLFMT_RGB888;
139 buffer->hres = (vid_ppl << 2) / 3;
142 buffer->colour_format = COLFMT_ARGB8888;
143 buffer->hres = vid_ppl;
147 if( video_driver != NULL ) {
148 if( buffer->hres != last->hres ||
149 buffer->vres != last->vres ||
150 buffer->colour_format != last->colour_format) {
151 video_driver->set_display_format( buffer->hres, buffer->vres,
152 buffer->colour_format );
154 if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
155 uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
156 video_driver->display_blank_frame( colour );
157 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
158 video_driver->display_frame( buffer );
162 video_buffer_idx = 0;
163 video_buffer[0].hres = video_buffer[0].vres = 0;
165 pvr2_frame_counter++;
166 asic_event( EVENT_SCANLINE1 );
167 asic_event( EVENT_SCANLINE2 );
168 asic_event( EVENT_RETRACE );
171 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
173 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
174 MMIO_WRITE( PVR2, reg, val );
175 /* I don't want to hear about these */
179 INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val,
180 MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
184 pvr2_irq_vpos1 = (val >> 16) & 0x03FF;
185 pvr2_irq_vpos2 = val & 0x03FF;
188 if( val & 0x80000000 )
192 if( val == 0xFFFFFFFF )
196 MMIO_WRITE( PVR2, reg, val );
199 MMIO_REGION_READ_FN( PVR2, reg )
203 return sh4r.icount&0x20 ? 0x2000 : 1;
205 return MMIO_READ( PVR2, reg );
209 MMIO_REGION_DEFFNS( PVR2PAL )
211 void pvr2_set_base_address( uint32_t base )
213 mmio_region_PVR2_write( DISPADDR1, base );
219 int32_t mmio_region_PVR2TA_read( uint32_t reg )
224 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
226 pvr2_ta_write( &val, sizeof(uint32_t) );
230 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
232 int bank_flag = (destaddr & 0x04) >> 2;
237 destaddr = destaddr & 0x7FFFFF;
238 if( destaddr + length > 0x800000 ) {
239 length = 0x800000 - destaddr;
242 for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
243 texcache_invalidate_page( i );
246 banks[0] = ((uint32_t *)(video_base + (destaddr>>3)));
247 banks[1] = banks[0] + 0x100000;
249 /* Handle non-aligned start of source */
250 if( destaddr & 0x03 ) {
251 char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
252 for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
255 bank_flag = !bank_flag;
258 dwsrc = (uint32_t *)src;
259 while( length >= 4 ) {
260 *banks[bank_flag]++ = *dwsrc++;
261 bank_flag = !bank_flag;
265 /* Handle non-aligned end of source */
268 char *dest = (char *)banks[bank_flag];
269 while( length-- > 0 ) {
276 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
278 int bank_flag = (srcaddr & 0x04) >> 2;
283 srcaddr = srcaddr & 0x7FFFFF;
284 if( srcaddr + length > 0x800000 )
285 length = 0x800000 - srcaddr;
287 banks[0] = ((uint32_t *)(video_base + (srcaddr>>3)));
288 banks[1] = banks[0] + 0x100000;
290 /* Handle non-aligned start of source */
291 if( srcaddr & 0x03 ) {
292 char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
293 for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
296 bank_flag = !bank_flag;
299 dwdest = (uint32_t *)dest;
300 while( length >= 4 ) {
301 *dwdest++ = *banks[bank_flag]++;
302 bank_flag = !bank_flag;
306 /* Handle non-aligned end of source */
308 dest = (char *)dwdest;
309 char *src = (char *)banks[bank_flag];
310 while( length-- > 0 ) {
.