4 * SH4 parent module for all CPU modes and SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "dreamcast.h"
24 #include "sh4/sh4core.h"
25 #include "sh4/sh4mmio.h"
27 #include "sh4/xltcache.h"
28 #include "sh4/sh4stat.h"
33 void sh4_init( void );
34 void sh4_xlat_init( void );
35 void sh4_reset( void );
36 void sh4_start( void );
37 void sh4_stop( void );
38 void sh4_save_state( FILE *f );
39 int sh4_load_state( FILE *f );
41 uint32_t sh4_run_slice( uint32_t );
42 uint32_t sh4_xlat_run_slice( uint32_t );
44 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
45 NULL, sh4_run_slice, sh4_stop,
46 sh4_save_state, sh4_load_state };
48 struct sh4_registers sh4r;
49 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
50 int sh4_breakpoint_count = 0;
51 sh4ptr_t sh4_main_ram;
52 static gboolean sh4_use_translator = FALSE;
53 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
55 void sh4_set_use_xlat( gboolean use )
57 // No-op if the translator was not built
62 sh4_module.run_time_slice = sh4_xlat_run_slice;
64 sh4_module.run_time_slice = sh4_run_slice;
66 sh4_use_translator = use;
70 gboolean sh4_is_using_xlat()
72 return sh4_use_translator;
77 register_io_regions( mmio_list_sh4mmio );
78 sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
85 if( sh4_use_translator ) {
89 /* zero everything out, for the sake of having a consistent state. */
90 memset( &sh4r, 0, sizeof(sh4r) );
92 /* Resume running if we were halted */
93 sh4r.sh4_state = SH4_STATE_RUNNING;
96 sh4r.new_pc= 0xA0000002;
97 sh4r.vbr = 0x00000000;
98 sh4r.fpscr = 0x00040001;
100 sh4r.fr_bank = &sh4r.fr[0][0];
102 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
103 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
105 /* Peripheral modules */
116 if( sh4_use_translator ) {
117 /* If we were running with the translator, update new_pc and in_delay_slot */
118 sh4r.new_pc = sh4r.pc+2;
119 sh4r.in_delay_slot = FALSE;
124 void sh4_save_state( FILE *f )
126 if( sh4_use_translator ) {
127 /* If we were running with the translator, update new_pc and in_delay_slot */
128 sh4r.new_pc = sh4r.pc+2;
129 sh4r.in_delay_slot = FALSE;
132 fwrite( &sh4r, sizeof(sh4r), 1, f );
134 INTC_save_state( f );
136 SCIF_save_state( f );
139 int sh4_load_state( FILE * f )
141 if( sh4_use_translator ) {
144 fread( &sh4r, sizeof(sh4r), 1, f );
145 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
147 INTC_load_state( f );
149 return SCIF_load_state( f );
153 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
155 sh4_breakpoints[sh4_breakpoint_count].address = pc;
156 sh4_breakpoints[sh4_breakpoint_count].type = type;
157 sh4_breakpoint_count++;
160 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
164 for( i=0; i<sh4_breakpoint_count; i++ ) {
165 if( sh4_breakpoints[i].address == pc &&
166 sh4_breakpoints[i].type == type ) {
167 while( ++i < sh4_breakpoint_count ) {
168 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
169 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
171 sh4_breakpoint_count--;
178 int sh4_get_breakpoint( uint32_t pc )
181 for( i=0; i<sh4_breakpoint_count; i++ ) {
182 if( sh4_breakpoints[i].address == pc )
183 return sh4_breakpoints[i].type;
188 void sh4_set_pc( int pc )
195 /******************************* Support methods ***************************/
197 static void sh4_switch_banks( )
201 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
202 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
203 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
206 void sh4_write_sr( uint32_t newval )
208 int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
209 int newbank = (newval&SR_MDRB) == SR_MDRB;
210 if( oldbank != newbank )
213 sh4r.t = (newval&SR_T) ? 1 : 0;
214 sh4r.s = (newval&SR_S) ? 1 : 0;
215 sh4r.m = (newval&SR_M) ? 1 : 0;
216 sh4r.q = (newval&SR_Q) ? 1 : 0;
220 uint32_t sh4_read_sr( void )
222 /* synchronize sh4r.sr with the various bitflags */
223 sh4r.sr &= SR_MQSTMASK;
224 if( sh4r.t ) sh4r.sr |= SR_T;
225 if( sh4r.s ) sh4r.sr |= SR_S;
226 if( sh4r.m ) sh4r.sr |= SR_M;
227 if( sh4r.q ) sh4r.sr |= SR_Q;
233 #define RAISE( x, v ) do{ \
234 if( sh4r.vbr == 0 ) { \
235 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
236 dreamcast_stop(); return FALSE; \
238 sh4r.spc = sh4r.pc; \
239 sh4r.ssr = sh4_read_sr(); \
240 sh4r.sgr = sh4r.r[15]; \
241 MMIO_WRITE(MMU,EXPEVT,x); \
242 sh4r.pc = sh4r.vbr + v; \
243 sh4r.new_pc = sh4r.pc + 2; \
244 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
245 if( sh4r.in_delay_slot ) { \
246 sh4r.in_delay_slot = 0; \
250 return TRUE; } while(0)
253 * Raise a general CPU exception for the specified exception code.
254 * (NOT for TRAPA or TLB exceptions)
256 gboolean sh4_raise_exception( int code )
258 RAISE( code, EXV_EXCEPTION );
262 * Raise a CPU reset exception with the specified exception code.
264 gboolean sh4_raise_reset( int code )
266 // FIXME: reset modules as per "manual reset"
268 MMIO_WRITE(MMU,EXPEVT,code);
270 sh4r.pc = 0xA0000000;
271 sh4r.new_pc = sh4r.pc + 2;
272 sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
276 gboolean sh4_raise_trap( int trap )
278 MMIO_WRITE( MMU, TRA, trap<<2 );
279 return sh4_raise_exception( EXC_TRAP );
282 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
283 if( sh4r.in_delay_slot ) {
284 return sh4_raise_exception(slot_code);
286 return sh4_raise_exception(normal_code);
290 gboolean sh4_raise_tlb_exception( int code )
292 RAISE( code, EXV_TLBMISS );
295 void sh4_accept_interrupt( void )
297 uint32_t code = intc_accept_interrupt();
298 sh4r.ssr = sh4_read_sr();
300 sh4r.sgr = sh4r.r[15];
301 sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
302 MMIO_WRITE( MMU, INTEVT, code );
303 sh4r.pc = sh4r.vbr + 0x600;
304 sh4r.new_pc = sh4r.pc + 2;
305 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
308 void signsat48( void )
310 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
311 sh4r.mac = 0xFFFF800000000000LL;
312 else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
313 sh4r.mac = 0x00007FFFFFFFFFFFLL;
316 void sh4_fsca( uint32_t anglei, float *fr )
318 float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
325 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
326 sh4r.sh4_state = SH4_STATE_STANDBY;
328 sh4r.sh4_state = SH4_STATE_SLEEP;
333 * Compute the matrix tranform of fv given the matrix xf.
334 * Both fv and xf are word-swapped as per the sh4r.fr banks
336 void sh4_ftrv( float *target, float *xf )
338 float fv[4] = { target[1], target[0], target[3], target[2] };
339 target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
340 xf[9]*fv[2] + xf[13]*fv[3];
341 target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
342 xf[8]*fv[2] + xf[12]*fv[3];
343 target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
344 xf[11]*fv[2] + xf[15]*fv[3];
345 target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
346 xf[10]*fv[2] + xf[14]*fv[3];
.