lxdream.org :: lxdream/src/sh4/sh4core.c r367:9c52dcbad3fb

tree revision 367:9c52dcbad3fb

filename	src/sh4/sh4core.c
changeset	367:9c52dcbad3fb
prev	359:c588dce7ebde
next	369:4b4223e7d720
author	nkeynes
date	Tue Sep 04 08:38:33 2007 +0000 (16 years ago)
permissions	-rw-r--r--
last change	Move EXC_* codes to sh4core.h and rename to match the EX_* codes

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     1 /**

     2  * $Id: sh4core.c,v 1.42 2007-09-04 08:38:33 nkeynes Exp $

     3  *

     4  * SH4 emulation core, and parent module for all the SH4 peripheral

     5  * modules.

     6  *

     7  * Copyright (c) 2005 Nathan Keynes.

     8  *

     9  * This program is free software; you can redistribute it and/or modify

    10  * it under the terms of the GNU General Public License as published by

    11  * the Free Software Foundation; either version 2 of the License, or

    12  * (at your option) any later version.

    13  *

    14  * This program is distributed in the hope that it will be useful,

    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  * GNU General Public License for more details.

    18  */

    20 #define MODULE sh4_module

    21 #include <math.h>

    22 #include "dream.h"

    23 #include "sh4/sh4core.h"

    24 #include "sh4/sh4mmio.h"

    25 #include "sh4/intc.h"

    26 #include "mem.h"

    27 #include "clock.h"

    28 #include "syscall.h"

    30 #define SH4_CALLTRACE 1

    32 #define MAX_INT 0x7FFFFFFF

    33 #define MIN_INT 0x80000000

    34 #define MAX_INTF 2147483647.0

    35 #define MIN_INTF -2147483648.0

    37 #define EXV_EXCEPTION    0x100  /* General exception vector */

    38 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */

    39 #define EXV_INTERRUPT    0x600  /* External interrupt vector */

    41 /********************** SH4 Module Definition ****************************/

    43 void sh4_init( void );

    44 void sh4_reset( void );

    45 uint32_t sh4_run_slice( uint32_t );

    46 void sh4_start( void );

    47 void sh4_stop( void );

    48 void sh4_save_state( FILE *f );

    49 int sh4_load_state( FILE *f );

    50 void sh4_accept_interrupt( void );

    52 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,

    53 				       NULL, sh4_run_slice, sh4_stop,

    54 				       sh4_save_state, sh4_load_state };

    56 struct sh4_registers sh4r;

    58 void sh4_init(void)

    59 {

    60     register_io_regions( mmio_list_sh4mmio );

    61     MMU_init();

    62     sh4_reset();

    63 }

    65 void sh4_reset(void)

    66 {

    67     /* zero everything out, for the sake of having a consistent state. */

    68     memset( &sh4r, 0, sizeof(sh4r) );

    70     /* Resume running if we were halted */

    71     sh4r.sh4_state = SH4_STATE_RUNNING;

    73     sh4r.pc    = 0xA0000000;

    74     sh4r.new_pc= 0xA0000002;

    75     sh4r.vbr   = 0x00000000;

    76     sh4r.fpscr = 0x00040001;

    77     sh4r.sr    = 0x700000F0;

    79     /* Mem reset will do this, but if we want to reset _just_ the SH4... */

    80     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );

    82     /* Peripheral modules */

    83     CPG_reset();

    84     INTC_reset();

    85     MMU_reset();

    86     TMU_reset();

    87     SCIF_reset();

    88 }

    90 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];

    91 static int sh4_breakpoint_count = 0;

    92 static uint16_t *sh4_icache = NULL;

    93 static uint32_t sh4_icache_addr = 0;

    95 void sh4_set_breakpoint( uint32_t pc, int type )

    96 {

    97     sh4_breakpoints[sh4_breakpoint_count].address = pc;

    98     sh4_breakpoints[sh4_breakpoint_count].type = type;

    99     sh4_breakpoint_count++;

   100 }

   102 gboolean sh4_clear_breakpoint( uint32_t pc, int type )

   103 {

   104     int i;

   106     for( i=0; i<sh4_breakpoint_count; i++ ) {

   107 	if( sh4_breakpoints[i].address == pc &&

   108 	    sh4_breakpoints[i].type == type ) {

   109 	    while( ++i < sh4_breakpoint_count ) {

   110 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;

   111 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;

   112 	    }

   113 	    sh4_breakpoint_count--;

   114 	    return TRUE;

   115 	}

   116     }

   117     return FALSE;

   118 }

   120 int sh4_get_breakpoint( uint32_t pc )

   121 {

   122     int i;

   123     for( i=0; i<sh4_breakpoint_count; i++ ) {

   124 	if( sh4_breakpoints[i].address == pc )

   125 	    return sh4_breakpoints[i].type;

   126     }

   127     return 0;

   128 }

   130 uint32_t sh4_run_slice( uint32_t nanosecs )

   131 {

   132     int i;

   133     sh4r.slice_cycle = 0;

   135     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {

   136 	if( sh4r.event_pending < nanosecs ) {

   137 	    sh4r.sh4_state = SH4_STATE_RUNNING;

   138 	    sh4r.slice_cycle = sh4r.event_pending;

   139 	}

   140     }

   142     if( sh4_breakpoint_count == 0 ) {

   143 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

   144 	    if( SH4_EVENT_PENDING() ) {

   145 		if( sh4r.event_types & PENDING_EVENT ) {

   146 		    event_execute();

   147 		}

   148 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

   149 		if( sh4r.event_types & PENDING_IRQ ) {

   150 		    sh4_accept_interrupt();

   151 		}

   152 	    }

   153 	    if( !sh4_execute_instruction() ) {

   154 		break;

   155 	    }

   156 	}

   157     } else {

   158 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

   159 	    if( SH4_EVENT_PENDING() ) {

   160 		if( sh4r.event_types & PENDING_EVENT ) {

   161 		    event_execute();

   162 		}

   163 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

   164 		if( sh4r.event_types & PENDING_IRQ ) {

   165 		    sh4_accept_interrupt();

   166 		}

   167 	    }

   169 	    if( !sh4_execute_instruction() )

   170 		break;

   171 #ifdef ENABLE_DEBUG_MODE

   172 	    for( i=0; i<sh4_breakpoint_count; i++ ) {

   173 		if( sh4_breakpoints[i].address == sh4r.pc ) {

   174 		    break;

   175 		}

   176 	    }

   177 	    if( i != sh4_breakpoint_count ) {

   178 		dreamcast_stop();

   179 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )

   180 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );

   181 		break;

   182 	    }

   183 #endif

   184 	}

   185     }

   187     /* If we aborted early, but the cpu is still technically running,

   188      * we're doing a hard abort - cut the timeslice back to what we

   189      * actually executed

   190      */

   191     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {

   192 	nanosecs = sh4r.slice_cycle;

   193     }

   194     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {

   195 	TMU_run_slice( nanosecs );

   196 	SCIF_run_slice( nanosecs );

   197     }

   198     return nanosecs;

   199 }

   201 void sh4_stop(void)

   202 {

   204 }

   206 void sh4_save_state( FILE *f )

   207 {

   208     fwrite( &sh4r, sizeof(sh4r), 1, f );

   209     MMU_save_state( f );

   210     INTC_save_state( f );

   211     TMU_save_state( f );

   212     SCIF_save_state( f );

   213 }

   215 int sh4_load_state( FILE * f )

   216 {

   217     fread( &sh4r, sizeof(sh4r), 1, f );

   218     MMU_load_state( f );

   219     INTC_load_state( f );

   220     TMU_load_state( f );

   221     return SCIF_load_state( f );

   222 }

   224 /********************** SH4 emulation core  ****************************/

   226 void sh4_set_pc( int pc )

   227 {

   228     sh4r.pc = pc;

   229     sh4r.new_pc = pc+2;

   230 }

   232 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)

   233 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)

   235 #if(SH4_CALLTRACE == 1)

   236 #define MAX_CALLSTACK 32

   237 static struct call_stack {

   238     sh4addr_t call_addr;

   239     sh4addr_t target_addr;

   240     sh4addr_t stack_pointer;

   241 } call_stack[MAX_CALLSTACK];

   243 static int call_stack_depth = 0;

   244 int sh4_call_trace_on = 0;

   246 static inline trace_call( sh4addr_t source, sh4addr_t dest )

   247 {

   248     if( call_stack_depth < MAX_CALLSTACK ) {

   249 	call_stack[call_stack_depth].call_addr = source;

   250 	call_stack[call_stack_depth].target_addr = dest;

   251 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];

   252     }

   253     call_stack_depth++;

   254 }

   256 static inline trace_return( sh4addr_t source, sh4addr_t dest )

   257 {

   258     if( call_stack_depth > 0 ) {

   259 	call_stack_depth--;

   260     }

   261 }

   263 void fprint_stack_trace( FILE *f )

   264 {

   265     int i = call_stack_depth -1;

   266     if( i >= MAX_CALLSTACK )

   267 	i = MAX_CALLSTACK - 1;

   268     for( ; i >= 0; i-- ) {

   269 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",

   270 		 (call_stack_depth - i), call_stack[i].call_addr,

   271 		 call_stack[i].target_addr, call_stack[i].stack_pointer );

   272     }

   273 }

   275 #define TRACE_CALL( source, dest ) trace_call(source, dest)

   276 #define TRACE_RETURN( source, dest ) trace_return(source, dest)

   277 #else

   278 #define TRACE_CALL( dest, rts )

   279 #define TRACE_RETURN( source, dest )

   280 #endif

   282 #define RAISE( x, v ) do{			\

   283     if( sh4r.vbr == 0 ) { \

   284         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \

   285         dreamcast_stop(); return FALSE;	\

   286     } else { \

   287         sh4r.spc = sh4r.pc;	\

   288         sh4r.ssr = sh4_read_sr(); \

   289         sh4r.sgr = sh4r.r[15]; \

   290         MMIO_WRITE(MMU,EXPEVT,x); \

   291         sh4r.pc = sh4r.vbr + v; \

   292         sh4r.new_pc = sh4r.pc + 2; \

   293         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \

   294 	if( sh4r.in_delay_slot ) { \

   295 	    sh4r.in_delay_slot = 0; \

   296 	    sh4r.spc -= 2; \

   297 	} \

   298     } \

   299     return TRUE; } while(0)

   301 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)

   302 #define MEM_READ_WORD( addr ) sh4_read_word(addr)

   303 #define MEM_READ_LONG( addr ) sh4_read_long(addr)

   304 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)

   305 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)

   306 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)

   308 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)

   310 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );

   311 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );

   313 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )

   314 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

   315 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

   316 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

   317 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

   319 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }

   320 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }

   321 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)

   323 static void sh4_switch_banks( )

   324 {

   325     uint32_t tmp[8];

   327     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );

   328     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );

   329     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );

   330 }

   332 static void sh4_load_sr( uint32_t newval )

   333 {

   334     if( (newval ^ sh4r.sr) & SR_RB )

   335         sh4_switch_banks();

   336     sh4r.sr = newval;

   337     sh4r.t = (newval&SR_T) ? 1 : 0;

   338     sh4r.s = (newval&SR_S) ? 1 : 0;

   339     sh4r.m = (newval&SR_M) ? 1 : 0;

   340     sh4r.q = (newval&SR_Q) ? 1 : 0;

   341     intc_mask_changed();

   342 }

   344 static void sh4_write_float( uint32_t addr, int reg )

   345 {

   346     if( IS_FPU_DOUBLESIZE() ) {

   347 	if( reg & 1 ) {

   348 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );

   349 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );

   350 	} else {

   351 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) );

   352 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );

   353 	}

   354     } else {

   355 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );

   356     }

   357 }

   359 static void sh4_read_float( uint32_t addr, int reg )

   360 {

   361     if( IS_FPU_DOUBLESIZE() ) {

   362 	if( reg & 1 ) {

   363 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);

   364 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);

   365 	} else {

   366 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);

   367 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);

   368 	}

   369     } else {

   370 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);

   371     }

   372 }

   374 static uint32_t sh4_read_sr( void )

   375 {

   376     /* synchronize sh4r.sr with the various bitflags */

   377     sh4r.sr &= SR_MQSTMASK;

   378     if( sh4r.t ) sh4r.sr |= SR_T;

   379     if( sh4r.s ) sh4r.sr |= SR_S;

   380     if( sh4r.m ) sh4r.sr |= SR_M;

   381     if( sh4r.q ) sh4r.sr |= SR_Q;

   382     return sh4r.sr;

   383 }

   385 /**

   386  * Raise a general CPU exception for the specified exception code.

   387  * (NOT for TRAPA or TLB exceptions)

   388  */

   389 gboolean sh4_raise_exception( int code )

   390 {

   391     RAISE( code, EXV_EXCEPTION );

   392 }

   394 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {

   395     if( sh4r.in_delay_slot ) {

   396 	return sh4_raise_exception(slot_code);

   397     } else {

   398 	return sh4_raise_exception(normal_code);

   399     }

   400 }

   402 gboolean sh4_raise_tlb_exception( int code )

   403 {

   404     RAISE( code, EXV_TLBMISS );

   405 }

   407 void sh4_accept_interrupt( void )

   408 {

   409     uint32_t code = intc_accept_interrupt();

   410     sh4r.ssr = sh4_read_sr();

   411     sh4r.spc = sh4r.pc;

   412     sh4r.sgr = sh4r.r[15];

   413     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );

   414     MMIO_WRITE( MMU, INTEVT, code );

   415     sh4r.pc = sh4r.vbr + 0x600;

   416     sh4r.new_pc = sh4r.pc + 2;

   417     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );

   418 }

   420 gboolean sh4_execute_instruction( void )

   421 {

   422     uint32_t pc;

   423     unsigned short ir;

   424     uint32_t tmp;

   425     float ftmp;

   426     double dtmp;

   428 #define R0 sh4r.r[0]

   429     pc = sh4r.pc;

   430     if( pc > 0xFFFFFF00 ) {

   431 	/* SYSCALL Magic */

   432 	syscall_invoke( pc );

   433 	sh4r.in_delay_slot = 0;

   434 	pc = sh4r.pc = sh4r.pr;

   435 	sh4r.new_pc = sh4r.pc + 2;

   436     }

   437     CHECKRALIGN16(pc);

   439     /* Read instruction */

   440     uint32_t pageaddr = pc >> 12;

   441     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {

   442 	ir = sh4_icache[(pc&0xFFF)>>1];

   443     } else {

   444 	sh4_icache = (uint16_t *)mem_get_page(pc);

   445 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {

   446 	    /* If someone's actually been so daft as to try to execute out of an IO

   447 	     * region, fallback on the full-blown memory read

   448 	     */

   449 	    sh4_icache = NULL;

   450 	    ir = MEM_READ_WORD(pc);

   451 	} else {

   452 	    sh4_icache_addr = pageaddr;

   453 	    ir = sh4_icache[(pc&0xFFF)>>1];

   454 	}

   455     }

   456         switch( (ir&0xF000) >> 12 ) {

   457             case 0x0:

   458                 switch( ir&0xF ) {

   459                     case 0x2:

   460                         switch( (ir&0x80) >> 7 ) {

   461                             case 0x0:

   462                                 switch( (ir&0x70) >> 4 ) {

   463                                     case 0x0:

   464                                         { /* STC SR, Rn */

   465                                         uint32_t Rn = ((ir>>8)&0xF);

   466                                         CHECKPRIV();

   467                                         sh4r.r[Rn] = sh4_read_sr();

   468                                         }

   469                                         break;

   470                                     case 0x1:

   471                                         { /* STC GBR, Rn */

   472                                         uint32_t Rn = ((ir>>8)&0xF);

   473                                         CHECKPRIV();

   474                                         sh4r.r[Rn] = sh4r.gbr;

   475                                         }

   476                                         break;

   477                                     case 0x2:

   478                                         { /* STC VBR, Rn */

   479                                         uint32_t Rn = ((ir>>8)&0xF);

   480                                         CHECKPRIV();

   481                                         sh4r.r[Rn] = sh4r.vbr;

   482                                         }

   483                                         break;

   484                                     case 0x3:

   485                                         { /* STC SSR, Rn */

   486                                         uint32_t Rn = ((ir>>8)&0xF);

   487                                         CHECKPRIV();

   488                                         sh4r.r[Rn] = sh4r.ssr;

   489                                         }

   490                                         break;

   491                                     case 0x4:

   492                                         { /* STC SPC, Rn */

   493                                         uint32_t Rn = ((ir>>8)&0xF);

   494                                         CHECKPRIV();

   495                                         sh4r.r[Rn] = sh4r.spc;

   496                                         }

   497                                         break;

   498                                     default:

   499                                         UNDEF();

   500                                         break;

   501                                 }

   502                                 break;

   503                             case 0x1:

   504                                 { /* STC Rm_BANK, Rn */

   505                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

   506                                 CHECKPRIV();

   507                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];

   508                                 }

   509                                 break;

   510                         }

   511                         break;

   512                     case 0x3:

   513                         switch( (ir&0xF0) >> 4 ) {

   514                             case 0x0:

   515                                 { /* BSRF Rn */

   516                                 uint32_t Rn = ((ir>>8)&0xF);

   517                                 CHECKSLOTILLEGAL();

   518                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );

   519                                 sh4r.in_delay_slot = 1;

   520                                 sh4r.pr = sh4r.pc + 4;

   521                                 sh4r.pc = sh4r.new_pc;

   522                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];

   523                                 TRACE_CALL( pc, sh4r.new_pc );

   524                                 return TRUE;

   525                                 }

   526                                 break;

   527                             case 0x2:

   528                                 { /* BRAF Rn */

   529                                 uint32_t Rn = ((ir>>8)&0xF);

   530                                 CHECKSLOTILLEGAL();

   531                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );

   532                                 sh4r.in_delay_slot = 1;

   533                                 sh4r.pc = sh4r.new_pc;

   534                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];

   535                                 return TRUE;

   536                                 }

   537                                 break;

   538                             case 0x8:

   539                                 { /* PREF @Rn */

   540                                 uint32_t Rn = ((ir>>8)&0xF);

   541                                 tmp = sh4r.r[Rn];

   542                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {

   543                            	 /* Store queue operation */

   544                            	 int queue = (tmp&0x20)>>2;

   545                            	 int32_t *src = &sh4r.store_queue[queue];

   546                            	 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;

   547                            	 uint32_t target = tmp&0x03FFFFE0 | hi;

   548                            	 mem_copy_to_sh4( target, src, 32 );

   549                                 }

   550                                 }

   551                                 break;

   552                             case 0x9:

   553                                 { /* OCBI @Rn */

   554                                 uint32_t Rn = ((ir>>8)&0xF);

   555                                 }

   556                                 break;

   557                             case 0xA:

   558                                 { /* OCBP @Rn */

   559                                 uint32_t Rn = ((ir>>8)&0xF);

   560                                 }

   561                                 break;

   562                             case 0xB:

   563                                 { /* OCBWB @Rn */

   564                                 uint32_t Rn = ((ir>>8)&0xF);

   565                                 }

   566                                 break;

   567                             case 0xC:

   568                                 { /* MOVCA.L R0, @Rn */

   569                                 uint32_t Rn = ((ir>>8)&0xF);

   570                                 tmp = sh4r.r[Rn];

   571                                 CHECKWALIGN32(tmp);

   572                                 MEM_WRITE_LONG( tmp, R0 );

   573                                 }

   574                                 break;

   575                             default:

   576                                 UNDEF();

   577                                 break;

   578                         }

   579                         break;

   580                     case 0x4:

   581                         { /* MOV.B Rm, @(R0, Rn) */

   582                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   583                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   584                         }

   585                         break;

   586                     case 0x5:

   587                         { /* MOV.W Rm, @(R0, Rn) */

   588                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   589                         CHECKWALIGN16( R0 + sh4r.r[Rn] );

   590                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   591                         }

   592                         break;

   593                     case 0x6:

   594                         { /* MOV.L Rm, @(R0, Rn) */

   595                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   596                         CHECKWALIGN32( R0 + sh4r.r[Rn] );

   597                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   598                         }

   599                         break;

   600                     case 0x7:

   601                         { /* MUL.L Rm, Rn */

   602                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   603                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   604                                                (sh4r.r[Rm] * sh4r.r[Rn]);

   605                         }

   606                         break;

   607                     case 0x8:

   608                         switch( (ir&0xFF0) >> 4 ) {

   609                             case 0x0:

   610                                 { /* CLRT */

   611                                 sh4r.t = 0;

   612                                 }

   613                                 break;

   614                             case 0x1:

   615                                 { /* SETT */

   616                                 sh4r.t = 1;

   617                                 }

   618                                 break;

   619                             case 0x2:

   620                                 { /* CLRMAC */

   621                                 sh4r.mac = 0;

   622                                 }

   623                                 break;

   624                             case 0x3:

   625                                 { /* LDTLB */

   626                                 /* TODO */

   627                                 }

   628                                 break;

   629                             case 0x4:

   630                                 { /* CLRS */

   631                                 sh4r.s = 0;

   632                                 }

   633                                 break;

   634                             case 0x5:

   635                                 { /* SETS */

   636                                 sh4r.s = 1;

   637                                 }

   638                                 break;

   639                             default:

   640                                 UNDEF();

   641                                 break;

   642                         }

   643                         break;

   644                     case 0x9:

   645                         switch( (ir&0xF0) >> 4 ) {

   646                             case 0x0:

   647                                 { /* NOP */

   648                                 /* NOP */

   649                                 }

   650                                 break;

   651                             case 0x1:

   652                                 { /* DIV0U */

   653                                 sh4r.m = sh4r.q = sh4r.t = 0;

   654                                 }

   655                                 break;

   656                             case 0x2:

   657                                 { /* MOVT Rn */

   658                                 uint32_t Rn = ((ir>>8)&0xF);

   659                                 sh4r.r[Rn] = sh4r.t;

   660                                 }

   661                                 break;

   662                             default:

   663                                 UNDEF();

   664                                 break;

   665                         }

   666                         break;

   667                     case 0xA:

   668                         switch( (ir&0xF0) >> 4 ) {

   669                             case 0x0:

   670                                 { /* STS MACH, Rn */

   671                                 uint32_t Rn = ((ir>>8)&0xF);

   672                                 sh4r.r[Rn] = (sh4r.mac>>32);

   673                                 }

   674                                 break;

   675                             case 0x1:

   676                                 { /* STS MACL, Rn */

   677                                 uint32_t Rn = ((ir>>8)&0xF);

   678                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;

   679                                 }

   680                                 break;

   681                             case 0x2:

   682                                 { /* STS PR, Rn */

   683                                 uint32_t Rn = ((ir>>8)&0xF);

   684                                 sh4r.r[Rn] = sh4r.pr;

   685                                 }

   686                                 break;

   687                             case 0x3:

   688                                 { /* STC SGR, Rn */

   689                                 uint32_t Rn = ((ir>>8)&0xF);

   690                                 CHECKPRIV();

   691                                 sh4r.r[Rn] = sh4r.sgr;

   692                                 }

   693                                 break;

   694                             case 0x5:

   695                                 { /* STS FPUL, Rn */

   696                                 uint32_t Rn = ((ir>>8)&0xF);

   697                                 sh4r.r[Rn] = sh4r.fpul;

   698                                 }

   699                                 break;

   700                             case 0x6:

   701                                 { /* STS FPSCR, Rn */

   702                                 uint32_t Rn = ((ir>>8)&0xF);

   703                                 sh4r.r[Rn] = sh4r.fpscr;

   704                                 }

   705                                 break;

   706                             case 0xF:

   707                                 { /* STC DBR, Rn */

   708                                 uint32_t Rn = ((ir>>8)&0xF);

   709                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;

   710                                 }

   711                                 break;

   712                             default:

   713                                 UNDEF();

   714                                 break;

   715                         }

   716                         break;

   717                     case 0xB:

   718                         switch( (ir&0xFF0) >> 4 ) {

   719                             case 0x0:

   720                                 { /* RTS */

   721                                 CHECKSLOTILLEGAL();

   722                                 CHECKDEST( sh4r.pr );

   723                                 sh4r.in_delay_slot = 1;

   724                                 sh4r.pc = sh4r.new_pc;

   725                                 sh4r.new_pc = sh4r.pr;

   726                                 TRACE_RETURN( pc, sh4r.new_pc );

   727                                 return TRUE;

   728                                 }

   729                                 break;

   730                             case 0x1:

   731                                 { /* SLEEP */

   732                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {

   733                             	sh4r.sh4_state = SH4_STATE_STANDBY;

   734                                 } else {

   735                             	sh4r.sh4_state = SH4_STATE_SLEEP;

   736                                 }

   737                                 return FALSE; /* Halt CPU */

   738                                 }

   739                                 break;

   740                             case 0x2:

   741                                 { /* RTE */

   742                                 CHECKPRIV();

   743                                 CHECKDEST( sh4r.spc );

   744                                 CHECKSLOTILLEGAL();

   745                                 sh4r.in_delay_slot = 1;

   746                                 sh4r.pc = sh4r.new_pc;

   747                                 sh4r.new_pc = sh4r.spc;

   748                                 sh4_load_sr( sh4r.ssr );

   749                                 return TRUE;

   750                                 }

   751                                 break;

   752                             default:

   753                                 UNDEF();

   754                                 break;

   755                         }

   756                         break;

   757                     case 0xC:

   758                         { /* MOV.B @(R0, Rm), Rn */

   759                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   760                         sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );

   761                         }

   762                         break;

   763                     case 0xD:

   764                         { /* MOV.W @(R0, Rm), Rn */

   765                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   766                         CHECKRALIGN16( R0 + sh4r.r[Rm] );

   767                                            sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );

   768                         }

   769                         break;

   770                     case 0xE:

   771                         { /* MOV.L @(R0, Rm), Rn */

   772                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   773                         CHECKRALIGN32( R0 + sh4r.r[Rm] );

   774                                            sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );

   775                         }

   776                         break;

   777                     case 0xF:

   778                         { /* MAC.L @Rm+, @Rn+ */

   779                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   780                         CHECKRALIGN32( sh4r.r[Rm] );

   781                         CHECKRALIGN32( sh4r.r[Rn] );

   782                         int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));

   783                         sh4r.r[Rn] += 4;

   784                         tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;

   785                         sh4r.r[Rm] += 4;

   786                         if( sh4r.s ) {

   787                             /* 48-bit Saturation. Yuch */

   788                             if( tmpl < (int64_t)0xFFFF800000000000LL )

   789                                 tmpl = 0xFFFF800000000000LL;

   790                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )

   791                                 tmpl = 0x00007FFFFFFFFFFFLL;

   792                         }

   793                         sh4r.mac = tmpl;

   794                         }

   795                         break;

   796                     default:

   797                         UNDEF();

   798                         break;

   799                 }

   800                 break;

   801             case 0x1:

   802                 { /* MOV.L Rm, @(disp, Rn) */

   803                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

   804                 tmp = sh4r.r[Rn] + disp;

   805                 CHECKWALIGN32( tmp );

   806                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );

   807                 }

   808                 break;

   809             case 0x2:

   810                 switch( ir&0xF ) {

   811                     case 0x0:

   812                         { /* MOV.B Rm, @Rn */

   813                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   814                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );

   815                         }

   816                         break;

   817                     case 0x1:

   818                         { /* MOV.W Rm, @Rn */

   819                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   820                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );

   821                         }

   822                         break;

   823                     case 0x2:

   824                         { /* MOV.L Rm, @Rn */

   825                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   826                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );

   827                         }

   828                         break;

   829                     case 0x4:

   830                         { /* MOV.B Rm, @-Rn */

   831                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   832                         sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );

   833                         }

   834                         break;

   835                     case 0x5:

   836                         { /* MOV.W Rm, @-Rn */

   837                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   838                         sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );

   839                         }

   840                         break;

   841                     case 0x6:

   842                         { /* MOV.L Rm, @-Rn */

   843                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   844                         sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );

   845                         }

   846                         break;

   847                     case 0x7:

   848                         { /* DIV0S Rm, Rn */

   849                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   850                         sh4r.q = sh4r.r[Rn]>>31;

   851                         sh4r.m = sh4r.r[Rm]>>31;

   852                         sh4r.t = sh4r.q ^ sh4r.m;

   853                         }

   854                         break;

   855                     case 0x8:

   856                         { /* TST Rm, Rn */

   857                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   858                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);

   859                         }

   860                         break;

   861                     case 0x9:

   862                         { /* AND Rm, Rn */

   863                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   864                         sh4r.r[Rn] &= sh4r.r[Rm];

   865                         }

   866                         break;

   867                     case 0xA:

   868                         { /* XOR Rm, Rn */

   869                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   870                         sh4r.r[Rn] ^= sh4r.r[Rm];

   871                         }

   872                         break;

   873                     case 0xB:

   874                         { /* OR Rm, Rn */

   875                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   876                         sh4r.r[Rn] |= sh4r.r[Rm];

   877                         }

   878                         break;

   879                     case 0xC:

   880                         { /* CMP/STR Rm, Rn */

   881                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   882                         /* set T = 1 if any byte in RM & RN is the same */

   883                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];

   884                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||

   885                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;

   886                         }

   887                         break;

   888                     case 0xD:

   889                         { /* XTRCT Rm, Rn */

   890                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   891                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);

   892                         }

   893                         break;

   894                     case 0xE:

   895                         { /* MULU.W Rm, Rn */

   896                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   897                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   898                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));

   899                         }

   900                         break;

   901                     case 0xF:

   902                         { /* MULS.W Rm, Rn */

   903                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   904                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   905                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));

   906                         }

   907                         break;

   908                     default:

   909                         UNDEF();

   910                         break;

   911                 }

   912                 break;

   913             case 0x3:

   914                 switch( ir&0xF ) {

   915                     case 0x0:

   916                         { /* CMP/EQ Rm, Rn */

   917                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   918                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );

   919                         }

   920                         break;

   921                     case 0x2:

   922                         { /* CMP/HS Rm, Rn */

   923                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   924                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );

   925                         }

   926                         break;

   927                     case 0x3:

   928                         { /* CMP/GE Rm, Rn */

   929                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   930                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

   931                         }

   932                         break;

   933                     case 0x4:

   934                         { /* DIV1 Rm, Rn */

   935                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   936                         /* This is just from the sh4p manual with some

   937                          * simplifications (someone want to check it's correct? :)

   938                          * Why they couldn't just provide a real DIV instruction...

   939                          */

   940                         uint32_t tmp0, tmp1, tmp2, dir;

   942                         dir = sh4r.q ^ sh4r.m;

   943                         sh4r.q = (sh4r.r[Rn] >> 31);

   944                         tmp2 = sh4r.r[Rm];

   945                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;

   946                         tmp0 = sh4r.r[Rn];

   947                         if( dir ) {

   948                              sh4r.r[Rn] += tmp2;

   949                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );

   950                         } else {

   951                              sh4r.r[Rn] -= tmp2;

   952                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );

   953                         }

   954                         sh4r.q ^= sh4r.m ^ tmp1;

   955                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );

   956                         }

   957                         break;

   958                     case 0x5:

   959                         { /* DMULU.L Rm, Rn */

   960                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   961                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);

   962                         }

   963                         break;

   964                     case 0x6:

   965                         { /* CMP/HI Rm, Rn */

   966                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   967                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );

   968                         }

   969                         break;

   970                     case 0x7:

   971                         { /* CMP/GT Rm, Rn */

   972                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   973                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

   974                         }

   975                         break;

   976                     case 0x8:

   977                         { /* SUB Rm, Rn */

   978                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   979                         sh4r.r[Rn] -= sh4r.r[Rm];

   980                         }

   981                         break;

   982                     case 0xA:

   983                         { /* SUBC Rm, Rn */

   984                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   985                         tmp = sh4r.r[Rn];

   986                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;

   987                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));

   988                         }

   989                         break;

   990                     case 0xB:

   991                         UNIMP(ir); /* SUBV Rm, Rn */

   992                         break;

   993                     case 0xC:

   994                         { /* ADD Rm, Rn */

   995                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   996                         sh4r.r[Rn] += sh4r.r[Rm];

   997                         }

   998                         break;

   999                     case 0xD:

  1000                         { /* DMULS.L Rm, Rn */

  1001                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1002                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);

  1003                         }

  1004                         break;

  1005                     case 0xE:

  1006                         { /* ADDC Rm, Rn */

  1007                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1008                         tmp = sh4r.r[Rn];

  1009                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;

  1010                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );

  1011                         }

  1012                         break;

  1013                     case 0xF:

  1014                         { /* ADDV Rm, Rn */

  1015                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1016                         tmp = sh4r.r[Rn] + sh4r.r[Rm];

  1017                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );

  1018                         sh4r.r[Rn] = tmp;

  1019                         }

  1020                         break;

  1021                     default:

  1022                         UNDEF();

  1023                         break;

  1024                 }

  1025                 break;

  1026             case 0x4:

  1027                 switch( ir&0xF ) {

  1028                     case 0x0:

  1029                         switch( (ir&0xF0) >> 4 ) {

  1030                             case 0x0:

  1031                                 { /* SHLL Rn */

  1032                                 uint32_t Rn = ((ir>>8)&0xF);

  1033                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;

  1034                                 }

  1035                                 break;

  1036                             case 0x1:

  1037                                 { /* DT Rn */

  1038                                 uint32_t Rn = ((ir>>8)&0xF);

  1039                                 sh4r.r[Rn] --;

  1040                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );

  1041                                 }

  1042                                 break;

  1043                             case 0x2:

  1044                                 { /* SHAL Rn */

  1045                                 uint32_t Rn = ((ir>>8)&0xF);

  1046                                 sh4r.t = sh4r.r[Rn] >> 31;

  1047                                 sh4r.r[Rn] <<= 1;

  1048                                 }

  1049                                 break;

  1050                             default:

  1051                                 UNDEF();

  1052                                 break;

  1053                         }

  1054                         break;

  1055                     case 0x1:

  1056                         switch( (ir&0xF0) >> 4 ) {

  1057                             case 0x0:

  1058                                 { /* SHLR Rn */

  1059                                 uint32_t Rn = ((ir>>8)&0xF);

  1060                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;

  1061                                 }

  1062                                 break;

  1063                             case 0x1:

  1064                                 { /* CMP/PZ Rn */

  1065                                 uint32_t Rn = ((ir>>8)&0xF);

  1066                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );

  1067                                 }

  1068                                 break;

  1069                             case 0x2:

  1070                                 { /* SHAR Rn */

  1071                                 uint32_t Rn = ((ir>>8)&0xF);

  1072                                 sh4r.t = sh4r.r[Rn] & 0x00000001;

  1073                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;

  1074                                 }

  1075                                 break;

  1076                             default:

  1077                                 UNDEF();

  1078                                 break;

  1079                         }

  1080                         break;

  1081                     case 0x2:

  1082                         switch( (ir&0xF0) >> 4 ) {

  1083                             case 0x0:

  1084                                 { /* STS.L MACH, @-Rn */

  1085                                 uint32_t Rn = ((ir>>8)&0xF);

  1086                                 sh4r.r[Rn] -= 4;

  1087                                 CHECKWALIGN32( sh4r.r[Rn] );

  1088                                 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );

  1089                                 }

  1090                                 break;

  1091                             case 0x1:

  1092                                 { /* STS.L MACL, @-Rn */

  1093                                 uint32_t Rn = ((ir>>8)&0xF);

  1094                                 sh4r.r[Rn] -= 4;

  1095                                 CHECKWALIGN32( sh4r.r[Rn] );

  1096                                 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );

  1097                                 }

  1098                                 break;

  1099                             case 0x2:

  1100                                 { /* STS.L PR, @-Rn */

  1101                                 uint32_t Rn = ((ir>>8)&0xF);

  1102                                 sh4r.r[Rn] -= 4;

  1103                                 CHECKWALIGN32( sh4r.r[Rn] );

  1104                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );

  1105                                 }

  1106                                 break;

  1107                             case 0x3:

  1108                                 { /* STC.L SGR, @-Rn */

  1109                                 uint32_t Rn = ((ir>>8)&0xF);

  1110                                 CHECKPRIV();

  1111                                 sh4r.r[Rn] -= 4;

  1112                                 CHECKWALIGN32( sh4r.r[Rn] );

  1113                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );

  1114                                 }

  1115                                 break;

  1116                             case 0x5:

  1117                                 { /* STS.L FPUL, @-Rn */

  1118                                 uint32_t Rn = ((ir>>8)&0xF);

  1119                                 sh4r.r[Rn] -= 4;

  1120                                 CHECKWALIGN32( sh4r.r[Rn] );

  1121                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );

  1122                                 }

  1123                                 break;

  1124                             case 0x6:

  1125                                 { /* STS.L FPSCR, @-Rn */

  1126                                 uint32_t Rn = ((ir>>8)&0xF);

  1127                                 sh4r.r[Rn] -= 4;

  1128                                 CHECKWALIGN32( sh4r.r[Rn] );

  1129                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );

  1130                                 }

  1131                                 break;

  1132                             case 0xF:

  1133                                 { /* STC.L DBR, @-Rn */

  1134                                 uint32_t Rn = ((ir>>8)&0xF);

  1135                                 CHECKPRIV();

  1136                                 sh4r.r[Rn] -= 4;

  1137                                 CHECKWALIGN32( sh4r.r[Rn] );

  1138                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );

  1139                                 }

  1140                                 break;

  1141                             default:

  1142                                 UNDEF();

  1143                                 break;

  1144                         }

  1145                         break;

  1146                     case 0x3:

  1147                         switch( (ir&0x80) >> 7 ) {

  1148                             case 0x0:

  1149                                 switch( (ir&0x70) >> 4 ) {

  1150                                     case 0x0:

  1151                                         { /* STC.L SR, @-Rn */

  1152                                         uint32_t Rn = ((ir>>8)&0xF);

  1153                                         CHECKPRIV();

  1154                                         sh4r.r[Rn] -= 4;

  1155                                         CHECKWALIGN32( sh4r.r[Rn] );

  1156                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );

  1157                                         }

  1158                                         break;

  1159                                     case 0x1:

  1160                                         { /* STC.L GBR, @-Rn */

  1161                                         uint32_t Rn = ((ir>>8)&0xF);

  1162                                         sh4r.r[Rn] -= 4;

  1163                                         CHECKWALIGN32( sh4r.r[Rn] );

  1164                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );

  1165                                         }

  1166                                         break;

  1167                                     case 0x2:

  1168                                         { /* STC.L VBR, @-Rn */

  1169                                         uint32_t Rn = ((ir>>8)&0xF);

  1170                                         CHECKPRIV();

  1171                                         sh4r.r[Rn] -= 4;

  1172                                         CHECKWALIGN32( sh4r.r[Rn] );

  1173                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );

  1174                                         }

  1175                                         break;

  1176                                     case 0x3:

  1177                                         { /* STC.L SSR, @-Rn */

  1178                                         uint32_t Rn = ((ir>>8)&0xF);

  1179                                         CHECKPRIV();

  1180                                         sh4r.r[Rn] -= 4;

  1181                                         CHECKWALIGN32( sh4r.r[Rn] );

  1182                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );

  1183                                         }

  1184                                         break;

  1185                                     case 0x4:

  1186                                         { /* STC.L SPC, @-Rn */

  1187                                         uint32_t Rn = ((ir>>8)&0xF);

  1188                                         CHECKPRIV();

  1189                                         sh4r.r[Rn] -= 4;

  1190                                         CHECKWALIGN32( sh4r.r[Rn] );

  1191                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );

  1192                                         }

  1193                                         break;

  1194                                     default:

  1195                                         UNDEF();

  1196                                         break;

  1197                                 }

  1198                                 break;

  1199                             case 0x1:

  1200                                 { /* STC.L Rm_BANK, @-Rn */

  1201                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

  1202                                 CHECKPRIV();

  1203                                 sh4r.r[Rn] -= 4;

  1204                                 CHECKWALIGN32( sh4r.r[Rn] );

  1205                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );

  1206                                 }

  1207                                 break;

  1208                         }

  1209                         break;

  1210                     case 0x4:

  1211                         switch( (ir&0xF0) >> 4 ) {

  1212                             case 0x0:

  1213                                 { /* ROTL Rn */

  1214                                 uint32_t Rn = ((ir>>8)&0xF);

  1215                                 sh4r.t = sh4r.r[Rn] >> 31;

  1216                                 sh4r.r[Rn] <<= 1;

  1217                                 sh4r.r[Rn] |= sh4r.t;

  1218                                 }

  1219                                 break;

  1220                             case 0x2:

  1221                                 { /* ROTCL Rn */

  1222                                 uint32_t Rn = ((ir>>8)&0xF);

  1223                                 tmp = sh4r.r[Rn] >> 31;

  1224                                 sh4r.r[Rn] <<= 1;

  1225                                 sh4r.r[Rn] |= sh4r.t;

  1226                                 sh4r.t = tmp;

  1227                                 }

  1228                                 break;

  1229                             default:

  1230                                 UNDEF();

  1231                                 break;

  1232                         }

  1233                         break;

  1234                     case 0x5:

  1235                         switch( (ir&0xF0) >> 4 ) {

  1236                             case 0x0:

  1237                                 { /* ROTR Rn */

  1238                                 uint32_t Rn = ((ir>>8)&0xF);

  1239                                 sh4r.t = sh4r.r[Rn] & 0x00000001;

  1240                                 sh4r.r[Rn] >>= 1;

  1241                                 sh4r.r[Rn] |= (sh4r.t << 31);

  1242                                 }

  1243                                 break;

  1244                             case 0x1:

  1245                                 { /* CMP/PL Rn */

  1246                                 uint32_t Rn = ((ir>>8)&0xF);

  1247                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );

  1248                                 }

  1249                                 break;

  1250                             case 0x2:

  1251                                 { /* ROTCR Rn */

  1252                                 uint32_t Rn = ((ir>>8)&0xF);

  1253                                 tmp = sh4r.r[Rn] & 0x00000001;

  1254                                 sh4r.r[Rn] >>= 1;

  1255                                 sh4r.r[Rn] |= (sh4r.t << 31 );

  1256                                 sh4r.t = tmp;

  1257                                 }

  1258                                 break;

  1259                             default:

  1260                                 UNDEF();

  1261                                 break;

  1262                         }

  1263                         break;

  1264                     case 0x6:

  1265                         switch( (ir&0xF0) >> 4 ) {

  1266                             case 0x0:

  1267                                 { /* LDS.L @Rm+, MACH */

  1268                                 uint32_t Rm = ((ir>>8)&0xF);

  1269                                 CHECKRALIGN32( sh4r.r[Rm] );

  1270                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

  1271                                            (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);

  1272                                 sh4r.r[Rm] += 4;

  1273                                 }

  1274                                 break;

  1275                             case 0x1:

  1276                                 { /* LDS.L @Rm+, MACL */

  1277                                 uint32_t Rm = ((ir>>8)&0xF);

  1278                                 CHECKRALIGN32( sh4r.r[Rm] );

  1279                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1280                                            (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));

  1281                                 sh4r.r[Rm] += 4;

  1282                                 }

  1283                                 break;

  1284                             case 0x2:

  1285                                 { /* LDS.L @Rm+, PR */

  1286                                 uint32_t Rm = ((ir>>8)&0xF);

  1287                                 CHECKRALIGN32( sh4r.r[Rm] );

  1288                                 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );

  1289                                 sh4r.r[Rm] += 4;

  1290                                 }

  1291                                 break;

  1292                             case 0x3:

  1293                                 { /* LDC.L @Rm+, SGR */

  1294                                 uint32_t Rm = ((ir>>8)&0xF);

  1295                                 CHECKPRIV();

  1296                                 CHECKRALIGN32( sh4r.r[Rm] );

  1297                                 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);

  1298                                 sh4r.r[Rm] +=4;

  1299                                 }

  1300                                 break;

  1301                             case 0x5:

  1302                                 { /* LDS.L @Rm+, FPUL */

  1303                                 uint32_t Rm = ((ir>>8)&0xF);

  1304                                 CHECKRALIGN32( sh4r.r[Rm] );

  1305                                 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);

  1306                                 sh4r.r[Rm] +=4;

  1307                                 }

  1308                                 break;

  1309                             case 0x6:

  1310                                 { /* LDS.L @Rm+, FPSCR */

  1311                                 uint32_t Rm = ((ir>>8)&0xF);

  1312                                 CHECKRALIGN32( sh4r.r[Rm] );

  1313                                 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);

  1314                                 sh4r.r[Rm] +=4;

  1315                                 }

  1316                                 break;

  1317                             case 0xF:

  1318                                 { /* LDC.L @Rm+, DBR */

  1319                                 uint32_t Rm = ((ir>>8)&0xF);

  1320                                 CHECKPRIV();

  1321                                 CHECKRALIGN32( sh4r.r[Rm] );

  1322                                 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);

  1323                                 sh4r.r[Rm] +=4;

  1324                                 }

  1325                                 break;

  1326                             default:

  1327                                 UNDEF();

  1328                                 break;

  1329                         }

  1330                         break;

  1331                     case 0x7:

  1332                         switch( (ir&0x80) >> 7 ) {

  1333                             case 0x0:

  1334                                 switch( (ir&0x70) >> 4 ) {

  1335                                     case 0x0:

  1336                                         { /* LDC.L @Rm+, SR */

  1337                                         uint32_t Rm = ((ir>>8)&0xF);

  1338                                         CHECKSLOTILLEGAL();

  1339                                         CHECKPRIV();

  1340                                         CHECKWALIGN32( sh4r.r[Rm] );

  1341                                         sh4_load_sr( MEM_READ_LONG(sh4r.r[Rm]) );

  1342                                         sh4r.r[Rm] +=4;

  1343                                         }

  1344                                         break;

  1345                                     case 0x1:

  1346                                         { /* LDC.L @Rm+, GBR */

  1347                                         uint32_t Rm = ((ir>>8)&0xF);

  1348                                         CHECKRALIGN32( sh4r.r[Rm] );

  1349                                         sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);

  1350                                         sh4r.r[Rm] +=4;

  1351                                         }

  1352                                         break;

  1353                                     case 0x2:

  1354                                         { /* LDC.L @Rm+, VBR */

  1355                                         uint32_t Rm = ((ir>>8)&0xF);

  1356                                         CHECKPRIV();

  1357                                         CHECKRALIGN32( sh4r.r[Rm] );

  1358                                         sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);

  1359                                         sh4r.r[Rm] +=4;

  1360                                         }

  1361                                         break;

  1362                                     case 0x3:

  1363                                         { /* LDC.L @Rm+, SSR */

  1364                                         uint32_t Rm = ((ir>>8)&0xF);

  1365                                         CHECKPRIV();

  1366                                         CHECKRALIGN32( sh4r.r[Rm] );

  1367                                         sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);

  1368                                         sh4r.r[Rm] +=4;

  1369                                         }

  1370                                         break;

  1371                                     case 0x4:

  1372                                         { /* LDC.L @Rm+, SPC */

  1373                                         uint32_t Rm = ((ir>>8)&0xF);

  1374                                         CHECKPRIV();

  1375                                         CHECKRALIGN32( sh4r.r[Rm] );

  1376                                         sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);

  1377                                         sh4r.r[Rm] +=4;

  1378                                         }

  1379                                         break;

  1380                                     default:

  1381                                         UNDEF();

  1382                                         break;

  1383                                 }

  1384                                 break;

  1385                             case 0x1:

  1386                                 { /* LDC.L @Rm+, Rn_BANK */

  1387                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1388                                 CHECKPRIV();

  1389                                 CHECKRALIGN32( sh4r.r[Rm] );

  1390                                 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );

  1391                                 sh4r.r[Rm] += 4;

  1392                                 }

  1393                                 break;

  1394                         }

  1395                         break;

  1396                     case 0x8:

  1397                         switch( (ir&0xF0) >> 4 ) {

  1398                             case 0x0:

  1399                                 { /* SHLL2 Rn */

  1400                                 uint32_t Rn = ((ir>>8)&0xF);

  1401                                 sh4r.r[Rn] <<= 2;

  1402                                 }

  1403                                 break;

  1404                             case 0x1:

  1405                                 { /* SHLL8 Rn */

  1406                                 uint32_t Rn = ((ir>>8)&0xF);

  1407                                 sh4r.r[Rn] <<= 8;

  1408                                 }

  1409                                 break;

  1410                             case 0x2:

  1411                                 { /* SHLL16 Rn */

  1412                                 uint32_t Rn = ((ir>>8)&0xF);

  1413                                 sh4r.r[Rn] <<= 16;

  1414                                 }

  1415                                 break;

  1416                             default:

  1417                                 UNDEF();

  1418                                 break;

  1419                         }

  1420                         break;

  1421                     case 0x9:

  1422                         switch( (ir&0xF0) >> 4 ) {

  1423                             case 0x0:

  1424                                 { /* SHLR2 Rn */

  1425                                 uint32_t Rn = ((ir>>8)&0xF);

  1426                                 sh4r.r[Rn] >>= 2;

  1427                                 }

  1428                                 break;

  1429                             case 0x1:

  1430                                 { /* SHLR8 Rn */

  1431                                 uint32_t Rn = ((ir>>8)&0xF);

  1432                                 sh4r.r[Rn] >>= 8;

  1433                                 }

  1434                                 break;

  1435                             case 0x2:

  1436                                 { /* SHLR16 Rn */

  1437                                 uint32_t Rn = ((ir>>8)&0xF);

  1438                                 sh4r.r[Rn] >>= 16;

  1439                                 }

  1440                                 break;

  1441                             default:

  1442                                 UNDEF();

  1443                                 break;

  1444                         }

  1445                         break;

  1446                     case 0xA:

  1447                         switch( (ir&0xF0) >> 4 ) {

  1448                             case 0x0:

  1449                                 { /* LDS Rm, MACH */

  1450                                 uint32_t Rm = ((ir>>8)&0xF);

  1451                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

  1452                                            (((uint64_t)sh4r.r[Rm])<<32);

  1453                                 }

  1454                                 break;

  1455                             case 0x1:

  1456                                 { /* LDS Rm, MACL */

  1457                                 uint32_t Rm = ((ir>>8)&0xF);

  1458                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1459                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));

  1460                                 }

  1461                                 break;

  1462                             case 0x2:

  1463                                 { /* LDS Rm, PR */

  1464                                 uint32_t Rm = ((ir>>8)&0xF);

  1465                                 sh4r.pr = sh4r.r[Rm];

  1466                                 }

  1467                                 break;

  1468                             case 0x3:

  1469                                 { /* LDC Rm, SGR */

  1470                                 uint32_t Rm = ((ir>>8)&0xF);

  1471                                 CHECKPRIV();

  1472                                 sh4r.sgr = sh4r.r[Rm];

  1473                                 }

  1474                                 break;

  1475                             case 0x5:

  1476                                 { /* LDS Rm, FPUL */

  1477                                 uint32_t Rm = ((ir>>8)&0xF);

  1478                                 sh4r.fpul = sh4r.r[Rm];

  1479                                 }

  1480                                 break;

  1481                             case 0x6:

  1482                                 { /* LDS Rm, FPSCR */

  1483                                 uint32_t Rm = ((ir>>8)&0xF);

  1484                                 sh4r.fpscr = sh4r.r[Rm];

  1485                                 }

  1486                                 break;

  1487                             case 0xF:

  1488                                 { /* LDC Rm, DBR */

  1489                                 uint32_t Rm = ((ir>>8)&0xF);

  1490                                 CHECKPRIV();

  1491                                 sh4r.dbr = sh4r.r[Rm];

  1492                                 }

  1493                                 break;

  1494                             default:

  1495                                 UNDEF();

  1496                                 break;

  1497                         }

  1498                         break;

  1499                     case 0xB:

  1500                         switch( (ir&0xF0) >> 4 ) {

  1501                             case 0x0:

  1502                                 { /* JSR @Rn */

  1503                                 uint32_t Rn = ((ir>>8)&0xF);

  1504                                 CHECKDEST( sh4r.r[Rn] );

  1505                                 CHECKSLOTILLEGAL();

  1506                                 sh4r.in_delay_slot = 1;

  1507                                 sh4r.pc = sh4r.new_pc;

  1508                                 sh4r.new_pc = sh4r.r[Rn];

  1509                                 sh4r.pr = pc + 4;

  1510                                 TRACE_CALL( pc, sh4r.new_pc );

  1511                                 return TRUE;

  1512                                 }

  1513                                 break;

  1514                             case 0x1:

  1515                                 { /* TAS.B @Rn */

  1516                                 uint32_t Rn = ((ir>>8)&0xF);

  1517                                 tmp = MEM_READ_BYTE( sh4r.r[Rn] );

  1518                                 sh4r.t = ( tmp == 0 ? 1 : 0 );

  1519                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );

  1520                                 }

  1521                                 break;

  1522                             case 0x2:

  1523                                 { /* JMP @Rn */

  1524                                 uint32_t Rn = ((ir>>8)&0xF);

  1525                                 CHECKDEST( sh4r.r[Rn] );

  1526                                 CHECKSLOTILLEGAL();

  1527                                 sh4r.in_delay_slot = 1;

  1528                                 sh4r.pc = sh4r.new_pc;

  1529                                 sh4r.new_pc = sh4r.r[Rn];

  1530                                 return TRUE;

  1531                                 }

  1532                                 break;

  1533                             default:

  1534                                 UNDEF();

  1535                                 break;

  1536                         }

  1537                         break;

  1538                     case 0xC:

  1539                         { /* SHAD Rm, Rn */

  1540                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1541                         tmp = sh4r.r[Rm];

  1542                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

  1543                         else if( (tmp & 0x1F) == 0 )

  1544                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;

  1545                         else

  1546                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);

  1547                         }

  1548                         break;

  1549                     case 0xD:

  1550                         { /* SHLD Rm, Rn */

  1551                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1552                         tmp = sh4r.r[Rm];

  1553                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

  1554                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;

  1555                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);

  1556                         }

  1557                         break;

  1558                     case 0xE:

  1559                         switch( (ir&0x80) >> 7 ) {

  1560                             case 0x0:

  1561                                 switch( (ir&0x70) >> 4 ) {

  1562                                     case 0x0:

  1563                                         { /* LDC Rm, SR */

  1564                                         uint32_t Rm = ((ir>>8)&0xF);

  1565                                         CHECKSLOTILLEGAL();

  1566                                         CHECKPRIV();

  1567                                         sh4_load_sr( sh4r.r[Rm] );

  1568                                         }

  1569                                         break;

  1570                                     case 0x1:

  1571                                         { /* LDC Rm, GBR */

  1572                                         uint32_t Rm = ((ir>>8)&0xF);

  1573                                         sh4r.gbr = sh4r.r[Rm];

  1574                                         }

  1575                                         break;

  1576                                     case 0x2:

  1577                                         { /* LDC Rm, VBR */

  1578                                         uint32_t Rm = ((ir>>8)&0xF);

  1579                                         CHECKPRIV();

  1580                                         sh4r.vbr = sh4r.r[Rm];

  1581                                         }

  1582                                         break;

  1583                                     case 0x3:

  1584                                         { /* LDC Rm, SSR */

  1585                                         uint32_t Rm = ((ir>>8)&0xF);

  1586                                         CHECKPRIV();

  1587                                         sh4r.ssr = sh4r.r[Rm];

  1588                                         }

  1589                                         break;

  1590                                     case 0x4:

  1591                                         { /* LDC Rm, SPC */

  1592                                         uint32_t Rm = ((ir>>8)&0xF);

  1593                                         CHECKPRIV();

  1594                                         sh4r.spc = sh4r.r[Rm];

  1595                                         }

  1596                                         break;

  1597                                     default:

  1598                                         UNDEF();

  1599                                         break;

  1600                                 }

  1601                                 break;

  1602                             case 0x1:

  1603                                 { /* LDC Rm, Rn_BANK */

  1604                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1605                                 CHECKPRIV();

  1606                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];

  1607                                 }

  1608                                 break;

  1609                         }

  1610                         break;

  1611                     case 0xF:

  1612                         { /* MAC.W @Rm+, @Rn+ */

  1613                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1614                         CHECKRALIGN16( sh4r.r[Rn] );

  1615                         CHECKRALIGN16( sh4r.r[Rm] );

  1616                         int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));

  1617                         sh4r.r[Rn] += 2;

  1618                         stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));

  1619                         sh4r.r[Rm] += 2;

  1620                         if( sh4r.s ) {

  1621                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;

  1622                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {

  1623                     	    sh4r.mac = 0x000000017FFFFFFFLL;

  1624                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {

  1625                     	    sh4r.mac = 0x0000000180000000LL;

  1626                     	} else {

  1627                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1628                     		((uint32_t)(sh4r.mac + stmp));

  1629                     	}

  1630                         } else {

  1631                     	sh4r.mac += SIGNEXT32(stmp);

  1632                         }

  1633                         }

  1634                         break;

  1635                 }

  1636                 break;

  1637             case 0x5:

  1638                 { /* MOV.L @(disp, Rm), Rn */

  1639                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

  1640                 tmp = sh4r.r[Rm] + disp;

  1641                 CHECKRALIGN32( tmp );

  1642                 sh4r.r[Rn] = MEM_READ_LONG( tmp );

  1643                 }

  1644                 break;

  1645             case 0x6:

  1646                 switch( ir&0xF ) {

  1647                     case 0x0:

  1648                         { /* MOV.B @Rm, Rn */

  1649                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1650                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] );

  1651                         }

  1652                         break;

  1653                     case 0x1:

  1654                         { /* MOV.W @Rm, Rn */

  1655                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1656                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] );

  1657                         }

  1658                         break;

  1659                     case 0x2:

  1660                         { /* MOV.L @Rm, Rn */

  1661                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1662                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] );

  1663                         }

  1664                         break;

  1665                     case 0x3:

  1666                         { /* MOV Rm, Rn */

  1667                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1668                         sh4r.r[Rn] = sh4r.r[Rm];

  1669                         }

  1670                         break;

  1671                     case 0x4:

  1672                         { /* MOV.B @Rm+, Rn */

  1673                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1674                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++;

  1675                         }

  1676                         break;

  1677                     case 0x5:

  1678                         { /* MOV.W @Rm+, Rn */

  1679                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1680                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2;

  1681                         }

  1682                         break;

  1683                     case 0x6:

  1684                         { /* MOV.L @Rm+, Rn */

  1685                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1686                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4;

  1687                         }

  1688                         break;

  1689                     case 0x7:

  1690                         { /* NOT Rm, Rn */

  1691                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1692                         sh4r.r[Rn] = ~sh4r.r[Rm];

  1693                         }

  1694                         break;

  1695                     case 0x8:

  1696                         { /* SWAP.B Rm, Rn */

  1697                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1698                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);

  1699                         }

  1700                         break;

  1701                     case 0x9:

  1702                         { /* SWAP.W Rm, Rn */

  1703                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1704                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);

  1705                         }

  1706                         break;

  1707                     case 0xA:

  1708                         { /* NEGC Rm, Rn */

  1709                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1710                         tmp = 0 - sh4r.r[Rm];

  1711                         sh4r.r[Rn] = tmp - sh4r.t;

  1712                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );

  1713                         }

  1714                         break;

  1715                     case 0xB:

  1716                         { /* NEG Rm, Rn */

  1717                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1718                         sh4r.r[Rn] = 0 - sh4r.r[Rm];

  1719                         }

  1720                         break;

  1721                     case 0xC:

  1722                         { /* EXTU.B Rm, Rn */

  1723                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1724                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;

  1725                         }

  1726                         break;

  1727                     case 0xD:

  1728                         { /* EXTU.W Rm, Rn */

  1729                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1730                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;

  1731                         }

  1732                         break;

  1733                     case 0xE:

  1734                         { /* EXTS.B Rm, Rn */

  1735                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1736                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );

  1737                         }

  1738                         break;

  1739                     case 0xF:

  1740                         { /* EXTS.W Rm, Rn */

  1741                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1742                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );

  1743                         }

  1744                         break;

  1745                 }

  1746                 break;

  1747             case 0x7:

  1748                 { /* ADD #imm, Rn */

  1749                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1750                 sh4r.r[Rn] += imm;

  1751                 }

  1752                 break;

  1753             case 0x8:

  1754                 switch( (ir&0xF00) >> 8 ) {

  1755                     case 0x0:

  1756                         { /* MOV.B R0, @(disp, Rn) */

  1757                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1758                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );

  1759                         }

  1760                         break;

  1761                     case 0x1:

  1762                         { /* MOV.W R0, @(disp, Rn) */

  1763                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1764                         tmp = sh4r.r[Rn] + disp;

  1765                         CHECKWALIGN16( tmp );

  1766                         MEM_WRITE_WORD( tmp, R0 );

  1767                         }

  1768                         break;

  1769                     case 0x4:

  1770                         { /* MOV.B @(disp, Rm), R0 */

  1771                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1772                         R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp );

  1773                         }

  1774                         break;

  1775                     case 0x5:

  1776                         { /* MOV.W @(disp, Rm), R0 */

  1777                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1778                         tmp = sh4r.r[Rm] + disp;

  1779                         CHECKRALIGN16( tmp );

  1780                         R0 = MEM_READ_WORD( tmp );

  1781                         }

  1782                         break;

  1783                     case 0x8:

  1784                         { /* CMP/EQ #imm, R0 */

  1785                         int32_t imm = SIGNEXT8(ir&0xFF);

  1786                         sh4r.t = ( R0 == imm ? 1 : 0 );

  1787                         }

  1788                         break;

  1789                     case 0x9:

  1790                         { /* BT disp */

  1791                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1792                         CHECKSLOTILLEGAL();

  1793                         if( sh4r.t ) {

  1794                             CHECKDEST( sh4r.pc + disp + 4 )

  1795                             sh4r.pc += disp + 4;

  1796                             sh4r.new_pc = sh4r.pc + 2;

  1797                             return TRUE;

  1798                         }

  1799                         }

  1800                         break;

  1801                     case 0xB:

  1802                         { /* BF disp */

  1803                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1804                         CHECKSLOTILLEGAL();

  1805                         if( !sh4r.t ) {

  1806                             CHECKDEST( sh4r.pc + disp + 4 )

  1807                             sh4r.pc += disp + 4;

  1808                             sh4r.new_pc = sh4r.pc + 2;

  1809                             return TRUE;

  1810                         }

  1811                         }

  1812                         break;

  1813                     case 0xD:

  1814                         { /* BT/S disp */

  1815                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1816                         CHECKSLOTILLEGAL();

  1817                         if( sh4r.t ) {

  1818                             CHECKDEST( sh4r.pc + disp + 4 )

  1819                             sh4r.in_delay_slot = 1;

  1820                             sh4r.pc = sh4r.new_pc;

  1821                             sh4r.new_pc = pc + disp + 4;

  1822                             sh4r.in_delay_slot = 1;

  1823                             return TRUE;

  1824                         }

  1825                         }

  1826                         break;

  1827                     case 0xF:

  1828                         { /* BF/S disp */

  1829                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1830                         CHECKSLOTILLEGAL();

  1831                         if( !sh4r.t ) {

  1832                             CHECKDEST( sh4r.pc + disp + 4 )

  1833                             sh4r.in_delay_slot = 1;

  1834                             sh4r.pc = sh4r.new_pc;

  1835                             sh4r.new_pc = pc + disp + 4;

  1836                             return TRUE;

  1837                         }

  1838                         }

  1839                         break;

  1840                     default:

  1841                         UNDEF();

  1842                         break;

  1843                 }

  1844                 break;

  1845             case 0x9:

  1846                 { /* MOV.W @(disp, PC), Rn */

  1847                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;

  1848                 CHECKSLOTILLEGAL();

  1849                 tmp = pc + 4 + disp;

  1850                 sh4r.r[Rn] = MEM_READ_WORD( tmp );

  1851                 }

  1852                 break;

  1853             case 0xA:

  1854                 { /* BRA disp */

  1855                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1856                 CHECKSLOTILLEGAL();

  1857                 CHECKDEST( sh4r.pc + disp + 4 );

  1858                 sh4r.in_delay_slot = 1;

  1859                 sh4r.pc = sh4r.new_pc;

  1860                 sh4r.new_pc = pc + 4 + disp;

  1861                 return TRUE;

  1862                 }

  1863                 break;

  1864             case 0xB:

  1865                 { /* BSR disp */

  1866                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1867                 CHECKDEST( sh4r.pc + disp + 4 );

  1868                 CHECKSLOTILLEGAL();

  1869                 sh4r.in_delay_slot = 1;

  1870                 sh4r.pr = pc + 4;

  1871                 sh4r.pc = sh4r.new_pc;

  1872                 sh4r.new_pc = pc + 4 + disp;

  1873                 TRACE_CALL( pc, sh4r.new_pc );

  1874                 return TRUE;

  1875                 }

  1876                 break;

  1877             case 0xC:

  1878                 switch( (ir&0xF00) >> 8 ) {

  1879                     case 0x0:

  1880                         { /* MOV.B R0, @(disp, GBR) */

  1881                         uint32_t disp = (ir&0xFF);

  1882                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );

  1883                         }

  1884                         break;

  1885                     case 0x1:

  1886                         { /* MOV.W R0, @(disp, GBR) */

  1887                         uint32_t disp = (ir&0xFF)<<1;

  1888                         tmp = sh4r.gbr + disp;

  1889                         CHECKWALIGN16( tmp );

  1890                         MEM_WRITE_WORD( tmp, R0 );

  1891                         }

  1892                         break;

  1893                     case 0x2:

  1894                         { /* MOV.L R0, @(disp, GBR) */

  1895                         uint32_t disp = (ir&0xFF)<<2;

  1896                         tmp = sh4r.gbr + disp;

  1897                         CHECKWALIGN32( tmp );

  1898                         MEM_WRITE_LONG( tmp, R0 );

  1899                         }

  1900                         break;

  1901                     case 0x3:

  1902                         { /* TRAPA #imm */

  1903                         uint32_t imm = (ir&0xFF);

  1904                         CHECKSLOTILLEGAL();

  1905                         MMIO_WRITE( MMU, TRA, imm<<2 );

  1906                         sh4r.pc += 2;

  1907                         sh4_raise_exception( EXC_TRAP );

  1908                         }

  1909                         break;

  1910                     case 0x4:

  1911                         { /* MOV.B @(disp, GBR), R0 */

  1912                         uint32_t disp = (ir&0xFF);

  1913                         R0 = MEM_READ_BYTE( sh4r.gbr + disp );

  1914                         }

  1915                         break;

  1916                     case 0x5:

  1917                         { /* MOV.W @(disp, GBR), R0 */

  1918                         uint32_t disp = (ir&0xFF)<<1;

  1919                         tmp = sh4r.gbr + disp;

  1920                         CHECKRALIGN16( tmp );

  1921                         R0 = MEM_READ_WORD( tmp );

  1922                         }

  1923                         break;

  1924                     case 0x6:

  1925                         { /* MOV.L @(disp, GBR), R0 */

  1926                         uint32_t disp = (ir&0xFF)<<2;

  1927                         tmp = sh4r.gbr + disp;

  1928                         CHECKRALIGN32( tmp );

  1929                         R0 = MEM_READ_LONG( tmp );

  1930                         }

  1931                         break;

  1932                     case 0x7:

  1933                         { /* MOVA @(disp, PC), R0 */

  1934                         uint32_t disp = (ir&0xFF)<<2;

  1935                         CHECKSLOTILLEGAL();

  1936                         R0 = (pc&0xFFFFFFFC) + disp + 4;

  1937                         }

  1938                         break;

  1939                     case 0x8:

  1940                         { /* TST #imm, R0 */

  1941                         uint32_t imm = (ir&0xFF);

  1942                         sh4r.t = (R0 & imm ? 0 : 1);

  1943                         }

  1944                         break;

  1945                     case 0x9:

  1946                         { /* AND #imm, R0 */

  1947                         uint32_t imm = (ir&0xFF);

  1948                         R0 &= imm;

  1949                         }

  1950                         break;

  1951                     case 0xA:

  1952                         { /* XOR #imm, R0 */

  1953                         uint32_t imm = (ir&0xFF);

  1954                         R0 ^= imm;

  1955                         }

  1956                         break;

  1957                     case 0xB:

  1958                         { /* OR #imm, R0 */

  1959                         uint32_t imm = (ir&0xFF);

  1960                         R0 |= imm;

  1961                         }

  1962                         break;

  1963                     case 0xC:

  1964                         { /* TST.B #imm, @(R0, GBR) */

  1965                         uint32_t imm = (ir&0xFF);

  1966                         sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 );

  1967                         }

  1968                         break;

  1969                     case 0xD:

  1970                         { /* AND.B #imm, @(R0, GBR) */

  1971                         uint32_t imm = (ir&0xFF);

  1972                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) );

  1973                         }

  1974                         break;

  1975                     case 0xE:

  1976                         { /* XOR.B #imm, @(R0, GBR) */

  1977                         uint32_t imm = (ir&0xFF);

  1978                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) );

  1979                         }

  1980                         break;

  1981                     case 0xF:

  1982                         { /* OR.B #imm, @(R0, GBR) */

  1983                         uint32_t imm = (ir&0xFF);

  1984                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) );

  1985                         }

  1986                         break;

  1987                 }

  1988                 break;

  1989             case 0xD:

  1990                 { /* MOV.L @(disp, PC), Rn */

  1991                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;

  1992                 CHECKSLOTILLEGAL();

  1993                 tmp = (pc&0xFFFFFFFC) + disp + 4;

  1994                 sh4r.r[Rn] = MEM_READ_LONG( tmp );

  1995                 }

  1996                 break;

  1997             case 0xE:

  1998                 { /* MOV #imm, Rn */

  1999                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  2000                 sh4r.r[Rn] = imm;

  2001                 }

  2002                 break;

  2003             case 0xF:

  2004                 switch( ir&0xF ) {

  2005                     case 0x0:

  2006                         { /* FADD FRm, FRn */

  2007                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2008                         CHECKFPUEN();

  2009                         if( IS_FPU_DOUBLEPREC() ) {

  2010                     	DR(FRn) += DR(FRm);

  2011                         } else {

  2012                     	FR(FRn) += FR(FRm);

  2013                         }

  2014                         }

  2015                         break;

  2016                     case 0x1:

  2017                         { /* FSUB FRm, FRn */

  2018                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2019                         CHECKFPUEN();

  2020                         if( IS_FPU_DOUBLEPREC() ) {

  2021                     	DR(FRn) -= DR(FRm);

  2022                         } else {

  2023                     	FR(FRn) -= FR(FRm);

  2024                         }

  2025                         }

  2026                         break;

  2027                     case 0x2:

  2028                         { /* FMUL FRm, FRn */

  2029                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2030                         CHECKFPUEN();

  2031                         if( IS_FPU_DOUBLEPREC() ) {

  2032                     	DR(FRn) *= DR(FRm);

  2033                         } else {

  2034                     	FR(FRn) *= FR(FRm);

  2035                         }

  2036                         }

  2037                         break;

  2038                     case 0x3:

  2039                         { /* FDIV FRm, FRn */

  2040                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2041                         CHECKFPUEN();

  2042                         if( IS_FPU_DOUBLEPREC() ) {

  2043                     	DR(FRn) /= DR(FRm);

  2044                         } else {

  2045                     	FR(FRn) /= FR(FRm);

  2046                         }

  2047                         }

  2048                         break;

  2049                     case 0x4:

  2050                         { /* FCMP/EQ FRm, FRn */

  2051                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2052                         CHECKFPUEN();

  2053                         if( IS_FPU_DOUBLEPREC() ) {

  2054                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );

  2055                         } else {

  2056                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );

  2057                         }

  2058                         }

  2059                         break;

  2060                     case 0x5:

  2061                         { /* FCMP/GT FRm, FRn */

  2062                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2063                         CHECKFPUEN();

  2064                         if( IS_FPU_DOUBLEPREC() ) {

  2065                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );

  2066                         } else {

  2067                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );

  2068                         }

  2069                         }

  2070                         break;

  2071                     case 0x6:

  2072                         { /* FMOV @(R0, Rm), FRn */

  2073                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  2074                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );

  2075                         }

  2076                         break;

  2077                     case 0x7:

  2078                         { /* FMOV FRm, @(R0, Rn) */

  2079                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2080                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );

  2081                         }

  2082                         break;

  2083                     case 0x8:

  2084                         { /* FMOV @Rm, FRn */

  2085                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  2086                         MEM_FP_READ( sh4r.r[Rm], FRn );

  2087                         }

  2088                         break;

  2089                     case 0x9:

  2090                         { /* FMOV @Rm+, FRn */

  2091                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  2092                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;

  2093                         }

  2094                         break;

  2095                     case 0xA:

  2096                         { /* FMOV FRm, @Rn */

  2097                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2098                         MEM_FP_WRITE( sh4r.r[Rn], FRm );

  2099                         }

  2100                         break;

  2101                     case 0xB:

  2102                         { /* FMOV FRm, @-Rn */

  2103                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2104                         sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );

  2105                         }

  2106                         break;

  2107                     case 0xC:

  2108                         { /* FMOV FRm, FRn */

  2109                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2110                         if( IS_FPU_DOUBLESIZE() )

  2111                     	DR(FRn) = DR(FRm);

  2112                         else

  2113                     	FR(FRn) = FR(FRm);

  2114                         }

  2115                         break;

  2116                     case 0xD:

  2117                         switch( (ir&0xF0) >> 4 ) {

  2118                             case 0x0:

  2119                                 { /* FSTS FPUL, FRn */

  2120                                 uint32_t FRn = ((ir>>8)&0xF);

  2121                                 CHECKFPUEN(); FR(FRn) = FPULf;

  2122                                 }

  2123                                 break;

  2124                             case 0x1:

  2125                                 { /* FLDS FRm, FPUL */

  2126                                 uint32_t FRm = ((ir>>8)&0xF);

  2127                                 CHECKFPUEN(); FPULf = FR(FRm);

  2128                                 }

  2129                                 break;

  2130                             case 0x2:

  2131                                 { /* FLOAT FPUL, FRn */

  2132                                 uint32_t FRn = ((ir>>8)&0xF);

  2133                                 CHECKFPUEN();

  2134                                 if( IS_FPU_DOUBLEPREC() )

  2135                             	DR(FRn) = (float)FPULi;

  2136                                 else

  2137                             	FR(FRn) = (float)FPULi;

  2138                                 }

  2139                                 break;

  2140                             case 0x3:

  2141                                 { /* FTRC FRm, FPUL */

  2142                                 uint32_t FRm = ((ir>>8)&0xF);

  2143                                 CHECKFPUEN();

  2144                                 if( IS_FPU_DOUBLEPREC() ) {

  2145                                     dtmp = DR(FRm);

  2146                                     if( dtmp >= MAX_INTF )

  2147                                         FPULi = MAX_INT;

  2148                                     else if( dtmp <= MIN_INTF )

  2149                                         FPULi = MIN_INT;

  2150                                     else

  2151                                         FPULi = (int32_t)dtmp;

  2152                                 } else {

  2153                             	ftmp = FR(FRm);

  2154                             	if( ftmp >= MAX_INTF )

  2155                             	    FPULi = MAX_INT;

  2156                             	else if( ftmp <= MIN_INTF )

  2157                             	    FPULi = MIN_INT;

  2158                             	else

  2159                             	    FPULi = (int32_t)ftmp;

  2160                                 }

  2161                                 }

  2162                                 break;

  2163                             case 0x4:

  2164                                 { /* FNEG FRn */

  2165                                 uint32_t FRn = ((ir>>8)&0xF);

  2166                                 CHECKFPUEN();

  2167                                 if( IS_FPU_DOUBLEPREC() ) {

  2168                             	DR(FRn) = -DR(FRn);

  2169                                 } else {

  2170                                     FR(FRn) = -FR(FRn);

  2171                                 }

  2172                                 }

  2173                                 break;

  2174                             case 0x5:

  2175                                 { /* FABS FRn */

  2176                                 uint32_t FRn = ((ir>>8)&0xF);

  2177                                 CHECKFPUEN();

  2178                                 if( IS_FPU_DOUBLEPREC() ) {

  2179                             	DR(FRn) = fabs(DR(FRn));

  2180                                 } else {

  2181                                     FR(FRn) = fabsf(FR(FRn));

  2182                                 }

  2183                                 }

  2184                                 break;

  2185                             case 0x6:

  2186                                 { /* FSQRT FRn */

  2187                                 uint32_t FRn = ((ir>>8)&0xF);

  2188                                 CHECKFPUEN();

  2189                                 if( IS_FPU_DOUBLEPREC() ) {

  2190                             	DR(FRn) = sqrt(DR(FRn));

  2191                                 } else {

  2192                                     FR(FRn) = sqrtf(FR(FRn));

  2193                                 }

  2194                                 }

  2195                                 break;

  2196                             case 0x7:

  2197                                 { /* FSRRA FRn */

  2198                                 uint32_t FRn = ((ir>>8)&0xF);

  2199                                 CHECKFPUEN();

  2200                                 if( !IS_FPU_DOUBLEPREC() ) {

  2201                             	FR(FRn) = 1.0/sqrtf(FR(FRn));

  2202                                 }

  2203                                 }

  2204                                 break;

  2205                             case 0x8:

  2206                                 { /* FLDI0 FRn */

  2207                                 uint32_t FRn = ((ir>>8)&0xF);

  2208                                 CHECKFPUEN();

  2209                                 if( IS_FPU_DOUBLEPREC() ) {

  2210                             	DR(FRn) = 0.0;

  2211                                 } else {

  2212                                     FR(FRn) = 0.0;

  2213                                 }

  2214                                 }

  2215                                 break;

  2216                             case 0x9:

  2217                                 { /* FLDI1 FRn */

  2218                                 uint32_t FRn = ((ir>>8)&0xF);

  2219                                 CHECKFPUEN();

  2220                                 if( IS_FPU_DOUBLEPREC() ) {

  2221                             	DR(FRn) = 1.0;

  2222                                 } else {

  2223                                     FR(FRn) = 1.0;

  2224                                 }

  2225                                 }

  2226                                 break;

  2227                             case 0xA:

  2228                                 { /* FCNVSD FPUL, FRn */

  2229                                 uint32_t FRn = ((ir>>8)&0xF);

  2230                                 CHECKFPUEN();

  2231                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

  2232                             	DR(FRn) = (double)FPULf;

  2233                                 }

  2234                                 }

  2235                                 break;

  2236                             case 0xB:

  2237                                 { /* FCNVDS FRm, FPUL */

  2238                                 uint32_t FRm = ((ir>>8)&0xF);

  2239                                 CHECKFPUEN();

  2240                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

  2241                             	FPULf = (float)DR(FRm);

  2242                                 }

  2243                                 }

  2244                                 break;

  2245                             case 0xE:

  2246                                 { /* FIPR FVm, FVn */

  2247                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);

  2248                                 CHECKFPUEN();

  2249                                 if( !IS_FPU_DOUBLEPREC() ) {

  2250                                     int tmp2 = FVn<<2;

  2251                                     tmp = FVm<<2;

  2252                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +

  2253                                         FR(tmp+1)*FR(tmp2+1) +

  2254                                         FR(tmp+2)*FR(tmp2+2) +

  2255                                         FR(tmp+3)*FR(tmp2+3);

  2256                                 }

  2257                                 }

  2258                                 break;

  2259                             case 0xF:

  2260                                 switch( (ir&0x100) >> 8 ) {

  2261                                     case 0x0:

  2262                                         { /* FSCA FPUL, FRn */

  2263                                         uint32_t FRn = ((ir>>9)&0x7)<<1;

  2264                                         CHECKFPUEN();

  2265                                         if( !IS_FPU_DOUBLEPREC() ) {

  2266                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;

  2267                                             FR(FRn) = sinf(angle);

  2268                                             FR((FRn)+1) = cosf(angle);

  2269                                         }

  2270                                         }

  2271                                         break;

  2272                                     case 0x1:

  2273                                         switch( (ir&0x200) >> 9 ) {

  2274                                             case 0x0:

  2275                                                 { /* FTRV XMTRX, FVn */

  2276                                                 uint32_t FVn = ((ir>>10)&0x3);

  2277                                                 CHECKFPUEN();

  2278                                                 if( !IS_FPU_DOUBLEPREC() ) {

  2279                                                     tmp = FVn<<2;

  2280                                                     float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };

  2281                                                     FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +

  2282                                             	    XF(8)*fv[2] + XF(12)*fv[3];

  2283                                                     FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +

  2284                                             	    XF(9)*fv[2] + XF(13)*fv[3];

  2285                                                     FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +

  2286                                             	    XF(10)*fv[2] + XF(14)*fv[3];

  2287                                                     FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +

  2288                                             	    XF(11)*fv[2] + XF(15)*fv[3];

  2289                                                 }

  2290                                                 }

  2291                                                 break;

  2292                                             case 0x1:

  2293                                                 switch( (ir&0xC00) >> 10 ) {

  2294                                                     case 0x0:

  2295                                                         { /* FSCHG */

  2296                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;

  2297                                                         }

  2298                                                         break;

  2299                                                     case 0x2:

  2300                                                         { /* FRCHG */

  2301                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_FR;

  2302                                                         }

  2303                                                         break;

  2304                                                     case 0x3:

  2305                                                         { /* UNDEF */

  2306                                                         UNDEF(ir);

  2307                                                         }

  2308                                                         break;

  2309                                                     default:

  2310                                                         UNDEF();

  2311                                                         break;

  2312                                                 }

  2313                                                 break;

  2314                                         }

  2315                                         break;

  2316                                 }

  2317                                 break;

  2318                             default:

  2319                                 UNDEF();

  2320                                 break;

  2321                         }

  2322                         break;

  2323                     case 0xE:

  2324                         { /* FMAC FR0, FRm, FRn */

  2325                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2326                         CHECKFPUEN();

  2327                         if( IS_FPU_DOUBLEPREC() ) {

  2328                             DR(FRn) += DR(FRm)*DR(0);

  2329                         } else {

  2330                     	FR(FRn) += FR(FRm)*FR(0);

  2331                         }

  2332                         }

  2333                         break;

  2334                     default:

  2335                         UNDEF();

  2336                         break;

  2337                 }

  2338                 break;

  2339         }

  2341     sh4r.pc = sh4r.new_pc;

  2342     sh4r.new_pc += 2;

  2343     sh4r.in_delay_slot = 0;

  2344     return TRUE;

  2345 }