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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 367:9c52dcbad3fb
prev359:c588dce7ebde
next369:4b4223e7d720
author nkeynes
date Tue Sep 04 08:38:33 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Move EXC_* codes to sh4core.h and rename to match the EX_* codes
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     1 /**
     2  * $Id: sh4core.in,v 1.2 2007-09-04 08:38:33 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 #define EXV_EXCEPTION    0x100  /* General exception vector */
    38 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    39 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    41 /********************** SH4 Module Definition ****************************/
    43 void sh4_init( void );
    44 void sh4_reset( void );
    45 uint32_t sh4_run_slice( uint32_t );
    46 void sh4_start( void );
    47 void sh4_stop( void );
    48 void sh4_save_state( FILE *f );
    49 int sh4_load_state( FILE *f );
    50 void sh4_accept_interrupt( void );
    52 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    53 				       NULL, sh4_run_slice, sh4_stop,
    54 				       sh4_save_state, sh4_load_state };
    56 struct sh4_registers sh4r;
    58 void sh4_init(void)
    59 {
    60     register_io_regions( mmio_list_sh4mmio );
    61     MMU_init();
    62     sh4_reset();
    63 }
    65 void sh4_reset(void)
    66 {
    67     /* zero everything out, for the sake of having a consistent state. */
    68     memset( &sh4r, 0, sizeof(sh4r) );
    70     /* Resume running if we were halted */
    71     sh4r.sh4_state = SH4_STATE_RUNNING;
    73     sh4r.pc    = 0xA0000000;
    74     sh4r.new_pc= 0xA0000002;
    75     sh4r.vbr   = 0x00000000;
    76     sh4r.fpscr = 0x00040001;
    77     sh4r.sr    = 0x700000F0;
    79     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    80     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    82     /* Peripheral modules */
    83     CPG_reset();
    84     INTC_reset();
    85     MMU_reset();
    86     TMU_reset();
    87     SCIF_reset();
    88 }
    90 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    91 static int sh4_breakpoint_count = 0;
    92 static uint16_t *sh4_icache = NULL;
    93 static uint32_t sh4_icache_addr = 0;
    95 void sh4_set_breakpoint( uint32_t pc, int type )
    96 {
    97     sh4_breakpoints[sh4_breakpoint_count].address = pc;
    98     sh4_breakpoints[sh4_breakpoint_count].type = type;
    99     sh4_breakpoint_count++;
   100 }
   102 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   103 {
   104     int i;
   106     for( i=0; i<sh4_breakpoint_count; i++ ) {
   107 	if( sh4_breakpoints[i].address == pc && 
   108 	    sh4_breakpoints[i].type == type ) {
   109 	    while( ++i < sh4_breakpoint_count ) {
   110 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   111 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   112 	    }
   113 	    sh4_breakpoint_count--;
   114 	    return TRUE;
   115 	}
   116     }
   117     return FALSE;
   118 }
   120 int sh4_get_breakpoint( uint32_t pc )
   121 {
   122     int i;
   123     for( i=0; i<sh4_breakpoint_count; i++ ) {
   124 	if( sh4_breakpoints[i].address == pc )
   125 	    return sh4_breakpoints[i].type;
   126     }
   127     return 0;
   128 }
   130 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   131 {
   132     int i;
   133     sh4r.slice_cycle = 0;
   135     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   136 	if( sh4r.event_pending < nanosecs ) {
   137 	    sh4r.sh4_state = SH4_STATE_RUNNING;
   138 	    sh4r.slice_cycle = sh4r.event_pending;
   139 	}
   140     }
   142     if( sh4_breakpoint_count == 0 ) {
   143 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   144 	    if( SH4_EVENT_PENDING() ) {
   145 		if( sh4r.event_types & PENDING_EVENT ) {
   146 		    event_execute();
   147 		}
   148 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   149 		if( sh4r.event_types & PENDING_IRQ ) {
   150 		    sh4_accept_interrupt();
   151 		}
   152 	    }
   153 	    if( !sh4_execute_instruction() ) {
   154 		break;
   155 	    }
   156 	}
   157     } else {
   158 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   159 	    if( SH4_EVENT_PENDING() ) {
   160 		if( sh4r.event_types & PENDING_EVENT ) {
   161 		    event_execute();
   162 		}
   163 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   164 		if( sh4r.event_types & PENDING_IRQ ) {
   165 		    sh4_accept_interrupt();
   166 		}
   167 	    }
   169 	    if( !sh4_execute_instruction() )
   170 		break;
   171 #ifdef ENABLE_DEBUG_MODE
   172 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
   173 		if( sh4_breakpoints[i].address == sh4r.pc ) {
   174 		    break;
   175 		}
   176 	    }
   177 	    if( i != sh4_breakpoint_count ) {
   178 		dreamcast_stop();
   179 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   180 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   181 		break;
   182 	    }
   183 #endif	
   184 	}
   185     }
   187     /* If we aborted early, but the cpu is still technically running,
   188      * we're doing a hard abort - cut the timeslice back to what we
   189      * actually executed
   190      */
   191     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   192 	nanosecs = sh4r.slice_cycle;
   193     }
   194     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   195 	TMU_run_slice( nanosecs );
   196 	SCIF_run_slice( nanosecs );
   197     }
   198     return nanosecs;
   199 }
   201 void sh4_stop(void)
   202 {
   204 }
   206 void sh4_save_state( FILE *f )
   207 {
   208     fwrite( &sh4r, sizeof(sh4r), 1, f );
   209     MMU_save_state( f );
   210     INTC_save_state( f );
   211     TMU_save_state( f );
   212     SCIF_save_state( f );
   213 }
   215 int sh4_load_state( FILE * f )
   216 {
   217     fread( &sh4r, sizeof(sh4r), 1, f );
   218     MMU_load_state( f );
   219     INTC_load_state( f );
   220     TMU_load_state( f );
   221     return SCIF_load_state( f );
   222 }
   224 /********************** SH4 emulation core  ****************************/
   226 void sh4_set_pc( int pc )
   227 {
   228     sh4r.pc = pc;
   229     sh4r.new_pc = pc+2;
   230 }
   232 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   233 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   235 #if(SH4_CALLTRACE == 1)
   236 #define MAX_CALLSTACK 32
   237 static struct call_stack {
   238     sh4addr_t call_addr;
   239     sh4addr_t target_addr;
   240     sh4addr_t stack_pointer;
   241 } call_stack[MAX_CALLSTACK];
   243 static int call_stack_depth = 0;
   244 int sh4_call_trace_on = 0;
   246 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   247 {
   248     if( call_stack_depth < MAX_CALLSTACK ) {
   249 	call_stack[call_stack_depth].call_addr = source;
   250 	call_stack[call_stack_depth].target_addr = dest;
   251 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   252     }
   253     call_stack_depth++;
   254 }
   256 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   257 {
   258     if( call_stack_depth > 0 ) {
   259 	call_stack_depth--;
   260     }
   261 }
   263 void fprint_stack_trace( FILE *f )
   264 {
   265     int i = call_stack_depth -1;
   266     if( i >= MAX_CALLSTACK )
   267 	i = MAX_CALLSTACK - 1;
   268     for( ; i >= 0; i-- ) {
   269 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   270 		 (call_stack_depth - i), call_stack[i].call_addr,
   271 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   272     }
   273 }
   275 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   276 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   277 #else
   278 #define TRACE_CALL( dest, rts ) 
   279 #define TRACE_RETURN( source, dest )
   280 #endif
   282 #define RAISE( x, v ) do{			\
   283     if( sh4r.vbr == 0 ) { \
   284         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   285         dreamcast_stop(); return FALSE;	\
   286     } else { \
   287         sh4r.spc = sh4r.pc;	\
   288         sh4r.ssr = sh4_read_sr(); \
   289         sh4r.sgr = sh4r.r[15]; \
   290         MMIO_WRITE(MMU,EXPEVT,x); \
   291         sh4r.pc = sh4r.vbr + v; \
   292         sh4r.new_pc = sh4r.pc + 2; \
   293         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   294 	if( sh4r.in_delay_slot ) { \
   295 	    sh4r.in_delay_slot = 0; \
   296 	    sh4r.spc -= 2; \
   297 	} \
   298     } \
   299     return TRUE; } while(0)
   301 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   302 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   303 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   304 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   305 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   306 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   308 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   310 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   311 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   313 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   314 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   315 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   316 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   317 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   319 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   320 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   321 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   323 static void sh4_switch_banks( )
   324 {
   325     uint32_t tmp[8];
   327     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   328     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   329     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   330 }
   332 static void sh4_load_sr( uint32_t newval )
   333 {
   334     if( (newval ^ sh4r.sr) & SR_RB )
   335         sh4_switch_banks();
   336     sh4r.sr = newval;
   337     sh4r.t = (newval&SR_T) ? 1 : 0;
   338     sh4r.s = (newval&SR_S) ? 1 : 0;
   339     sh4r.m = (newval&SR_M) ? 1 : 0;
   340     sh4r.q = (newval&SR_Q) ? 1 : 0;
   341     intc_mask_changed();
   342 }
   344 static void sh4_write_float( uint32_t addr, int reg )
   345 {
   346     if( IS_FPU_DOUBLESIZE() ) {
   347 	if( reg & 1 ) {
   348 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   349 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   350 	} else {
   351 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   352 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   353 	}
   354     } else {
   355 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   356     }
   357 }
   359 static void sh4_read_float( uint32_t addr, int reg )
   360 {
   361     if( IS_FPU_DOUBLESIZE() ) {
   362 	if( reg & 1 ) {
   363 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   364 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   365 	} else {
   366 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   367 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   368 	}
   369     } else {
   370 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   371     }
   372 }
   374 static uint32_t sh4_read_sr( void )
   375 {
   376     /* synchronize sh4r.sr with the various bitflags */
   377     sh4r.sr &= SR_MQSTMASK;
   378     if( sh4r.t ) sh4r.sr |= SR_T;
   379     if( sh4r.s ) sh4r.sr |= SR_S;
   380     if( sh4r.m ) sh4r.sr |= SR_M;
   381     if( sh4r.q ) sh4r.sr |= SR_Q;
   382     return sh4r.sr;
   383 }
   385 /**
   386  * Raise a general CPU exception for the specified exception code.
   387  * (NOT for TRAPA or TLB exceptions)
   388  */
   389 gboolean sh4_raise_exception( int code )
   390 {
   391     RAISE( code, EXV_EXCEPTION );
   392 }
   394 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   395     if( sh4r.in_delay_slot ) {
   396 	return sh4_raise_exception(slot_code);
   397     } else {
   398 	return sh4_raise_exception(normal_code);
   399     }
   400 }
   402 gboolean sh4_raise_tlb_exception( int code )
   403 {
   404     RAISE( code, EXV_TLBMISS );
   405 }
   407 void sh4_accept_interrupt( void )
   408 {
   409     uint32_t code = intc_accept_interrupt();
   410     sh4r.ssr = sh4_read_sr();
   411     sh4r.spc = sh4r.pc;
   412     sh4r.sgr = sh4r.r[15];
   413     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   414     MMIO_WRITE( MMU, INTEVT, code );
   415     sh4r.pc = sh4r.vbr + 0x600;
   416     sh4r.new_pc = sh4r.pc + 2;
   417     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   418 }
   420 gboolean sh4_execute_instruction( void )
   421 {
   422     uint32_t pc;
   423     unsigned short ir;
   424     uint32_t tmp;
   425     float ftmp;
   426     double dtmp;
   428 #define R0 sh4r.r[0]
   429     pc = sh4r.pc;
   430     if( pc > 0xFFFFFF00 ) {
   431 	/* SYSCALL Magic */
   432 	syscall_invoke( pc );
   433 	sh4r.in_delay_slot = 0;
   434 	pc = sh4r.pc = sh4r.pr;
   435 	sh4r.new_pc = sh4r.pc + 2;
   436     }
   437     CHECKRALIGN16(pc);
   439     /* Read instruction */
   440     uint32_t pageaddr = pc >> 12;
   441     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   442 	ir = sh4_icache[(pc&0xFFF)>>1];
   443     } else {
   444 	sh4_icache = (uint16_t *)mem_get_page(pc);
   445 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   446 	    /* If someone's actually been so daft as to try to execute out of an IO
   447 	     * region, fallback on the full-blown memory read
   448 	     */
   449 	    sh4_icache = NULL;
   450 	    ir = MEM_READ_WORD(pc);
   451 	} else {
   452 	    sh4_icache_addr = pageaddr;
   453 	    ir = sh4_icache[(pc&0xFFF)>>1];
   454 	}
   455     }
   456 %%
   457 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   458 AND #imm, R0 {: R0 &= imm; :}
   459 AND.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
   460 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   461 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   462 OR #imm, R0  {: R0 |= imm; :}
   463 OR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
   464 TAS.B @Rn {:
   465     tmp = MEM_READ_BYTE( sh4r.r[Rn] );
   466     sh4r.t = ( tmp == 0 ? 1 : 0 );
   467     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   468 :}
   469 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   470 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   471 TST.B #imm, @(R0, GBR) {: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); :}
   472 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   473 XOR #imm, R0 {: R0 ^= imm; :}
   474 XOR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
   475 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   477 ROTL Rn {:
   478     sh4r.t = sh4r.r[Rn] >> 31;
   479     sh4r.r[Rn] <<= 1;
   480     sh4r.r[Rn] |= sh4r.t;
   481 :}
   482 ROTR Rn {:
   483     sh4r.t = sh4r.r[Rn] & 0x00000001;
   484     sh4r.r[Rn] >>= 1;
   485     sh4r.r[Rn] |= (sh4r.t << 31);
   486 :}
   487 ROTCL Rn {:
   488     tmp = sh4r.r[Rn] >> 31;
   489     sh4r.r[Rn] <<= 1;
   490     sh4r.r[Rn] |= sh4r.t;
   491     sh4r.t = tmp;
   492 :}
   493 ROTCR Rn {:
   494     tmp = sh4r.r[Rn] & 0x00000001;
   495     sh4r.r[Rn] >>= 1;
   496     sh4r.r[Rn] |= (sh4r.t << 31 );
   497     sh4r.t = tmp;
   498 :}
   499 SHAD Rm, Rn {:
   500     tmp = sh4r.r[Rm];
   501     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   502     else if( (tmp & 0x1F) == 0 )  
   503         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   504     else 
   505 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   506 :}
   507 SHLD Rm, Rn {:
   508     tmp = sh4r.r[Rm];
   509     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   510     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   511     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   512 :}
   513 SHAL Rn {:
   514     sh4r.t = sh4r.r[Rn] >> 31;
   515     sh4r.r[Rn] <<= 1;
   516 :}
   517 SHAR Rn {:
   518     sh4r.t = sh4r.r[Rn] & 0x00000001;
   519     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   520 :}
   521 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   522 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   523 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   524 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   525 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   526 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   527 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   528 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   530 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   531 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   532 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   533 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   534 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   535 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   537 CLRT {: sh4r.t = 0; :}
   538 SETT {: sh4r.t = 1; :}
   539 CLRMAC {: sh4r.mac = 0; :}
   540 LDTLB {: /* TODO */ :}
   541 CLRS {: sh4r.s = 0; :}
   542 SETS {: sh4r.s = 1; :}
   543 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   544 NOP {: /* NOP */ :}
   546 PREF @Rn {:
   547      tmp = sh4r.r[Rn];
   548      if( (tmp & 0xFC000000) == 0xE0000000 ) {
   549 	 /* Store queue operation */
   550 	 int queue = (tmp&0x20)>>2;
   551 	 int32_t *src = &sh4r.store_queue[queue];
   552 	 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   553 	 uint32_t target = tmp&0x03FFFFE0 | hi;
   554 	 mem_copy_to_sh4( target, src, 32 );
   555      }
   556 :}
   557 OCBI @Rn {: :}
   558 OCBP @Rn {: :}
   559 OCBWB @Rn {: :}
   560 MOVCA.L R0, @Rn {:
   561     tmp = sh4r.r[Rn];
   562     CHECKWALIGN32(tmp);
   563     MEM_WRITE_LONG( tmp, R0 );
   564 :}
   565 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   566 MOV.W Rm, @(R0, Rn) {: 
   567     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   568     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   569 :}
   570 MOV.L Rm, @(R0, Rn) {:
   571     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   572     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   573 :}
   574 MOV.B @(R0, Rm), Rn {: sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); :}
   575 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   576                     sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
   577 :}
   578 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   579                     sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
   580 :}
   581 MOV.L Rm, @(disp, Rn) {:
   582     tmp = sh4r.r[Rn] + disp;
   583     CHECKWALIGN32( tmp );
   584     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   585 :}
   586 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   587 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   588 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   589 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   590 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   591 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   592 MOV.L @(disp, Rm), Rn {:
   593     tmp = sh4r.r[Rm] + disp;
   594     CHECKRALIGN32( tmp );
   595     sh4r.r[Rn] = MEM_READ_LONG( tmp );
   596 :}
   597 MOV.B @Rm, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); :}
   598 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); :}
   599 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); :}
   600 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   601 MOV.B @Rm+, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; :}
   602 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; :}
   603 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; :}
   604 MOV.L @(disp, PC), Rn {:
   605     CHECKSLOTILLEGAL();
   606     tmp = (pc&0xFFFFFFFC) + disp + 4;
   607     sh4r.r[Rn] = MEM_READ_LONG( tmp );
   608 :}
   609 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   610 MOV.W R0, @(disp, GBR) {:
   611     tmp = sh4r.gbr + disp;
   612     CHECKWALIGN16( tmp );
   613     MEM_WRITE_WORD( tmp, R0 );
   614 :}
   615 MOV.L R0, @(disp, GBR) {:
   616     tmp = sh4r.gbr + disp;
   617     CHECKWALIGN32( tmp );
   618     MEM_WRITE_LONG( tmp, R0 );
   619 :}
   620 MOV.B @(disp, GBR), R0 {: R0 = MEM_READ_BYTE( sh4r.gbr + disp ); :}
   621 MOV.W @(disp, GBR), R0 {: 
   622     tmp = sh4r.gbr + disp;
   623     CHECKRALIGN16( tmp );
   624     R0 = MEM_READ_WORD( tmp );
   625 :}
   626 MOV.L @(disp, GBR), R0 {:
   627     tmp = sh4r.gbr + disp;
   628     CHECKRALIGN32( tmp );
   629     R0 = MEM_READ_LONG( tmp );
   630 :}
   631 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   632 MOV.W R0, @(disp, Rn) {: 
   633     tmp = sh4r.r[Rn] + disp;
   634     CHECKWALIGN16( tmp );
   635     MEM_WRITE_WORD( tmp, R0 );
   636 :}
   637 MOV.B @(disp, Rm), R0 {: R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); :}
   638 MOV.W @(disp, Rm), R0 {: 
   639     tmp = sh4r.r[Rm] + disp;
   640     CHECKRALIGN16( tmp );
   641     R0 = MEM_READ_WORD( tmp );
   642 :}
   643 MOV.W @(disp, PC), Rn {:
   644     CHECKSLOTILLEGAL();
   645     tmp = pc + 4 + disp;
   646     sh4r.r[Rn] = MEM_READ_WORD( tmp );
   647 :}
   648 MOVA @(disp, PC), R0 {:
   649     CHECKSLOTILLEGAL();
   650     R0 = (pc&0xFFFFFFFC) + disp + 4;
   651 :}
   652 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   654 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   655 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   656 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   657 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   658 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   659 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   660 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   661 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   662 CMP/STR Rm, Rn {: 
   663     /* set T = 1 if any byte in RM & RN is the same */
   664     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   665     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   666              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   667 :}
   669 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   670 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   671 ADDC Rm, Rn {:
   672     tmp = sh4r.r[Rn];
   673     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   674     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   675 :}
   676 ADDV Rm, Rn {:
   677     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   678     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   679     sh4r.r[Rn] = tmp;
   680 :}
   681 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   682 DIV0S Rm, Rn {: 
   683     sh4r.q = sh4r.r[Rn]>>31;
   684     sh4r.m = sh4r.r[Rm]>>31;
   685     sh4r.t = sh4r.q ^ sh4r.m;
   686 :}
   687 DIV1 Rm, Rn {:
   688     /* This is just from the sh4p manual with some
   689      * simplifications (someone want to check it's correct? :)
   690      * Why they couldn't just provide a real DIV instruction...
   691      */
   692     uint32_t tmp0, tmp1, tmp2, dir;
   694     dir = sh4r.q ^ sh4r.m;
   695     sh4r.q = (sh4r.r[Rn] >> 31);
   696     tmp2 = sh4r.r[Rm];
   697     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   698     tmp0 = sh4r.r[Rn];
   699     if( dir ) {
   700          sh4r.r[Rn] += tmp2;
   701          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   702     } else {
   703          sh4r.r[Rn] -= tmp2;
   704          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   705     }
   706     sh4r.q ^= sh4r.m ^ tmp1;
   707     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   708 :}
   709 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   710 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   711 DT Rn {:
   712     sh4r.r[Rn] --;
   713     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   714 :}
   715 MAC.W @Rm+, @Rn+ {:
   716     CHECKRALIGN16( sh4r.r[Rn] );
   717     CHECKRALIGN16( sh4r.r[Rm] );
   718     int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
   719     sh4r.r[Rn] += 2;
   720     stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
   721     sh4r.r[Rm] += 2;
   722     if( sh4r.s ) {
   723 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   724 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   725 	    sh4r.mac = 0x000000017FFFFFFFLL;
   726 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   727 	    sh4r.mac = 0x0000000180000000LL;
   728 	} else {
   729 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   730 		((uint32_t)(sh4r.mac + stmp));
   731 	}
   732     } else {
   733 	sh4r.mac += SIGNEXT32(stmp);
   734     }
   735 :}
   736 MAC.L @Rm+, @Rn+ {:
   737     CHECKRALIGN32( sh4r.r[Rm] );
   738     CHECKRALIGN32( sh4r.r[Rn] );
   739     int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
   740     sh4r.r[Rn] += 4;
   741     tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
   742     sh4r.r[Rm] += 4;
   743     if( sh4r.s ) {
   744         /* 48-bit Saturation. Yuch */
   745         if( tmpl < (int64_t)0xFFFF800000000000LL )
   746             tmpl = 0xFFFF800000000000LL;
   747         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   748             tmpl = 0x00007FFFFFFFFFFFLL;
   749     }
   750     sh4r.mac = tmpl;
   751 :}
   752 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   753                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   754 MULU.W Rm, Rn {:
   755     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   756                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   757 :}
   758 MULS.W Rm, Rn {:
   759     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   760                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   761 :}
   762 NEGC Rm, Rn {:
   763     tmp = 0 - sh4r.r[Rm];
   764     sh4r.r[Rn] = tmp - sh4r.t;
   765     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   766 :}
   767 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   768 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   769 SUBC Rm, Rn {: 
   770     tmp = sh4r.r[Rn];
   771     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   772     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   773 :}
   775 BRAF Rn {:
   776      CHECKSLOTILLEGAL();
   777      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   778      sh4r.in_delay_slot = 1;
   779      sh4r.pc = sh4r.new_pc;
   780      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   781      return TRUE;
   782 :}
   783 BSRF Rn {:
   784      CHECKSLOTILLEGAL();
   785      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   786      sh4r.in_delay_slot = 1;
   787      sh4r.pr = sh4r.pc + 4;
   788      sh4r.pc = sh4r.new_pc;
   789      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   790      TRACE_CALL( pc, sh4r.new_pc );
   791      return TRUE;
   792 :}
   793 BT disp {:
   794     CHECKSLOTILLEGAL();
   795     if( sh4r.t ) {
   796         CHECKDEST( sh4r.pc + disp + 4 )
   797         sh4r.pc += disp + 4;
   798         sh4r.new_pc = sh4r.pc + 2;
   799         return TRUE;
   800     }
   801 :}
   802 BF disp {:
   803     CHECKSLOTILLEGAL();
   804     if( !sh4r.t ) {
   805         CHECKDEST( sh4r.pc + disp + 4 )
   806         sh4r.pc += disp + 4;
   807         sh4r.new_pc = sh4r.pc + 2;
   808         return TRUE;
   809     }
   810 :}
   811 BT/S disp {:
   812     CHECKSLOTILLEGAL();
   813     if( sh4r.t ) {
   814         CHECKDEST( sh4r.pc + disp + 4 )
   815         sh4r.in_delay_slot = 1;
   816         sh4r.pc = sh4r.new_pc;
   817         sh4r.new_pc = pc + disp + 4;
   818         sh4r.in_delay_slot = 1;
   819         return TRUE;
   820     }
   821 :}
   822 BF/S disp {:
   823     CHECKSLOTILLEGAL();
   824     if( !sh4r.t ) {
   825         CHECKDEST( sh4r.pc + disp + 4 )
   826         sh4r.in_delay_slot = 1;
   827         sh4r.pc = sh4r.new_pc;
   828         sh4r.new_pc = pc + disp + 4;
   829         return TRUE;
   830     }
   831 :}
   832 BRA disp {:
   833     CHECKSLOTILLEGAL();
   834     CHECKDEST( sh4r.pc + disp + 4 );
   835     sh4r.in_delay_slot = 1;
   836     sh4r.pc = sh4r.new_pc;
   837     sh4r.new_pc = pc + 4 + disp;
   838     return TRUE;
   839 :}
   840 BSR disp {:
   841     CHECKDEST( sh4r.pc + disp + 4 );
   842     CHECKSLOTILLEGAL();
   843     sh4r.in_delay_slot = 1;
   844     sh4r.pr = pc + 4;
   845     sh4r.pc = sh4r.new_pc;
   846     sh4r.new_pc = pc + 4 + disp;
   847     TRACE_CALL( pc, sh4r.new_pc );
   848     return TRUE;
   849 :}
   850 TRAPA #imm {:
   851     CHECKSLOTILLEGAL();
   852     MMIO_WRITE( MMU, TRA, imm<<2 );
   853     sh4r.pc += 2;
   854     sh4_raise_exception( EXC_TRAP );
   855 :}
   856 RTS {: 
   857     CHECKSLOTILLEGAL();
   858     CHECKDEST( sh4r.pr );
   859     sh4r.in_delay_slot = 1;
   860     sh4r.pc = sh4r.new_pc;
   861     sh4r.new_pc = sh4r.pr;
   862     TRACE_RETURN( pc, sh4r.new_pc );
   863     return TRUE;
   864 :}
   865 SLEEP {:
   866     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   867 	sh4r.sh4_state = SH4_STATE_STANDBY;
   868     } else {
   869 	sh4r.sh4_state = SH4_STATE_SLEEP;
   870     }
   871     return FALSE; /* Halt CPU */
   872 :}
   873 RTE {:
   874     CHECKPRIV();
   875     CHECKDEST( sh4r.spc );
   876     CHECKSLOTILLEGAL();
   877     sh4r.in_delay_slot = 1;
   878     sh4r.pc = sh4r.new_pc;
   879     sh4r.new_pc = sh4r.spc;
   880     sh4_load_sr( sh4r.ssr );
   881     return TRUE;
   882 :}
   883 JMP @Rn {:
   884     CHECKDEST( sh4r.r[Rn] );
   885     CHECKSLOTILLEGAL();
   886     sh4r.in_delay_slot = 1;
   887     sh4r.pc = sh4r.new_pc;
   888     sh4r.new_pc = sh4r.r[Rn];
   889     return TRUE;
   890 :}
   891 JSR @Rn {:
   892     CHECKDEST( sh4r.r[Rn] );
   893     CHECKSLOTILLEGAL();
   894     sh4r.in_delay_slot = 1;
   895     sh4r.pc = sh4r.new_pc;
   896     sh4r.new_pc = sh4r.r[Rn];
   897     sh4r.pr = pc + 4;
   898     TRACE_CALL( pc, sh4r.new_pc );
   899     return TRUE;
   900 :}
   901 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   902 STS.L MACH, @-Rn {:
   903     sh4r.r[Rn] -= 4;
   904     CHECKWALIGN32( sh4r.r[Rn] );
   905     MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
   906 :}
   907 STC.L SR, @-Rn {:
   908     CHECKPRIV();
   909     sh4r.r[Rn] -= 4;
   910     CHECKWALIGN32( sh4r.r[Rn] );
   911     MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
   912 :}
   913 LDS.L @Rm+, MACH {:
   914     CHECKRALIGN32( sh4r.r[Rm] );
   915     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   916                (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
   917     sh4r.r[Rm] += 4;
   918 :}
   919 LDC.L @Rm+, SR {:
   920     CHECKSLOTILLEGAL();
   921     CHECKPRIV();
   922     CHECKWALIGN32( sh4r.r[Rm] );
   923     sh4_load_sr( MEM_READ_LONG(sh4r.r[Rm]) );
   924     sh4r.r[Rm] +=4;
   925 :}
   926 LDS Rm, MACH {:
   927     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   928                (((uint64_t)sh4r.r[Rm])<<32);
   929 :}
   930 LDC Rm, SR {:
   931     CHECKSLOTILLEGAL();
   932     CHECKPRIV();
   933     sh4_load_sr( sh4r.r[Rm] );
   934 :}
   935 LDC Rm, SGR {:
   936     CHECKPRIV();
   937     sh4r.sgr = sh4r.r[Rm];
   938 :}
   939 LDC.L @Rm+, SGR {:
   940     CHECKPRIV();
   941     CHECKRALIGN32( sh4r.r[Rm] );
   942     sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
   943     sh4r.r[Rm] +=4;
   944 :}
   945 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   946 STS.L MACL, @-Rn {:
   947     sh4r.r[Rn] -= 4;
   948     CHECKWALIGN32( sh4r.r[Rn] );
   949     MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
   950 :}
   951 STC.L GBR, @-Rn {:
   952     sh4r.r[Rn] -= 4;
   953     CHECKWALIGN32( sh4r.r[Rn] );
   954     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
   955 :}
   956 LDS.L @Rm+, MACL {:
   957     CHECKRALIGN32( sh4r.r[Rm] );
   958     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   959                (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
   960     sh4r.r[Rm] += 4;
   961 :}
   962 LDC.L @Rm+, GBR {:
   963     CHECKRALIGN32( sh4r.r[Rm] );
   964     sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
   965     sh4r.r[Rm] +=4;
   966 :}
   967 LDS Rm, MACL {:
   968     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   969                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   970 :}
   971 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   972 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   973 STS.L PR, @-Rn {:
   974     sh4r.r[Rn] -= 4;
   975     CHECKWALIGN32( sh4r.r[Rn] );
   976     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
   977 :}
   978 STC.L VBR, @-Rn {:
   979     CHECKPRIV();
   980     sh4r.r[Rn] -= 4;
   981     CHECKWALIGN32( sh4r.r[Rn] );
   982     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
   983 :}
   984 LDS.L @Rm+, PR {:
   985     CHECKRALIGN32( sh4r.r[Rm] );
   986     sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
   987     sh4r.r[Rm] += 4;
   988 :}
   989 LDC.L @Rm+, VBR {:
   990     CHECKPRIV();
   991     CHECKRALIGN32( sh4r.r[Rm] );
   992     sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
   993     sh4r.r[Rm] +=4;
   994 :}
   995 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   996 LDC Rm, VBR {:
   997     CHECKPRIV();
   998     sh4r.vbr = sh4r.r[Rm];
   999 :}
  1000 STC SGR, Rn {:
  1001     CHECKPRIV();
  1002     sh4r.r[Rn] = sh4r.sgr;
  1003 :}
  1004 STC.L SGR, @-Rn {:
  1005     CHECKPRIV();
  1006     sh4r.r[Rn] -= 4;
  1007     CHECKWALIGN32( sh4r.r[Rn] );
  1008     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
  1009 :}
  1010 STC.L SSR, @-Rn {:
  1011     CHECKPRIV();
  1012     sh4r.r[Rn] -= 4;
  1013     CHECKWALIGN32( sh4r.r[Rn] );
  1014     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
  1015 :}
  1016 LDC.L @Rm+, SSR {:
  1017     CHECKPRIV();
  1018     CHECKRALIGN32( sh4r.r[Rm] );
  1019     sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
  1020     sh4r.r[Rm] +=4;
  1021 :}
  1022 LDC Rm, SSR {:
  1023     CHECKPRIV();
  1024     sh4r.ssr = sh4r.r[Rm];
  1025 :}
  1026 STC.L SPC, @-Rn {:
  1027     CHECKPRIV();
  1028     sh4r.r[Rn] -= 4;
  1029     CHECKWALIGN32( sh4r.r[Rn] );
  1030     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
  1031 :}
  1032 LDC.L @Rm+, SPC {:
  1033     CHECKPRIV();
  1034     CHECKRALIGN32( sh4r.r[Rm] );
  1035     sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
  1036     sh4r.r[Rm] +=4;
  1037 :}
  1038 LDC Rm, SPC {:
  1039     CHECKPRIV();
  1040     sh4r.spc = sh4r.r[Rm];
  1041 :}
  1042 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
  1043 STS.L FPUL, @-Rn {:
  1044     sh4r.r[Rn] -= 4;
  1045     CHECKWALIGN32( sh4r.r[Rn] );
  1046     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
  1047 :}
  1048 LDS.L @Rm+, FPUL {:
  1049     CHECKRALIGN32( sh4r.r[Rm] );
  1050     sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
  1051     sh4r.r[Rm] +=4;
  1052 :}
  1053 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
  1054 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
  1055 STS.L FPSCR, @-Rn {:
  1056     sh4r.r[Rn] -= 4;
  1057     CHECKWALIGN32( sh4r.r[Rn] );
  1058     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
  1059 :}
  1060 LDS.L @Rm+, FPSCR {:
  1061     CHECKRALIGN32( sh4r.r[Rm] );
  1062     sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
  1063     sh4r.r[Rm] +=4;
  1064 :}
  1065 LDS Rm, FPSCR {: sh4r.fpscr = sh4r.r[Rm]; :}
  1066 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
  1067 STC.L DBR, @-Rn {:
  1068     CHECKPRIV();
  1069     sh4r.r[Rn] -= 4;
  1070     CHECKWALIGN32( sh4r.r[Rn] );
  1071     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
  1072 :}
  1073 LDC.L @Rm+, DBR {:
  1074     CHECKPRIV();
  1075     CHECKRALIGN32( sh4r.r[Rm] );
  1076     sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
  1077     sh4r.r[Rm] +=4;
  1078 :}
  1079 LDC Rm, DBR {:
  1080     CHECKPRIV();
  1081     sh4r.dbr = sh4r.r[Rm];
  1082 :}
  1083 STC.L Rm_BANK, @-Rn {:
  1084     CHECKPRIV();
  1085     sh4r.r[Rn] -= 4;
  1086     CHECKWALIGN32( sh4r.r[Rn] );
  1087     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
  1088 :}
  1089 LDC.L @Rm+, Rn_BANK {:
  1090     CHECKPRIV();
  1091     CHECKRALIGN32( sh4r.r[Rm] );
  1092     sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
  1093     sh4r.r[Rm] += 4;
  1094 :}
  1095 LDC Rm, Rn_BANK {:
  1096     CHECKPRIV();
  1097     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1098 :}
  1099 STC SR, Rn {: 
  1100     CHECKPRIV();
  1101     sh4r.r[Rn] = sh4_read_sr();
  1102 :}
  1103 STC GBR, Rn {:
  1104     CHECKPRIV();
  1105     sh4r.r[Rn] = sh4r.gbr;
  1106 :}
  1107 STC VBR, Rn {:
  1108     CHECKPRIV();
  1109     sh4r.r[Rn] = sh4r.vbr;
  1110 :}
  1111 STC SSR, Rn {:
  1112     CHECKPRIV();
  1113     sh4r.r[Rn] = sh4r.ssr;
  1114 :}
  1115 STC SPC, Rn {:
  1116     CHECKPRIV();
  1117     sh4r.r[Rn] = sh4r.spc;
  1118 :}
  1119 STC Rm_BANK, Rn {:
  1120     CHECKPRIV();
  1121     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
  1122 :}
  1124 FADD FRm, FRn {:
  1125     CHECKFPUEN();
  1126     if( IS_FPU_DOUBLEPREC() ) {
  1127 	DR(FRn) += DR(FRm);
  1128     } else {
  1129 	FR(FRn) += FR(FRm);
  1131 :}
  1132 FSUB FRm, FRn {:
  1133     CHECKFPUEN();
  1134     if( IS_FPU_DOUBLEPREC() ) {
  1135 	DR(FRn) -= DR(FRm);
  1136     } else {
  1137 	FR(FRn) -= FR(FRm);
  1139 :}
  1141 FMUL FRm, FRn {:
  1142     CHECKFPUEN();
  1143     if( IS_FPU_DOUBLEPREC() ) {
  1144 	DR(FRn) *= DR(FRm);
  1145     } else {
  1146 	FR(FRn) *= FR(FRm);
  1148 :}
  1150 FDIV FRm, FRn {:
  1151     CHECKFPUEN();
  1152     if( IS_FPU_DOUBLEPREC() ) {
  1153 	DR(FRn) /= DR(FRm);
  1154     } else {
  1155 	FR(FRn) /= FR(FRm);
  1157 :}
  1159 FCMP/EQ FRm, FRn {:
  1160     CHECKFPUEN();
  1161     if( IS_FPU_DOUBLEPREC() ) {
  1162 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1163     } else {
  1164 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1166 :}
  1168 FCMP/GT FRm, FRn {:
  1169     CHECKFPUEN();
  1170     if( IS_FPU_DOUBLEPREC() ) {
  1171 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1172     } else {
  1173 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1175 :}
  1177 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
  1178 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
  1179 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
  1180 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
  1181 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
  1182 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
  1183 FMOV FRm, FRn {: 
  1184     if( IS_FPU_DOUBLESIZE() )
  1185 	DR(FRn) = DR(FRm);
  1186     else
  1187 	FR(FRn) = FR(FRm);
  1188 :}
  1189 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
  1190 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
  1191 FLOAT FPUL, FRn {: 
  1192     CHECKFPUEN();
  1193     if( IS_FPU_DOUBLEPREC() )
  1194 	DR(FRn) = (float)FPULi;
  1195     else
  1196 	FR(FRn) = (float)FPULi;
  1197 :}
  1198 FTRC FRm, FPUL {:
  1199     CHECKFPUEN();
  1200     if( IS_FPU_DOUBLEPREC() ) {
  1201         dtmp = DR(FRm);
  1202         if( dtmp >= MAX_INTF )
  1203             FPULi = MAX_INT;
  1204         else if( dtmp <= MIN_INTF )
  1205             FPULi = MIN_INT;
  1206         else 
  1207             FPULi = (int32_t)dtmp;
  1208     } else {
  1209 	ftmp = FR(FRm);
  1210 	if( ftmp >= MAX_INTF )
  1211 	    FPULi = MAX_INT;
  1212 	else if( ftmp <= MIN_INTF )
  1213 	    FPULi = MIN_INT;
  1214 	else
  1215 	    FPULi = (int32_t)ftmp;
  1217 :}
  1218 FNEG FRn {:
  1219     CHECKFPUEN();
  1220     if( IS_FPU_DOUBLEPREC() ) {
  1221 	DR(FRn) = -DR(FRn);
  1222     } else {
  1223         FR(FRn) = -FR(FRn);
  1225 :}
  1226 FABS FRn {:
  1227     CHECKFPUEN();
  1228     if( IS_FPU_DOUBLEPREC() ) {
  1229 	DR(FRn) = fabs(DR(FRn));
  1230     } else {
  1231         FR(FRn) = fabsf(FR(FRn));
  1233 :}
  1234 FSQRT FRn {:
  1235     CHECKFPUEN();
  1236     if( IS_FPU_DOUBLEPREC() ) {
  1237 	DR(FRn) = sqrt(DR(FRn));
  1238     } else {
  1239         FR(FRn) = sqrtf(FR(FRn));
  1241 :}
  1242 FLDI0 FRn {:
  1243     CHECKFPUEN();
  1244     if( IS_FPU_DOUBLEPREC() ) {
  1245 	DR(FRn) = 0.0;
  1246     } else {
  1247         FR(FRn) = 0.0;
  1249 :}
  1250 FLDI1 FRn {:
  1251     CHECKFPUEN();
  1252     if( IS_FPU_DOUBLEPREC() ) {
  1253 	DR(FRn) = 1.0;
  1254     } else {
  1255         FR(FRn) = 1.0;
  1257 :}
  1258 FMAC FR0, FRm, FRn {:
  1259     CHECKFPUEN();
  1260     if( IS_FPU_DOUBLEPREC() ) {
  1261         DR(FRn) += DR(FRm)*DR(0);
  1262     } else {
  1263 	FR(FRn) += FR(FRm)*FR(0);
  1265 :}
  1266 FRCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_FR; :}
  1267 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1268 FCNVSD FPUL, FRn {:
  1269     CHECKFPUEN();
  1270     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1271 	DR(FRn) = (double)FPULf;
  1273 :}
  1274 FCNVDS FRm, FPUL {:
  1275     CHECKFPUEN();
  1276     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1277 	FPULf = (float)DR(FRm);
  1279 :}
  1281 FSRRA FRn {:
  1282     CHECKFPUEN();
  1283     if( !IS_FPU_DOUBLEPREC() ) {
  1284 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1286 :}
  1287 FIPR FVm, FVn {:
  1288     CHECKFPUEN();
  1289     if( !IS_FPU_DOUBLEPREC() ) {
  1290         int tmp2 = FVn<<2;
  1291         tmp = FVm<<2;
  1292         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1293             FR(tmp+1)*FR(tmp2+1) +
  1294             FR(tmp+2)*FR(tmp2+2) +
  1295             FR(tmp+3)*FR(tmp2+3);
  1297 :}
  1298 FSCA FPUL, FRn {:
  1299     CHECKFPUEN();
  1300     if( !IS_FPU_DOUBLEPREC() ) {
  1301         float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  1302         FR(FRn) = sinf(angle);
  1303         FR((FRn)+1) = cosf(angle);
  1305 :}
  1306 FTRV XMTRX, FVn {:
  1307     CHECKFPUEN();
  1308     if( !IS_FPU_DOUBLEPREC() ) {
  1309         tmp = FVn<<2;
  1310         float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  1311         FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
  1312 	    XF(8)*fv[2] + XF(12)*fv[3];
  1313         FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
  1314 	    XF(9)*fv[2] + XF(13)*fv[3];
  1315         FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
  1316 	    XF(10)*fv[2] + XF(14)*fv[3];
  1317         FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
  1318 	    XF(11)*fv[2] + XF(15)*fv[3];
  1320 :}
  1321 UNDEF {:
  1322     UNDEF(ir);
  1323 :}
  1324 %%
  1325     sh4r.pc = sh4r.new_pc;
  1326     sh4r.new_pc += 2;
  1327     sh4r.in_delay_slot = 0;
  1328     return TRUE;
.