Search
lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4core.c
changeset 232:9c8ef78376ed
prev229:f27eb26ccdd2
next235:880bff11df92
author nkeynes
date Tue Sep 26 11:09:13 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add CHECKSLOTILLEGAL() checks around a few banned delay-slot instructions
that were missing it
Change CHECKPRIV() to raise slot-illegal on a delay-slot instruction rather
than general-illegal (as per the manual)
Convert UNDEF() to do the real exception rather than halting the machine
Remove a couple of superfluous alignment checks
view annotate diff log raw
     1 /**
     2  * $Id: sh4core.c,v 1.33 2006-09-26 11:09:13 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 /* CPU-generated exception code/vector pairs */
    38 #define EXC_POWER_RESET  0x000 /* vector special */
    39 #define EXC_MANUAL_RESET 0x020
    40 #define EXC_READ_ADDR_ERR 0x0E0
    41 #define EXC_WRITE_ADDR_ERR 0x100
    42 #define EXC_SLOT_ILLEGAL 0x1A0
    43 #define EXC_ILLEGAL      0x180
    44 #define EXV_ILLEGAL      0x100
    45 #define EXC_TRAP         0x160
    46 #define EXV_TRAP         0x100
    47 #define EXC_FPDISABLE    0x800
    48 #define EXV_FPDISABLE    0x100
    50 /********************** SH4 Module Definition ****************************/
    52 void sh4_init( void );
    53 void sh4_reset( void );
    54 uint32_t sh4_run_slice( uint32_t );
    55 void sh4_start( void );
    56 void sh4_stop( void );
    57 void sh4_save_state( FILE *f );
    58 int sh4_load_state( FILE *f );
    60 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    61 				       NULL, sh4_run_slice, sh4_stop,
    62 				       sh4_save_state, sh4_load_state };
    64 struct sh4_registers sh4r;
    66 void sh4_init(void)
    67 {
    68     register_io_regions( mmio_list_sh4mmio );
    69     mmu_init();
    70     sh4_reset();
    71 }
    73 void sh4_reset(void)
    74 {
    75     /* zero everything out, for the sake of having a consistent state. */
    76     memset( &sh4r, 0, sizeof(sh4r) );
    78     /* Resume running if we were halted */
    79     sh4r.sh4_state = SH4_STATE_RUNNING;
    81     sh4r.pc    = 0xA0000000;
    82     sh4r.new_pc= 0xA0000002;
    83     sh4r.vbr   = 0x00000000;
    84     sh4r.fpscr = 0x00040001;
    85     sh4r.sr    = 0x700000F0;
    87     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    88     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    90     /* Peripheral modules */
    91     INTC_reset();
    92     TMU_reset();
    93     SCIF_reset();
    94 }
    96 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    97 static int sh4_breakpoint_count = 0;
    99 void sh4_set_breakpoint( uint32_t pc, int type )
   100 {
   101     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   102     sh4_breakpoints[sh4_breakpoint_count].type = type;
   103     sh4_breakpoint_count++;
   104 }
   106 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   107 {
   108     int i;
   110     for( i=0; i<sh4_breakpoint_count; i++ ) {
   111 	if( sh4_breakpoints[i].address == pc && 
   112 	    sh4_breakpoints[i].type == type ) {
   113 	    while( ++i < sh4_breakpoint_count ) {
   114 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   115 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   116 	    }
   117 	    sh4_breakpoint_count--;
   118 	    return TRUE;
   119 	}
   120     }
   121     return FALSE;
   122 }
   124 int sh4_get_breakpoint( uint32_t pc )
   125 {
   126     int i;
   127     for( i=0; i<sh4_breakpoint_count; i++ ) {
   128 	if( sh4_breakpoints[i].address == pc )
   129 	    return sh4_breakpoints[i].type;
   130     }
   131     return 0;
   132 }
   134 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   135 {
   136     int target = sh4r.icount + nanosecs / sh4_cpu_period;
   137     int start = sh4r.icount;
   138     int i;
   140     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   141 	if( sh4r.int_pending != 0 )
   142 	    sh4r.sh4_state = SH4_STATE_RUNNING;;
   143     }
   145     for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   146 	if( !sh4_execute_instruction() )
   147 	    break;
   148 #ifdef ENABLE_DEBUG_MODE
   149 	for( i=0; i<sh4_breakpoint_count; i++ ) {
   150 	    if( sh4_breakpoints[i].address == sh4r.pc ) {
   151 		break;
   152 	    }
   153 	}
   154 	if( i != sh4_breakpoint_count ) {
   155 	    dreamcast_stop();
   156 	    if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   157 		sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   158 	    break;
   159 	}
   160 #endif	
   161     }
   163     /* If we aborted early, but the cpu is still technically running,
   164      * we're doing a hard abort - cut the timeslice back to what we
   165      * actually executed
   166      */
   167     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   168 	nanosecs = sh4r.slice_cycle;
   169     }
   170     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   171 	TMU_run_slice( nanosecs );
   172 	SCIF_run_slice( nanosecs );
   173     }
   174     sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
   175     return nanosecs;
   176 }
   178 void sh4_stop(void)
   179 {
   181 }
   183 void sh4_save_state( FILE *f )
   184 {
   185     fwrite( &sh4r, sizeof(sh4r), 1, f );
   186     INTC_save_state( f );
   187     TMU_save_state( f );
   188     SCIF_save_state( f );
   189 }
   191 int sh4_load_state( FILE * f )
   192 {
   193     fread( &sh4r, sizeof(sh4r), 1, f );
   194     INTC_load_state( f );
   195     TMU_load_state( f );
   196     return SCIF_load_state( f );
   197 }
   199 /********************** SH4 emulation core  ****************************/
   201 void sh4_set_pc( int pc )
   202 {
   203     sh4r.pc = pc;
   204     sh4r.new_pc = pc+2;
   205 }
   207 #define UNDEF(ir) if( sh4r.in_delay_slot ) { RAISE( EXC_SLOT_ILLEGAL, EXV_ILLEGAL, -2 ); } else { RAISE( EXC_ILLEGAL, EXV_ILLEGAL, 0 ); }
   208 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   210 #if(SH4_CALLTRACE == 1)
   211 #define MAX_CALLSTACK 32
   212 static struct call_stack {
   213     sh4addr_t call_addr;
   214     sh4addr_t target_addr;
   215     sh4addr_t stack_pointer;
   216 } call_stack[MAX_CALLSTACK];
   218 static int call_stack_depth = 0;
   219 int sh4_call_trace_on = 0;
   221 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   222 {
   223     if( call_stack_depth < MAX_CALLSTACK ) {
   224 	call_stack[call_stack_depth].call_addr = source;
   225 	call_stack[call_stack_depth].target_addr = dest;
   226 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   227     }
   228     call_stack_depth++;
   229 }
   231 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   232 {
   233     if( call_stack_depth > 0 ) {
   234 	call_stack_depth--;
   235     }
   236 }
   238 void fprint_stack_trace( FILE *f )
   239 {
   240     int i = call_stack_depth -1;
   241     if( i >= MAX_CALLSTACK )
   242 	i = MAX_CALLSTACK - 1;
   243     for( ; i >= 0; i-- ) {
   244 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   245 		 (call_stack_depth - i), call_stack[i].call_addr,
   246 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   247     }
   248 }
   250 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   251 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   252 #else
   253 #define TRACE_CALL( dest, rts ) 
   254 #define TRACE_RETURN( source, dest )
   255 #endif
   257 #define RAISE( x, v, pcadj ) do{			\
   258     if( sh4r.vbr == 0 ) { \
   259         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   260         dreamcast_stop(); return FALSE;	\
   261     } else { \
   262         sh4r.spc = sh4r.pc + pcadj; \
   263         sh4r.ssr = sh4_read_sr(); \
   264         sh4r.sgr = sh4r.r[15]; \
   265         MMIO_WRITE(MMU,EXPEVT,x); \
   266         sh4r.pc = sh4r.vbr + v; \
   267         sh4r.new_pc = sh4r.pc + 2; \
   268         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   269 	sh4r.in_delay_slot = 0; \
   270     } \
   271     return TRUE; } while(0)
   272 #define RAISE_SLOTILLEGAL() RAISE( EXC_SLOT_ILLEGAL, EXV_ILLEGAL, -2 )
   273 #define RAISE_ILLEGAL() RAISE( EXC_ILLEGAL, EXV_ILLEGAL, 0 )
   275 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   276 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   277 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   278 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   279 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   280 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   282 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   284 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   286 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   288 #define CHECK( x, c, v ) if( !x ) RAISE( c, v, 0 )
   289 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) { if( sh4r.in_delay_slot ) { RAISE_SLOTILLEGAL(); } else { RAISE_ILLEGAL(); } }
   290 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
   291 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
   292 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
   293 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
   295 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
   296 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   297 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL, -2); }
   299 static void sh4_switch_banks( )
   300 {
   301     uint32_t tmp[8];
   303     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   304     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   305     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   306 }
   308 static void sh4_load_sr( uint32_t newval )
   309 {
   310     if( (newval ^ sh4r.sr) & SR_RB )
   311         sh4_switch_banks();
   312     sh4r.sr = newval;
   313     sh4r.t = (newval&SR_T) ? 1 : 0;
   314     sh4r.s = (newval&SR_S) ? 1 : 0;
   315     sh4r.m = (newval&SR_M) ? 1 : 0;
   316     sh4r.q = (newval&SR_Q) ? 1 : 0;
   317     intc_mask_changed();
   318 }
   320 static void sh4_write_float( uint32_t addr, int reg )
   321 {
   322     if( IS_FPU_DOUBLESIZE() ) {
   323 	if( reg & 1 ) {
   324 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   325 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   326 	} else {
   327 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   328 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   329 	}
   330     } else {
   331 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   332     }
   333 }
   335 static void sh4_read_float( uint32_t addr, int reg )
   336 {
   337     if( IS_FPU_DOUBLESIZE() ) {
   338 	if( reg & 1 ) {
   339 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   340 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   341 	} else {
   342 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   343 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   344 	}
   345     } else {
   346 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   347     }
   348 }
   350 static uint32_t sh4_read_sr( void )
   351 {
   352     /* synchronize sh4r.sr with the various bitflags */
   353     sh4r.sr &= SR_MQSTMASK;
   354     if( sh4r.t ) sh4r.sr |= SR_T;
   355     if( sh4r.s ) sh4r.sr |= SR_S;
   356     if( sh4r.m ) sh4r.sr |= SR_M;
   357     if( sh4r.q ) sh4r.sr |= SR_Q;
   358     return sh4r.sr;
   359 }
   360 /* function for external use */
   361 void sh4_raise_exception( int code, int vector )
   362 {
   363     RAISE(code, vector, 0);
   364 }
   366 static void sh4_accept_interrupt( void )
   367 {
   368     uint32_t code = intc_accept_interrupt();
   369     sh4r.ssr = sh4_read_sr();
   370     sh4r.spc = sh4r.pc;
   371     sh4r.sgr = sh4r.r[15];
   372     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   373     MMIO_WRITE( MMU, INTEVT, code );
   374     sh4r.pc = sh4r.vbr + 0x600;
   375     sh4r.new_pc = sh4r.pc + 2;
   376     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   377 }
   379 gboolean sh4_execute_instruction( void )
   380 {
   381     uint32_t pc;
   382     unsigned short ir;
   383     uint32_t tmp;
   384     uint64_t tmpl;
   385     float ftmp;
   386     double dtmp;
   388 #define R0 sh4r.r[0]
   389 #define FR0 FR(0)
   390 #define DR0 DR(0)
   391 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   392 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   393 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   394 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   395 #define DISP8(ir) (ir&0x00FF)
   396 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   397 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   398 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   399 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   400 #define FRNn(ir) ((ir&0x0F00)>>8)
   401 #define FRMn(ir) ((ir&0x00F0)>>4)
   402 #define DRNn(ir) ((ir&0x0E00)>>9)
   403 #define DRMn(ir) ((ir&0x00E0)>>5)
   404 #define FVN(ir) ((ir&0x0C00)>>8)
   405 #define FVM(ir) ((ir&0x0300)>>6)
   406 #define FRN(ir) FR(FRNn(ir))
   407 #define FRM(ir) FR(FRMn(ir))
   408 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
   409 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
   410 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
   411 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
   412 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
   413 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
   414 #define FPULf   *((float *)&sh4r.fpul)
   415 #define FPULi    (sh4r.fpul)
   417     if( SH4_INT_PENDING() ) 
   418         sh4_accept_interrupt();
   420     pc = sh4r.pc;
   421     if( pc > 0xFFFFFF00 ) {
   422 	/* SYSCALL Magic */
   423 	syscall_invoke( pc );
   424 	sh4r.in_delay_slot = 0;
   425 	pc = sh4r.pc = sh4r.pr;
   426 	sh4r.new_pc = sh4r.pc + 2;
   427     }
   428     CHECKRALIGN16(pc);
   429     ir = MEM_READ_WORD(pc);
   430     sh4r.icount++;
   432     switch( (ir&0xF000)>>12 ) {
   433         case 0: /* 0000nnnnmmmmxxxx */
   434             switch( ir&0x000F ) {
   435                 case 2:
   436                     switch( (ir&0x00F0)>>4 ) {
   437                         case 0: /* STC     SR, Rn */
   438                             CHECKPRIV();
   439                             RN(ir) = sh4_read_sr();
   440                             break;
   441                         case 1: /* STC     GBR, Rn */
   442                             RN(ir) = sh4r.gbr;
   443                             break;
   444                         case 2: /* STC     VBR, Rn */
   445                             CHECKPRIV();
   446                             RN(ir) = sh4r.vbr;
   447                             break;
   448                         case 3: /* STC     SSR, Rn */
   449                             CHECKPRIV();
   450                             RN(ir) = sh4r.ssr;
   451                             break;
   452                         case 4: /* STC     SPC, Rn */
   453                             CHECKPRIV();
   454                             RN(ir) = sh4r.spc;
   455                             break;
   456                         case 8: case 9: case 10: case 11: case 12: case 13:
   457                         case 14: case 15:/* STC     Rm_bank, Rn */
   458                             CHECKPRIV();
   459                             RN(ir) = RN_BANK(ir);
   460                             break;
   461                         default: UNDEF(ir);
   462                     }
   463                     break;
   464                 case 3:
   465                     switch( (ir&0x00F0)>>4 ) {
   466                         case 0: /* BSRF    Rn */
   467                             CHECKSLOTILLEGAL();
   468                             CHECKDEST( pc + 4 + RN(ir) );
   469                             sh4r.in_delay_slot = 1;
   470                             sh4r.pr = sh4r.pc + 4;
   471                             sh4r.pc = sh4r.new_pc;
   472                             sh4r.new_pc = pc + 4 + RN(ir);
   473 			    TRACE_CALL( pc, sh4r.new_pc );
   474                             return TRUE;
   475                         case 2: /* BRAF    Rn */
   476                             CHECKSLOTILLEGAL();
   477                             CHECKDEST( pc + 4 + RN(ir) );
   478                             sh4r.in_delay_slot = 1;
   479                             sh4r.pc = sh4r.new_pc;
   480                             sh4r.new_pc = pc + 4 + RN(ir);
   481                             return TRUE;
   482                         case 8: /* PREF    [Rn] */
   483                             tmp = RN(ir);
   484                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   485                                 /* Store queue operation */
   486                                 int queue = (tmp&0x20)>>2;
   487                                 int32_t *src = &sh4r.store_queue[queue];
   488                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   489                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   490                                 mem_copy_to_sh4( target, src, 32 );
   491                             }
   492                             break;
   493                         case 9: /* OCBI    [Rn] */
   494                         case 10:/* OCBP    [Rn] */
   495                         case 11:/* OCBWB   [Rn] */
   496                             /* anything? */
   497                             break;
   498                         case 12:/* MOVCA.L R0, [Rn] */
   499 			    tmp = RN(ir);
   500 			    CHECKWALIGN32(tmp);
   501 			    MEM_WRITE_LONG( tmp, R0 );
   502 			    break;
   503                         default: UNDEF(ir);
   504                     }
   505                     break;
   506                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   507                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   508                     break;
   509                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   510 		    CHECKWALIGN16( R0 + RN(ir) );
   511                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   512                     break;
   513                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   514 		    CHECKWALIGN32( R0 + RN(ir) );
   515                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   516                     break;
   517                 case 7: /* MUL.L   Rm, Rn */
   518                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   519                         (RM(ir) * RN(ir));
   520                     break;
   521                 case 8: 
   522                     switch( (ir&0x0FF0)>>4 ) {
   523                         case 0: /* CLRT    */
   524                             sh4r.t = 0;
   525                             break;
   526                         case 1: /* SETT    */
   527                             sh4r.t = 1;
   528                             break;
   529                         case 2: /* CLRMAC  */
   530                             sh4r.mac = 0;
   531                             break;
   532                         case 3: /* LDTLB   */
   533                             break;
   534                         case 4: /* CLRS    */
   535                             sh4r.s = 0;
   536                             break;
   537                         case 5: /* SETS    */
   538                             sh4r.s = 1;
   539                             break;
   540                         default: UNDEF(ir);
   541                     }
   542                     break;
   543                 case 9: 
   544                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   545                         RN(ir) = sh4r.t;
   546                     else if( ir == 0x0019 ) /* DIV0U   */
   547                         sh4r.m = sh4r.q = sh4r.t = 0;
   548                     else if( ir == 0x0009 )
   549                         /* NOP     */;
   550                     else UNDEF(ir);
   551                     break;
   552                 case 10:
   553                     switch( (ir&0x00F0) >> 4 ) {
   554                         case 0: /* STS     MACH, Rn */
   555                             RN(ir) = sh4r.mac >> 32;
   556                             break;
   557                         case 1: /* STS     MACL, Rn */
   558                             RN(ir) = (uint32_t)sh4r.mac;
   559                             break;
   560                         case 2: /* STS     PR, Rn */
   561                             RN(ir) = sh4r.pr;
   562                             break;
   563                         case 3: /* STC     SGR, Rn */
   564                             CHECKPRIV();
   565                             RN(ir) = sh4r.sgr;
   566                             break;
   567                         case 5:/* STS      FPUL, Rn */
   568                             RN(ir) = sh4r.fpul;
   569                             break;
   570                         case 6: /* STS     FPSCR, Rn */
   571                             RN(ir) = sh4r.fpscr;
   572                             break;
   573                         case 15:/* STC     DBR, Rn */
   574                             CHECKPRIV();
   575                             RN(ir) = sh4r.dbr;
   576                             break;
   577                         default: UNDEF(ir);
   578                     }
   579                     break;
   580                 case 11:
   581                     switch( (ir&0x0FF0)>>4 ) {
   582                         case 0: /* RTS     */
   583                             CHECKSLOTILLEGAL();
   584                             CHECKDEST( sh4r.pr );
   585                             sh4r.in_delay_slot = 1;
   586                             sh4r.pc = sh4r.new_pc;
   587                             sh4r.new_pc = sh4r.pr;
   588                             TRACE_RETURN( pc, sh4r.new_pc );
   589                             return TRUE;
   590                         case 1: /* SLEEP   */
   591 			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   592 				sh4r.sh4_state = SH4_STATE_STANDBY;
   593 			    } else {
   594 				sh4r.sh4_state = SH4_STATE_SLEEP;
   595 			    }
   596 			    return FALSE; /* Halt CPU */
   597                         case 2: /* RTE     */
   598                             CHECKPRIV();
   599                             CHECKDEST( sh4r.spc );
   600                             CHECKSLOTILLEGAL();
   601                             sh4r.in_delay_slot = 1;
   602                             sh4r.pc = sh4r.new_pc;
   603                             sh4r.new_pc = sh4r.spc;
   604                             sh4_load_sr( sh4r.ssr );
   605                             return TRUE;
   606                         default:UNDEF(ir);
   607                     }
   608                     break;
   609                 case 12:/* MOV.B   [R0+R%d], R%d */
   610                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   611                     break;
   612                 case 13:/* MOV.W   [R0+R%d], R%d */
   613 		    CHECKRALIGN16( R0 + RM(ir) );
   614                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   615                     break;
   616                 case 14:/* MOV.L   [R0+R%d], R%d */
   617 		    CHECKRALIGN32( R0 + RM(ir) );
   618                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   619                     break;
   620                 case 15:/* MAC.L   [Rm++], [Rn++] */
   621 		    CHECKRALIGN32( RM(ir) );
   622 		    CHECKRALIGN32( RN(ir) );
   623                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   624                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   625                     if( sh4r.s ) {
   626                         /* 48-bit Saturation. Yuch */
   627                         tmpl += SIGNEXT48(sh4r.mac);
   628                         if( tmpl < 0xFFFF800000000000LL )
   629                             tmpl = 0xFFFF800000000000LL;
   630                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   631                             tmpl = 0x00007FFFFFFFFFFFLL;
   632                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   633                             (tmpl&0x0000FFFFFFFFFFFFLL);
   634                     } else sh4r.mac = tmpl;
   636                     RM(ir) += 4;
   637                     RN(ir) += 4;
   639                     break;
   640                 default: UNDEF(ir);
   641             }
   642             break;
   643         case 1: /* 0001nnnnmmmmdddd */
   644             /* MOV.L   Rm, [Rn + disp4*4] */
   645 	    tmp = RN(ir) + (DISP4(ir)<<2);
   646 	    CHECKWALIGN32( tmp );
   647             MEM_WRITE_LONG( tmp, RM(ir) );
   648             break;
   649         case 2: /* 0010nnnnmmmmxxxx */
   650             switch( ir&0x000F ) {
   651                 case 0: /* MOV.B   Rm, [Rn] */
   652                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   653                     break;
   654                 case 1: /* MOV.W   Rm, [Rn] */
   655                	    CHECKWALIGN16( RN(ir) );
   656 		    MEM_WRITE_WORD( RN(ir), RM(ir) );
   657                     break;
   658                 case 2: /* MOV.L   Rm, [Rn] */
   659 		    CHECKWALIGN32( RN(ir) );
   660                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   661                     break;
   662                 case 3: UNDEF(ir);
   663                     break;
   664                 case 4: /* MOV.B   Rm, [--Rn] */
   665                     RN(ir) --;
   666                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   667                     break;
   668                 case 5: /* MOV.W   Rm, [--Rn] */
   669                     RN(ir) -= 2;
   670 		    CHECKWALIGN16( RN(ir) );
   671                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   672                     break;
   673                 case 6: /* MOV.L   Rm, [--Rn] */
   674                     RN(ir) -= 4;
   675 		    CHECKWALIGN32( RN(ir) );
   676                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   677                     break;
   678                 case 7: /* DIV0S   Rm, Rn */
   679                     sh4r.q = RN(ir)>>31;
   680                     sh4r.m = RM(ir)>>31;
   681                     sh4r.t = sh4r.q ^ sh4r.m;
   682                     break;
   683                 case 8: /* TST     Rm, Rn */
   684                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   685                     break;
   686                 case 9: /* AND     Rm, Rn */
   687                     RN(ir) &= RM(ir);
   688                     break;
   689                 case 10:/* XOR     Rm, Rn */
   690                     RN(ir) ^= RM(ir);
   691                     break;
   692                 case 11:/* OR      Rm, Rn */
   693                     RN(ir) |= RM(ir);
   694                     break;
   695                 case 12:/* CMP/STR Rm, Rn */
   696                     /* set T = 1 if any byte in RM & RN is the same */
   697                     tmp = RM(ir) ^ RN(ir);
   698                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   699                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   700                     break;
   701                 case 13:/* XTRCT   Rm, Rn */
   702                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   703                     break;
   704                 case 14:/* MULU.W  Rm, Rn */
   705                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   706                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   707                     break;
   708                 case 15:/* MULS.W  Rm, Rn */
   709                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   710                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   711                     break;
   712             }
   713             break;
   714         case 3: /* 0011nnnnmmmmxxxx */
   715             switch( ir&0x000F ) {
   716                 case 0: /* CMP/EQ  Rm, Rn */
   717                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   718                     break;
   719                 case 2: /* CMP/HS  Rm, Rn */
   720                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   721                     break;
   722                 case 3: /* CMP/GE  Rm, Rn */
   723                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   724                     break;
   725                 case 4: { /* DIV1    Rm, Rn */
   726                     /* This is just from the sh4p manual with some
   727                      * simplifications (someone want to check it's correct? :)
   728                      * Why they couldn't just provide a real DIV instruction...
   729                      * Please oh please let the translator batch these things
   730                      * up into a single DIV... */
   731                     uint32_t tmp0, tmp1, tmp2, dir;
   733                     dir = sh4r.q ^ sh4r.m;
   734                     sh4r.q = (RN(ir) >> 31);
   735                     tmp2 = RM(ir);
   736                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   737                     tmp0 = RN(ir);
   738                     if( dir ) {
   739                         RN(ir) += tmp2;
   740                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   741                     } else {
   742                         RN(ir) -= tmp2;
   743                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   744                     }
   745                     sh4r.q ^= sh4r.m ^ tmp1;
   746                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   747                     break; }
   748                 case 5: /* DMULU.L Rm, Rn */
   749                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   750                     break;
   751                 case 6: /* CMP/HI  Rm, Rn */
   752                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   753                     break;
   754                 case 7: /* CMP/GT  Rm, Rn */
   755                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   756                     break;
   757                 case 8: /* SUB     Rm, Rn */
   758                     RN(ir) -= RM(ir);
   759                     break;
   760                 case 10:/* SUBC    Rm, Rn */
   761                     tmp = RN(ir);
   762                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   763                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   764                     break;
   765                 case 11:/* SUBV    Rm, Rn */
   766                     UNIMP(ir);
   767                     break;
   768                 case 12:/* ADD     Rm, Rn */
   769                     RN(ir) += RM(ir);
   770                     break;
   771                 case 13:/* DMULS.L Rm, Rn */
   772                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   773                     break;
   774                 case 14:/* ADDC    Rm, Rn */
   775                     tmp = RN(ir);
   776                     RN(ir) += RM(ir) + sh4r.t;
   777                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   778                     break;
   779                 case 15:/* ADDV    Rm, Rn */
   780 		    tmp = RN(ir) + RM(ir);
   781 		    sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
   782 		    RN(ir) = tmp;
   783                     break;
   784                 default: UNDEF(ir);
   785             }
   786             break;
   787         case 4: /* 0100nnnnxxxxxxxx */
   788             switch( ir&0x00FF ) {
   789                 case 0x00: /* SHLL    Rn */
   790                     sh4r.t = RN(ir) >> 31;
   791                     RN(ir) <<= 1;
   792                     break;
   793                 case 0x01: /* SHLR    Rn */
   794                     sh4r.t = RN(ir) & 0x00000001;
   795                     RN(ir) >>= 1;
   796                     break;
   797                 case 0x02: /* STS.L   MACH, [--Rn] */
   798                     RN(ir) -= 4;
   799 		    CHECKWALIGN32( RN(ir) );
   800                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   801                     break;
   802                 case 0x03: /* STC.L   SR, [--Rn] */
   803                     CHECKPRIV();
   804                     RN(ir) -= 4;
   805 		    CHECKWALIGN32( RN(ir) );
   806                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   807                     break;
   808                 case 0x04: /* ROTL    Rn */
   809                     sh4r.t = RN(ir) >> 31;
   810                     RN(ir) <<= 1;
   811                     RN(ir) |= sh4r.t;
   812                     break;
   813                 case 0x05: /* ROTR    Rn */
   814                     sh4r.t = RN(ir) & 0x00000001;
   815                     RN(ir) >>= 1;
   816                     RN(ir) |= (sh4r.t << 31);
   817                     break;
   818                 case 0x06: /* LDS.L   [Rn++], MACH */
   819 		    CHECKRALIGN32( RN(ir) );
   820                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   821                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   822                     RN(ir) += 4;
   823                     break;
   824                 case 0x07: /* LDC.L   [Rn++], SR */
   825 		    CHECKSLOTILLEGAL();
   826                     CHECKPRIV();
   827 		    CHECKWALIGN32( RN(ir) );
   828                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   829                     RN(ir) +=4;
   830                     break;
   831                 case 0x08: /* SHLL2   Rn */
   832                     RN(ir) <<= 2;
   833                     break;
   834                 case 0x09: /* SHLR2   Rn */
   835                     RN(ir) >>= 2;
   836                     break;
   837                 case 0x0A: /* LDS     Rn, MACH */
   838                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   839                         (((uint64_t)RN(ir))<<32);
   840                     break;
   841                 case 0x0B: /* JSR     [Rn] */
   842                     CHECKDEST( RN(ir) );
   843                     CHECKSLOTILLEGAL();
   844                     sh4r.in_delay_slot = 1;
   845                     sh4r.pc = sh4r.new_pc;
   846                     sh4r.new_pc = RN(ir);
   847                     sh4r.pr = pc + 4;
   848 		    TRACE_CALL( pc, sh4r.new_pc );
   849                     return TRUE;
   850                 case 0x0E: /* LDC     Rn, SR */
   851 		    CHECKSLOTILLEGAL();
   852                     CHECKPRIV();
   853                     sh4_load_sr( RN(ir) );
   854                     break;
   855                 case 0x10: /* DT      Rn */
   856                     RN(ir) --;
   857                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   858                     break;
   859                 case 0x11: /* CMP/PZ  Rn */
   860                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   861                     break;
   862                 case 0x12: /* STS.L   MACL, [--Rn] */
   863                     RN(ir) -= 4;
   864 		    CHECKWALIGN32( RN(ir) );
   865                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   866                     break;
   867                 case 0x13: /* STC.L   GBR, [--Rn] */
   868                     RN(ir) -= 4;
   869 		    CHECKWALIGN32( RN(ir) );
   870                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   871                     break;
   872                 case 0x15: /* CMP/PL  Rn */
   873                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   874                     break;
   875                 case 0x16: /* LDS.L   [Rn++], MACL */
   876 		    CHECKRALIGN32( RN(ir) );
   877                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   878                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   879                     RN(ir) += 4;
   880                     break;
   881                 case 0x17: /* LDC.L   [Rn++], GBR */
   882 		    CHECKRALIGN32( RN(ir) );
   883                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   884                     RN(ir) +=4;
   885                     break;
   886                 case 0x18: /* SHLL8   Rn */
   887                     RN(ir) <<= 8;
   888                     break;
   889                 case 0x19: /* SHLR8   Rn */
   890                     RN(ir) >>= 8;
   891                     break;
   892                 case 0x1A: /* LDS     Rn, MACL */
   893                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   894                         (uint64_t)((uint32_t)(RN(ir)));
   895                     break;
   896                 case 0x1B: /* TAS.B   [Rn] */
   897                     tmp = MEM_READ_BYTE( RN(ir) );
   898                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   899                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   900                     break;
   901                 case 0x1E: /* LDC     Rn, GBR */
   902                     sh4r.gbr = RN(ir);
   903                     break;
   904                 case 0x20: /* SHAL    Rn */
   905                     sh4r.t = RN(ir) >> 31;
   906                     RN(ir) <<= 1;
   907                     break;
   908                 case 0x21: /* SHAR    Rn */
   909                     sh4r.t = RN(ir) & 0x00000001;
   910                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   911                     break;
   912                 case 0x22: /* STS.L   PR, [--Rn] */
   913                     RN(ir) -= 4;
   914 		    CHECKWALIGN32( RN(ir) );
   915                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   916                     break;
   917                 case 0x23: /* STC.L   VBR, [--Rn] */
   918                     CHECKPRIV();
   919                     RN(ir) -= 4;
   920 		    CHECKWALIGN32( RN(ir) );
   921                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   922                     break;
   923                 case 0x24: /* ROTCL   Rn */
   924                     tmp = RN(ir) >> 31;
   925                     RN(ir) <<= 1;
   926                     RN(ir) |= sh4r.t;
   927                     sh4r.t = tmp;
   928                     break;
   929                 case 0x25: /* ROTCR   Rn */
   930                     tmp = RN(ir) & 0x00000001;
   931                     RN(ir) >>= 1;
   932                     RN(ir) |= (sh4r.t << 31 );
   933                     sh4r.t = tmp;
   934                     break;
   935                 case 0x26: /* LDS.L   [Rn++], PR */
   936 		    CHECKRALIGN32( RN(ir) );
   937                     sh4r.pr = MEM_READ_LONG( RN(ir) );
   938                     RN(ir) += 4;
   939                     break;
   940                 case 0x27: /* LDC.L   [Rn++], VBR */
   941                     CHECKPRIV();
   942 		    CHECKRALIGN32( RN(ir) );
   943                     sh4r.vbr = MEM_READ_LONG(RN(ir));
   944                     RN(ir) +=4;
   945                     break;
   946                 case 0x28: /* SHLL16  Rn */
   947                     RN(ir) <<= 16;
   948                     break;
   949                 case 0x29: /* SHLR16  Rn */
   950                     RN(ir) >>= 16;
   951                     break;
   952                 case 0x2A: /* LDS     Rn, PR */
   953                     sh4r.pr = RN(ir);
   954                     break;
   955                 case 0x2B: /* JMP     [Rn] */
   956                     CHECKDEST( RN(ir) );
   957                     CHECKSLOTILLEGAL();
   958                     sh4r.in_delay_slot = 1;
   959                     sh4r.pc = sh4r.new_pc;
   960                     sh4r.new_pc = RN(ir);
   961                     return TRUE;
   962                 case 0x2E: /* LDC     Rn, VBR */
   963                     CHECKPRIV();
   964                     sh4r.vbr = RN(ir);
   965                     break;
   966                 case 0x32: /* STC.L   SGR, [--Rn] */
   967                     CHECKPRIV();
   968                     RN(ir) -= 4;
   969 		    CHECKWALIGN32( RN(ir) );
   970                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
   971                     break;
   972                 case 0x33: /* STC.L   SSR, [--Rn] */
   973                     CHECKPRIV();
   974                     RN(ir) -= 4;
   975 		    CHECKWALIGN32( RN(ir) );
   976                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
   977                     break;
   978                 case 0x37: /* LDC.L   [Rn++], SSR */
   979                     CHECKPRIV();
   980 		    CHECKRALIGN32( RN(ir) );
   981                     sh4r.ssr = MEM_READ_LONG(RN(ir));
   982                     RN(ir) +=4;
   983                     break;
   984                 case 0x3E: /* LDC     Rn, SSR */
   985                     CHECKPRIV();
   986                     sh4r.ssr = RN(ir);
   987                     break;
   988                 case 0x43: /* STC.L   SPC, [--Rn] */
   989                     CHECKPRIV();
   990                     RN(ir) -= 4;
   991 		    CHECKWALIGN32( RN(ir) );
   992                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
   993                     break;
   994                 case 0x47: /* LDC.L   [Rn++], SPC */
   995                     CHECKPRIV();
   996 		    CHECKRALIGN32( RN(ir) );
   997                     sh4r.spc = MEM_READ_LONG(RN(ir));
   998                     RN(ir) +=4;
   999                     break;
  1000                 case 0x4E: /* LDC     Rn, SPC */
  1001                     CHECKPRIV();
  1002                     sh4r.spc = RN(ir);
  1003                     break;
  1004                 case 0x52: /* STS.L   FPUL, [--Rn] */
  1005                     RN(ir) -= 4;
  1006 		    CHECKWALIGN32( RN(ir) );
  1007                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
  1008                     break;
  1009                 case 0x56: /* LDS.L   [Rn++], FPUL */
  1010 		    CHECKRALIGN32( RN(ir) );
  1011                     sh4r.fpul = MEM_READ_LONG(RN(ir));
  1012                     RN(ir) +=4;
  1013                     break;
  1014                 case 0x5A: /* LDS     Rn, FPUL */
  1015                     sh4r.fpul = RN(ir);
  1016                     break;
  1017                 case 0x62: /* STS.L   FPSCR, [--Rn] */
  1018                     RN(ir) -= 4;
  1019 		    CHECKWALIGN32( RN(ir) );
  1020                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
  1021                     break;
  1022                 case 0x66: /* LDS.L   [Rn++], FPSCR */
  1023 		    CHECKRALIGN32( RN(ir) );
  1024                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
  1025                     RN(ir) +=4;
  1026                     break;
  1027                 case 0x6A: /* LDS     Rn, FPSCR */
  1028                     sh4r.fpscr = RN(ir);
  1029                     break;
  1030                 case 0xF2: /* STC.L   DBR, [--Rn] */
  1031                     CHECKPRIV();
  1032                     RN(ir) -= 4;
  1033 		    CHECKWALIGN32( RN(ir) );
  1034                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
  1035                     break;
  1036                 case 0xF6: /* LDC.L   [Rn++], DBR */
  1037                     CHECKPRIV();
  1038 		    CHECKRALIGN32( RN(ir) );
  1039                     sh4r.dbr = MEM_READ_LONG(RN(ir));
  1040                     RN(ir) +=4;
  1041                     break;
  1042                 case 0xFA: /* LDC     Rn, DBR */
  1043                     CHECKPRIV();
  1044                     sh4r.dbr = RN(ir);
  1045                     break;
  1046                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
  1047                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
  1048                     CHECKPRIV();
  1049                     RN(ir) -= 4;
  1050 		    CHECKWALIGN32( RN(ir) );
  1051                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
  1052                     break;
  1053                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
  1054                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
  1055                     CHECKPRIV();
  1056 		    CHECKRALIGN32( RN(ir) );
  1057                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
  1058                     RN(ir) += 4;
  1059                     break;
  1060                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
  1061                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
  1062                     CHECKPRIV();
  1063                     RN_BANK(ir) = RM(ir);
  1064                     break;
  1065                 default:
  1066                     if( (ir&0x000F) == 0x0F ) {
  1067                         /* MAC.W   [Rm++], [Rn++] */
  1068 			CHECKRALIGN16( RN(ir) );
  1069 			CHECKRALIGN16( RM(ir) );
  1070                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
  1071                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
  1072                         if( sh4r.s ) {
  1073                             /* FIXME */
  1074                             UNIMP(ir);
  1075                         } else sh4r.mac += SIGNEXT32(tmp);
  1076                         RM(ir) += 2;
  1077                         RN(ir) += 2;
  1078                     } else if( (ir&0x000F) == 0x0C ) {
  1079                         /* SHAD    Rm, Rn */
  1080                         tmp = RM(ir);
  1081                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1082                         else if( (tmp & 0x1F) == 0 )  
  1083 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
  1084                         else 
  1085 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
  1086                     } else if( (ir&0x000F) == 0x0D ) {
  1087                         /* SHLD    Rm, Rn */
  1088                         tmp = RM(ir);
  1089                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1090                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
  1091                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
  1092                     } else UNDEF(ir);
  1094             break;
  1095         case 5: /* 0101nnnnmmmmdddd */
  1096             /* MOV.L   [Rm + disp4*4], Rn */
  1097 	    tmp = RM(ir) + (DISP4(ir)<<2);
  1098 	    CHECKRALIGN32( tmp );
  1099             RN(ir) = MEM_READ_LONG( tmp );
  1100             break;
  1101         case 6: /* 0110xxxxxxxxxxxx */
  1102             switch( ir&0x000f ) {
  1103                 case 0: /* MOV.B   [Rm], Rn */
  1104                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1105                     break;
  1106                 case 1: /* MOV.W   [Rm], Rn */
  1107 		    CHECKRALIGN16( RM(ir) );
  1108                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1109                     break;
  1110                 case 2: /* MOV.L   [Rm], Rn */
  1111 		    CHECKRALIGN32( RM(ir) );
  1112                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1113                     break;
  1114                 case 3: /* MOV     Rm, Rn */
  1115                     RN(ir) = RM(ir);
  1116                     break;
  1117                 case 4: /* MOV.B   [Rm++], Rn */
  1118                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1119                     RM(ir) ++;
  1120                     break;
  1121                 case 5: /* MOV.W   [Rm++], Rn */
  1122 		    CHECKRALIGN16( RM(ir) );
  1123                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1124                     RM(ir) += 2;
  1125                     break;
  1126                 case 6: /* MOV.L   [Rm++], Rn */
  1127 		    CHECKRALIGN32( RM(ir) );
  1128                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1129                     RM(ir) += 4;
  1130                     break;
  1131                 case 7: /* NOT     Rm, Rn */
  1132                     RN(ir) = ~RM(ir);
  1133                     break;
  1134                 case 8: /* SWAP.B  Rm, Rn */
  1135                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
  1136                         ((RM(ir)&0x000000FF)<<8);
  1137                     break;
  1138                 case 9: /* SWAP.W  Rm, Rn */
  1139                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
  1140                     break;
  1141                 case 10:/* NEGC    Rm, Rn */
  1142                     tmp = 0 - RM(ir);
  1143                     RN(ir) = tmp - sh4r.t;
  1144                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
  1145                     break;
  1146                 case 11:/* NEG     Rm, Rn */
  1147                     RN(ir) = 0 - RM(ir);
  1148                     break;
  1149                 case 12:/* EXTU.B  Rm, Rn */
  1150                     RN(ir) = RM(ir)&0x000000FF;
  1151                     break;
  1152                 case 13:/* EXTU.W  Rm, Rn */
  1153                     RN(ir) = RM(ir)&0x0000FFFF;
  1154                     break;
  1155                 case 14:/* EXTS.B  Rm, Rn */
  1156                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
  1157                     break;
  1158                 case 15:/* EXTS.W  Rm, Rn */
  1159                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
  1160                     break;
  1162             break;
  1163         case 7: /* 0111nnnniiiiiiii */
  1164             /* ADD    imm8, Rn */
  1165             RN(ir) += IMM8(ir);
  1166             break;
  1167         case 8: /* 1000xxxxxxxxxxxx */
  1168             switch( (ir&0x0F00) >> 8 ) {
  1169                 case 0: /* MOV.B   R0, [Rm + disp4] */
  1170                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
  1171                     break;
  1172                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
  1173 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1174 		    CHECKWALIGN16( tmp );
  1175                     MEM_WRITE_WORD( tmp, R0 );
  1176                     break;
  1177                 case 4: /* MOV.B   [Rm + disp4], R0 */
  1178                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
  1179                     break;
  1180                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
  1181 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1182 		    CHECKRALIGN16( tmp );
  1183                     R0 = MEM_READ_WORD( tmp );
  1184                     break;
  1185                 case 8: /* CMP/EQ  imm, R0 */
  1186                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
  1187                     break;
  1188                 case 9: /* BT      disp8 */
  1189                     CHECKSLOTILLEGAL()
  1190                     if( sh4r.t ) {
  1191                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1192                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1193                         sh4r.new_pc = sh4r.pc + 2;
  1194                         return TRUE;
  1196                     break;
  1197                 case 11:/* BF      disp8 */
  1198                     CHECKSLOTILLEGAL()
  1199                     if( !sh4r.t ) {
  1200                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1201                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1202                         sh4r.new_pc = sh4r.pc + 2;
  1203                         return TRUE;
  1205                     break;
  1206                 case 13:/* BT/S    disp8 */
  1207                     CHECKSLOTILLEGAL()
  1208                     if( sh4r.t ) {
  1209                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1210                         sh4r.in_delay_slot = 1;
  1211                         sh4r.pc = sh4r.new_pc;
  1212                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1213                         sh4r.in_delay_slot = 1;
  1214                         return TRUE;
  1216                     break;
  1217                 case 15:/* BF/S    disp8 */
  1218                     CHECKSLOTILLEGAL()
  1219                     if( !sh4r.t ) {
  1220                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1221                         sh4r.in_delay_slot = 1;
  1222                         sh4r.pc = sh4r.new_pc;
  1223                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1224                         return TRUE;
  1226                     break;
  1227                 default: UNDEF(ir);
  1229             break;
  1230         case 9: /* 1001xxxxxxxxxxxx */
  1231             /* MOV.W   [disp8*2 + pc + 4], Rn */
  1232 	    CHECKSLOTILLEGAL();
  1233 	    tmp = pc + 4 + (DISP8(ir)<<1);
  1234             RN(ir) = MEM_READ_WORD( tmp );
  1235             break;
  1236         case 10:/* 1010dddddddddddd */
  1237             /* BRA     disp12 */
  1238             CHECKSLOTILLEGAL()
  1239             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1240             sh4r.in_delay_slot = 1;
  1241             sh4r.pc = sh4r.new_pc;
  1242             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1243             return TRUE;
  1244         case 11:/* 1011dddddddddddd */
  1245             /* BSR     disp12 */
  1246             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
  1247             CHECKSLOTILLEGAL()
  1248             sh4r.in_delay_slot = 1;
  1249             sh4r.pr = pc + 4;
  1250             sh4r.pc = sh4r.new_pc;
  1251             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1252 	    TRACE_CALL( pc, sh4r.new_pc );
  1253             return TRUE;
  1254         case 12:/* 1100xxxxdddddddd */
  1255         switch( (ir&0x0F00)>>8 ) {
  1256                 case 0: /* MOV.B  R0, [GBR + disp8] */
  1257                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
  1258                     break;
  1259                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
  1260 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1261 		    CHECKWALIGN16( tmp );
  1262                     MEM_WRITE_WORD( tmp, R0 );
  1263                     break;
  1264                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
  1265 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1266 		    CHECKWALIGN32( tmp );
  1267                     MEM_WRITE_LONG( tmp, R0 );
  1268                     break;
  1269                 case 3: /* TRAPA   imm8 */
  1270                     CHECKSLOTILLEGAL()
  1271                     sh4r.in_delay_slot = 1;
  1272                     MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
  1273                     RAISE( EXC_TRAP, EXV_TRAP, 2 );
  1274                     break;
  1275                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1276                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1277                     break;
  1278                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1279 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1280 		    CHECKRALIGN16( tmp );
  1281                     R0 = MEM_READ_WORD( tmp );
  1282                     break;
  1283                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1284 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1285 		    CHECKRALIGN32( tmp );
  1286                     R0 = MEM_READ_LONG( tmp );
  1287                     break;
  1288                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1289 		    CHECKSLOTILLEGAL();
  1290                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1291                     break;
  1292                 case 8: /* TST     imm8, R0 */
  1293                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1294                     break;
  1295                 case 9: /* AND     imm8, R0 */
  1296                     R0 &= UIMM8(ir);
  1297                     break;
  1298                 case 10:/* XOR     imm8, R0 */
  1299                     R0 ^= UIMM8(ir);
  1300                     break;
  1301                 case 11:/* OR      imm8, R0 */
  1302                     R0 |= UIMM8(ir);
  1303                     break;
  1304                 case 12:/* TST.B   imm8, [R0+GBR] */		    
  1305                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1306                     break;
  1307                 case 13:/* AND.B   imm8, [R0+GBR] */
  1308                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1309                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1310                     break;
  1311                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1312                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1313                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1314                     break;
  1315                 case 15:/* OR.B    imm8, [R0+GBR] */
  1316                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1317                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1318                     break;
  1320             break;
  1321         case 13:/* 1101nnnndddddddd */
  1322             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1323 	    CHECKSLOTILLEGAL();
  1324 	    tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1325             RN(ir) = MEM_READ_LONG( tmp );
  1326             break;
  1327         case 14:/* 1110nnnniiiiiiii */
  1328             /* MOV     imm8, Rn */
  1329             RN(ir) = IMM8(ir);
  1330             break;
  1331         case 15:/* 1111xxxxxxxxxxxx */
  1332             CHECKFPUEN();
  1333 	    if( IS_FPU_DOUBLEPREC() ) {
  1334 		switch( ir&0x000F ) {
  1335                 case 0: /* FADD    FRm, FRn */
  1336                     DRN(ir) += DRM(ir);
  1337                     break;
  1338                 case 1: /* FSUB    FRm, FRn */
  1339                     DRN(ir) -= DRM(ir);
  1340                     break;
  1341                 case 2: /* FMUL    FRm, FRn */
  1342                     DRN(ir) = DRN(ir) * DRM(ir);
  1343                     break;
  1344                 case 3: /* FDIV    FRm, FRn */
  1345                     DRN(ir) = DRN(ir) / DRM(ir);
  1346                     break;
  1347                 case 4: /* FCMP/EQ FRm, FRn */
  1348                     sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
  1349                     break;
  1350                 case 5: /* FCMP/GT FRm, FRn */
  1351                     sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
  1352                     break;
  1353                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1354                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1355                     break;
  1356                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1357                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1358                     break;
  1359                 case 8: /* FMOV.S  [Rm], FRn */
  1360                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1361                     break;
  1362                 case 9: /* FMOV.S  [Rm++], FRn */
  1363                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1364                     RM(ir) += FP_WIDTH;
  1365                     break;
  1366                 case 10:/* FMOV.S  FRm, [Rn] */
  1367                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1368                     break;
  1369                 case 11:/* FMOV.S  FRm, [--Rn] */
  1370                     RN(ir) -= FP_WIDTH;
  1371                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1372                     break;
  1373                 case 12:/* FMOV    FRm, FRn */
  1374 		    if( IS_FPU_DOUBLESIZE() )
  1375 			DRN(ir) = DRM(ir);
  1376 		    else
  1377 			FRN(ir) = FRM(ir);
  1378                     break;
  1379                 case 13:
  1380                     switch( (ir&0x00F0) >> 4 ) {
  1381 		    case 0: /* FSTS    FPUL, FRn */
  1382 			FRN(ir) = FPULf;
  1383 			break;
  1384 		    case 1: /* FLDS    FRn,FPUL */
  1385 			FPULf = FRN(ir);
  1386 			break;
  1387 		    case 2: /* FLOAT   FPUL, FRn */
  1388 			DRN(ir) = (float)FPULi;
  1389 			break;
  1390 		    case 3: /* FTRC    FRn, FPUL */
  1391 			dtmp = DRN(ir);
  1392 			if( dtmp >= MAX_INTF )
  1393 			    FPULi = MAX_INT;
  1394 			else if( dtmp <= MIN_INTF )
  1395 			    FPULi = MIN_INT;
  1396 			else 
  1397 			    FPULi = (int32_t)dtmp;
  1398 			break;
  1399 		    case 4: /* FNEG    FRn */
  1400 			DRN(ir) = -DRN(ir);
  1401 			break;
  1402 		    case 5: /* FABS    FRn */
  1403 			DRN(ir) = fabs(DRN(ir));
  1404 			break;
  1405 		    case 6: /* FSQRT   FRn */
  1406 			DRN(ir) = sqrt(DRN(ir));
  1407 			break;
  1408 		    case 7: /* FSRRA FRn */
  1409 			/* NO-OP when PR=1 */
  1410 			break;
  1411 		    case 8: /* FLDI0   FRn */
  1412 			DRN(ir) = 0.0;
  1413 			break;
  1414 		    case 9: /* FLDI1   FRn */
  1415 			DRN(ir) = 1.0;
  1416 			break;
  1417 		    case 10: /* FCNVSD FPUL, DRn */
  1418 			if( ! IS_FPU_DOUBLESIZE() )
  1419 			    DRN(ir) = (double)FPULf;
  1420 			break;
  1421 		    case 11: /* FCNVDS DRn, FPUL */
  1422 			if( ! IS_FPU_DOUBLESIZE() )
  1423 			    FPULf = (float)DRN(ir);
  1424 			break;
  1425 		    case 14:/* FIPR    FVm, FVn */
  1426 			/* NO-OP when PR=1 */
  1427 			break;
  1428 		    case 15:
  1429 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1430 			    /* NO-OP when PR=1 */
  1431 			    break;
  1433 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */	
  1434 			    /* NO-OP when PR=1 */
  1435 			    break;
  1437 			else if( ir == 0xFBFD ) {
  1438 			    /* FRCHG   */
  1439 			    sh4r.fpscr ^= FPSCR_FR;
  1440 			    break;
  1442 			else if( ir == 0xF3FD ) {
  1443 			    /* FSCHG   */
  1444 			    sh4r.fpscr ^= FPSCR_SZ;
  1445 			    break;
  1447 		    default: UNDEF(ir);
  1449                     break;
  1450                 case 14:/* FMAC    FR0, FRm, FRn */
  1451                     DRN(ir) += DRM(ir)*DR0;
  1452                     break;
  1453                 default: UNDEF(ir);
  1455 	    } else { /* Single precision */
  1456 		switch( ir&0x000F ) {
  1457                 case 0: /* FADD    FRm, FRn */
  1458                     FRN(ir) += FRM(ir);
  1459                     break;
  1460                 case 1: /* FSUB    FRm, FRn */
  1461                     FRN(ir) -= FRM(ir);
  1462                     break;
  1463                 case 2: /* FMUL    FRm, FRn */
  1464                     FRN(ir) = FRN(ir) * FRM(ir);
  1465                     break;
  1466                 case 3: /* FDIV    FRm, FRn */
  1467                     FRN(ir) = FRN(ir) / FRM(ir);
  1468                     break;
  1469                 case 4: /* FCMP/EQ FRm, FRn */
  1470                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1471                     break;
  1472                 case 5: /* FCMP/GT FRm, FRn */
  1473                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1474                     break;
  1475                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1476                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1477                     break;
  1478                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1479                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1480                     break;
  1481                 case 8: /* FMOV.S  [Rm], FRn */
  1482                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1483                     break;
  1484                 case 9: /* FMOV.S  [Rm++], FRn */
  1485                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1486                     RM(ir) += FP_WIDTH;
  1487                     break;
  1488                 case 10:/* FMOV.S  FRm, [Rn] */
  1489                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1490                     break;
  1491                 case 11:/* FMOV.S  FRm, [--Rn] */
  1492                     RN(ir) -= FP_WIDTH;
  1493                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1494                     break;
  1495                 case 12:/* FMOV    FRm, FRn */
  1496 		    if( IS_FPU_DOUBLESIZE() )
  1497 			DRN(ir) = DRM(ir);
  1498 		    else
  1499 			FRN(ir) = FRM(ir);
  1500                     break;
  1501                 case 13:
  1502                     switch( (ir&0x00F0) >> 4 ) {
  1503 		    case 0: /* FSTS    FPUL, FRn */
  1504 			FRN(ir) = FPULf;
  1505 			break;
  1506 		    case 1: /* FLDS    FRn,FPUL */
  1507 			FPULf = FRN(ir);
  1508 			break;
  1509 		    case 2: /* FLOAT   FPUL, FRn */
  1510 			FRN(ir) = (float)FPULi;
  1511 			break;
  1512 		    case 3: /* FTRC    FRn, FPUL */
  1513 			ftmp = FRN(ir);
  1514 			if( ftmp >= MAX_INTF )
  1515 			    FPULi = MAX_INT;
  1516 			else if( ftmp <= MIN_INTF )
  1517 			    FPULi = MIN_INT;
  1518 			else
  1519 			    FPULi = (int32_t)ftmp;
  1520 			break;
  1521 		    case 4: /* FNEG    FRn */
  1522 			FRN(ir) = -FRN(ir);
  1523 			break;
  1524 		    case 5: /* FABS    FRn */
  1525 			FRN(ir) = fabsf(FRN(ir));
  1526 			break;
  1527 		    case 6: /* FSQRT   FRn */
  1528 			FRN(ir) = sqrtf(FRN(ir));
  1529 			break;
  1530 		    case 7: /* FSRRA FRn */
  1531 			FRN(ir) = 1.0/sqrtf(FRN(ir));
  1532 			break;
  1533 		    case 8: /* FLDI0   FRn */
  1534 			FRN(ir) = 0.0;
  1535 			break;
  1536 		    case 9: /* FLDI1   FRn */
  1537 			FRN(ir) = 1.0;
  1538 			break;
  1539 		    case 10: /* FCNVSD FPUL, DRn */
  1540 			break;
  1541 		    case 11: /* FCNVDS DRn, FPUL */
  1542 			break;
  1543 		    case 14:/* FIPR    FVm, FVn */
  1544                             /* FIXME: This is not going to be entirely accurate
  1545                              * as the SH4 instruction is less precise. Also
  1546                              * need to check for 0s and infinities.
  1547                              */
  1549                             int tmp2 = FVN(ir);
  1550                             tmp = FVM(ir);
  1551                             FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1552                                 FR(tmp+1)*FR(tmp2+1) +
  1553                                 FR(tmp+2)*FR(tmp2+2) +
  1554                                 FR(tmp+3)*FR(tmp2+3);
  1555                             break;
  1557 		    case 15:
  1558 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1559 			    tmp = FVN(ir);
  1560 			    float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  1561 			    FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
  1562 				XF(8)*fv[2] + XF(12)*fv[3];
  1563 			    FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
  1564 				XF(9)*fv[2] + XF(13)*fv[3];
  1565 			    FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
  1566 				XF(10)*fv[2] + XF(14)*fv[3];
  1567 			    FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
  1568 				XF(11)*fv[2] + XF(15)*fv[3];
  1569 			    break;
  1571 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1572 			    float angle = (((float)(short)(FPULi>>16)) +
  1573 					   (((float)(FPULi&0xFFFF))/65536.0)) *
  1574 				2 * M_PI;
  1575 			    int reg = FRNn(ir);
  1576 			    FR(reg) = sinf(angle);
  1577 			    FR(reg+1) = cosf(angle);
  1578 			    break;
  1580 			else if( ir == 0xFBFD ) {
  1581 			    /* FRCHG   */
  1582 			    sh4r.fpscr ^= FPSCR_FR;
  1583 			    break;
  1585 			else if( ir == 0xF3FD ) {
  1586 			    /* FSCHG   */
  1587 			    sh4r.fpscr ^= FPSCR_SZ;
  1588 			    break;
  1590 		    default: UNDEF(ir);
  1592                     break;
  1593                 case 14:/* FMAC    FR0, FRm, FRn */
  1594                     FRN(ir) += FRM(ir)*FR0;
  1595                     break;
  1596                 default: UNDEF(ir);
  1599 	    break;
  1601     sh4r.pc = sh4r.new_pc;
  1602     sh4r.new_pc += 2;
  1603     sh4r.in_delay_slot = 0;
.