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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 19:9da7a8e38f9d
prev16:f383e7640da4
next23:1ec3acd0594d
author nkeynes
date Thu Dec 22 07:38:12 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Implement 95% of the SCIF serial interface
Implement basic load_bin_file function to try to load demos directly
Update TMU to run all 3 timers, start on general timing
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     1 #include "dream.h"
     2 #include "video.h"
     3 #include "mem.h"
     4 #include "asic.h"
     5 #include "modules.h"
     6 #include "pvr2.h"
     7 #define MMIO_IMPL
     8 #include "pvr2.h"
    10 char *video_base;
    12 void pvr2_init( void );
    14 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, NULL,
    15 					NULL, NULL };
    17 void pvr2_init( void )
    18 {
    19     register_io_region( &mmio_region_PVR2 );
    20     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    21 }
    23 uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
    24 int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
    25 char *frame_start; /* current video start address (in real memory) */
    27 /*
    28  * Display the next frame, copying the current contents of video ram to
    29  * the window. If the video configuration has changed, first recompute the
    30  * new frame size/depth.
    31  */
    32 void pvr2_next_frame( void )
    33 {
    34     if( bChanged ) {
    35         int dispsize = MMIO_READ( PVR2, DISPSIZE );
    36         int dispmode = MMIO_READ( PVR2, DISPMODE );
    37         int vidcfg = MMIO_READ( PVR2, VIDCFG );
    38         vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
    39         vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
    40         vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
    41         vid_col = (dispmode & DISPMODE_COL);
    42         frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
    43         interlaced = (vidcfg & VIDCFG_I ? 1 : 0);
    44         bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & VIDCFG_VO ) ? 1 : 0;
    45         vid_size = (vid_ppl * vid_lpf) << (interlaced ? 3 : 2);
    46         vid_hres = vid_ppl;
    47         vid_vres = vid_lpf;
    48         if( interlaced ) vid_vres <<= 1;
    49         switch( vid_col ) {
    50             case MODE_RGB15:
    51             case MODE_RGB16: vid_hres <<= 1; break;
    52             case MODE_RGB24: vid_hres *= 3; break;
    53             case MODE_RGB32: vid_hres <<= 2; break;
    54         }
    55         vid_hres >>= 2;
    56         video_update_size( vid_hres, vid_vres, vid_col );
    57         bChanged = 0;
    58     }
    59     if( bEnabled ) {
    60         /* Assume bit depths match for now... */
    61         memcpy( video_data, frame_start, vid_size );
    62     } else {
    63         memset( video_data, 0, vid_size );
    64     }
    65     video_update_frame();
    66     asic_event( EVENT_SCANLINE1 );
    67     asic_event( EVENT_SCANLINE2 );
    68     asic_event( EVENT_RETRACE );
    69 }
    71 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
    72 {
    73     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
    74         MMIO_WRITE( PVR2, reg, val );
    75         /* I don't want to hear about these */
    76         return;
    77     }
    79     INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
    80           MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
    82     switch(reg) {
    83         case DISPSIZE: bChanged = 1;
    84         case DISPMODE: bChanged = 1;
    85         case DISPADDR1: bChanged = 1;
    86         case DISPADDR2: bChanged = 1;
    87         case VIDCFG: bChanged = 1;
    88             break;
    90     }
    91     MMIO_WRITE( PVR2, reg, val );
    92 }
    94 MMIO_REGION_READ_FN( PVR2, reg )
    95 {
    96     switch( reg ) {
    97         case BEAMPOS:
    98             return sh4r.icount&0x20 ? 0x2000 : 1;
    99         default:
   100             return MMIO_READ( PVR2, reg );
   101     }
   102 }
   104 void pvr2_set_base_address( uint32_t base ) 
   105 {
   106     mmio_region_PVR2_write( DISPADDR1, base );
   107 }
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