filename | src/sh4/sh4core.h |
changeset | 10:c898b37506e0 |
prev | 2:42349f6ea216 |
next | 23:1ec3acd0594d |
author | nkeynes |
date | Thu Dec 22 07:38:12 2005 +0000 (18 years ago) |
permissions | -rw-r--r-- |
last change | Implement 95% of the SCIF serial interface Implement basic load_bin_file function to try to load demos directly Update TMU to run all 3 timers, start on general timing |
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1 /**
2 * $Id: sh4core.h,v 1.3 2005-12-11 05:15:36 nkeynes Exp $
3 *
4 * This file defines the public functions exported by the SH4 core, except
5 * for disassembly functions defined in sh4dasm.h
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19 #ifndef sh4core_H
20 #define sh4core_H 1
22 #include <stdint.h>
24 #ifdef __cplusplus
25 extern "C" {
26 #if 0
27 }
28 #endif
29 #endif
31 struct sh4_registers {
32 uint32_t r[16];
33 uint32_t r_bank[8]; /* hidden banked registers */
34 uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
35 uint32_t pr, pc, fpul, fpscr;
36 uint64_t mac;
37 uint32_t m, q, s, t; /* really boolean - 0 or 1 */
38 float fr[2][16];
40 int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
42 uint32_t new_pc; /* Not a real register, but used to handle delay slots */
43 uint32_t icount; /* Also not a real register, instruction counter */
44 uint32_t int_pending; /* flag set by the INTC = pending priority level */
45 int in_delay_slot; /* flag to indicate the current instruction is in
46 * a delay slot (certain rules apply) */
47 };
49 extern struct sh4_registers sh4r;
51 /* Public functions */
53 void sh4_init( void );
54 void sh4_reset( void );
55 void sh4_run( void );
56 void sh4_runto( uint32_t pc, uint32_t count );
57 void sh4_runfor( uint32_t count );
58 int sh4_isrunning( void );
59 void sh4_stop( void );
60 void sh4_set_pc( int );
61 void sh4_execute_instruction( void );
62 void sh4_raise_exception( int, int );
64 /* SH4 Memory */
65 int32_t sh4_read_long( uint32_t addr );
66 int32_t sh4_read_word( uint32_t addr );
67 int32_t sh4_read_byte( uint32_t addr );
68 void sh4_write_long( uint32_t addr, uint32_t val );
69 void sh4_write_word( uint32_t addr, uint32_t val );
70 void sh4_write_byte( uint32_t addr, uint32_t val );
71 int32_t sh4_read_phys_word( uint32_t addr );
73 void run_timers( int );
75 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
76 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
77 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
78 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
79 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
80 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
82 /* Status Register (SR) bits */
83 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
84 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
85 #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
86 #define SR_FD 0x00008000 /* FPU disable */
87 #define SR_M 0x00000200
88 #define SR_Q 0x00000100
89 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
90 #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
91 #define SR_T 0x00000001 /* True/false or carry/borrow */
92 #define SR_MASK 0x700083F3
93 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
95 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
96 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
97 #define SH4_INT_PENDING() (sh4r.int_pending && !sh4r.in_delay_slot)
99 #define FPSCR_FR 0x00200000 /* FPU register bank */
100 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
101 #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
102 #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
103 #define FPSCR_CAUSE 0x0003F000
104 #define FPSCR_ENABLE 0x00000F80
105 #define FPSCR_FLAG 0x0000007C
106 #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
108 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
109 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
110 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
112 #define FR sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]
113 #define XF sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]
115 /* Exceptions (for use with sh4_raise_exception) */
117 #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
118 #define EX_SLOT_ILLEGAL 0x1A0, 0x100
119 #define EX_TLB_MISS_READ 0x040, 0x400
120 #define EX_TLB_MISS_WRITE 0x060, 0x400
121 #define EX_INIT_PAGE_WRITE 0x080, 0x100
122 #define EX_TLB_PROT_READ 0x0A0, 0x100
123 #define EX_TLB_PROT_WRITE 0x0C0, 0x100
124 #define EX_DATA_ADDR_READ 0x0E0, 0x100
125 #define EX_DATA_ADDR_WRITE 0x100, 0x100
126 #define EX_FPU_EXCEPTION 0x120, 0x100
127 #define EX_TRAPA 0x160, 0x100
128 #define EX_BREAKPOINT 0x1E0, 0x100
129 #define EX_FPU_DISABLED 0x800, 0x100
130 #define EX_SLOT_FPU_DISABLED 0x820, 0x100
132 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
134 #ifdef __cplusplus
135 }
136 #endif
137 #endif
.