filename | src/sh4/sh4.c |
changeset | 1125:9dd5dee45db9 |
prev | 1112:4cac5e474d4c |
next | 1171:d644413208a3 |
author | nkeynes |
date | Mon Sep 13 10:13:42 2010 +1000 (13 years ago) |
permissions | -rw-r--r-- |
last change | Implement shadow-execution 'core' to run translator + interpreter side by side (for testing) |
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1 /**
2 * $Id$
3 *
4 * SH4 parent module for all CPU modes and SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include <setjmp.h>
23 #include <assert.h>
24 #include "lxdream.h"
25 #include "dreamcast.h"
26 #include "cpu.h"
27 #include "mem.h"
28 #include "clock.h"
29 #include "eventq.h"
30 #include "syscall.h"
31 #include "sh4/intc.h"
32 #include "sh4/mmu.h"
33 #include "sh4/sh4core.h"
34 #include "sh4/sh4dasm.h"
35 #include "sh4/sh4mmio.h"
36 #include "sh4/sh4stat.h"
37 #include "sh4/sh4trans.h"
38 #include "xlat/xltcache.h"
40 #ifndef M_PI
41 #define M_PI 3.14159265358979323846264338327950288
42 #endif
44 void sh4_init( void );
45 void sh4_poweron_reset( void );
46 void sh4_start( void );
47 void sh4_stop( void );
48 void sh4_save_state( FILE *f );
49 int sh4_load_state( FILE *f );
50 size_t sh4_debug_read_phys( unsigned char *buf, uint32_t addr, size_t length );
51 size_t sh4_debug_write_phys( uint32_t addr, unsigned char *buf, size_t length );
52 size_t sh4_debug_read_vma( unsigned char *buf, uint32_t addr, size_t length );
53 size_t sh4_debug_write_vma( uint32_t addr, unsigned char *buf, size_t length );
55 uint32_t sh4_run_slice( uint32_t );
57 /* Note: this must match GDB's ordering */
58 const struct reg_desc_struct sh4_reg_map[] =
59 { {"R0", REG_TYPE_INT, &sh4r.r[0]}, {"R1", REG_TYPE_INT, &sh4r.r[1]},
60 {"R2", REG_TYPE_INT, &sh4r.r[2]}, {"R3", REG_TYPE_INT, &sh4r.r[3]},
61 {"R4", REG_TYPE_INT, &sh4r.r[4]}, {"R5", REG_TYPE_INT, &sh4r.r[5]},
62 {"R6", REG_TYPE_INT, &sh4r.r[6]}, {"R7", REG_TYPE_INT, &sh4r.r[7]},
63 {"R8", REG_TYPE_INT, &sh4r.r[8]}, {"R9", REG_TYPE_INT, &sh4r.r[9]},
64 {"R10",REG_TYPE_INT, &sh4r.r[10]}, {"R11",REG_TYPE_INT, &sh4r.r[11]},
65 {"R12",REG_TYPE_INT, &sh4r.r[12]}, {"R13",REG_TYPE_INT, &sh4r.r[13]},
66 {"R14",REG_TYPE_INT, &sh4r.r[14]}, {"R15",REG_TYPE_INT, &sh4r.r[15]},
67 {"PC", REG_TYPE_INT, &sh4r.pc}, {"PR", REG_TYPE_INT, &sh4r.pr},
68 {"GBR", REG_TYPE_INT, &sh4r.gbr}, {"VBR",REG_TYPE_INT, &sh4r.vbr},
69 {"MACH",REG_TYPE_INT, ((uint32_t *)&sh4r.mac)+1}, {"MACL",REG_TYPE_INT, &sh4r.mac},
70 {"SR", REG_TYPE_INT, &sh4r.sr},
71 {"FPUL", REG_TYPE_INT, &sh4r.fpul.i}, {"FPSCR", REG_TYPE_INT, &sh4r.fpscr},
73 {"FR0", REG_TYPE_FLOAT, &sh4r.fr[0][1] },{"FR1", REG_TYPE_FLOAT, &sh4r.fr[0][0]},
74 {"FR2", REG_TYPE_FLOAT, &sh4r.fr[0][3] },{"FR3", REG_TYPE_FLOAT, &sh4r.fr[0][2]},
75 {"FR4", REG_TYPE_FLOAT, &sh4r.fr[0][5] },{"FR5", REG_TYPE_FLOAT, &sh4r.fr[0][4]},
76 {"FR6", REG_TYPE_FLOAT, &sh4r.fr[0][7] },{"FR7", REG_TYPE_FLOAT, &sh4r.fr[0][6]},
77 {"FR8", REG_TYPE_FLOAT, &sh4r.fr[0][9] },{"FR9", REG_TYPE_FLOAT, &sh4r.fr[0][8]},
78 {"FR10", REG_TYPE_FLOAT, &sh4r.fr[0][11] },{"FR11", REG_TYPE_FLOAT, &sh4r.fr[0][10]},
79 {"FR12", REG_TYPE_FLOAT, &sh4r.fr[0][13] },{"FR13", REG_TYPE_FLOAT, &sh4r.fr[0][12]},
80 {"FR14", REG_TYPE_FLOAT, &sh4r.fr[0][15] },{"FR15", REG_TYPE_FLOAT, &sh4r.fr[0][14]},
82 {"SSR",REG_TYPE_INT, &sh4r.ssr}, {"SPC", REG_TYPE_INT, &sh4r.spc},
84 {"R0B0", REG_TYPE_INT, NULL}, {"R1B0", REG_TYPE_INT, NULL},
85 {"R2B0", REG_TYPE_INT, NULL}, {"R3B0", REG_TYPE_INT, NULL},
86 {"R4B0", REG_TYPE_INT, NULL}, {"R5B0", REG_TYPE_INT, NULL},
87 {"R6B0", REG_TYPE_INT, NULL}, {"R7B0", REG_TYPE_INT, NULL},
88 {"R0B1", REG_TYPE_INT, NULL}, {"R1B1", REG_TYPE_INT, NULL},
89 {"R2B1", REG_TYPE_INT, NULL}, {"R3B1", REG_TYPE_INT, NULL},
90 {"R4B1", REG_TYPE_INT, NULL}, {"R5B1", REG_TYPE_INT, NULL},
91 {"R6B1", REG_TYPE_INT, NULL}, {"R7B1", REG_TYPE_INT, NULL},
93 {"SGR",REG_TYPE_INT, &sh4r.sgr}, {"DBR", REG_TYPE_INT, &sh4r.dbr},
95 {"XF0", REG_TYPE_FLOAT, &sh4r.fr[1][1] },{"XF1", REG_TYPE_FLOAT, &sh4r.fr[1][0]},
96 {"XF2", REG_TYPE_FLOAT, &sh4r.fr[1][3] },{"XF3", REG_TYPE_FLOAT, &sh4r.fr[1][2]},
97 {"XF4", REG_TYPE_FLOAT, &sh4r.fr[1][5] },{"XF5", REG_TYPE_FLOAT, &sh4r.fr[1][4]},
98 {"XF6", REG_TYPE_FLOAT, &sh4r.fr[1][7] },{"XF7", REG_TYPE_FLOAT, &sh4r.fr[1][6]},
99 {"XF8", REG_TYPE_FLOAT, &sh4r.fr[1][9] },{"XF9", REG_TYPE_FLOAT, &sh4r.fr[1][8]},
100 {"XF10", REG_TYPE_FLOAT, &sh4r.fr[1][11] },{"XF11", REG_TYPE_FLOAT, &sh4r.fr[1][10]},
101 {"XF12", REG_TYPE_FLOAT, &sh4r.fr[1][13] },{"XF13", REG_TYPE_FLOAT, &sh4r.fr[1][12]},
102 {"XF14", REG_TYPE_FLOAT, &sh4r.fr[1][15] },{"XF15", REG_TYPE_FLOAT, &sh4r.fr[1][14]},
104 {NULL, 0, NULL} };
106 void *sh4_get_register( int reg )
107 {
108 if( reg < 0 || reg >= 94 ) {
109 return NULL;
110 } else if( reg < 43 ) {
111 return sh4_reg_map[reg].value;
112 } else if( reg < 51 ) {
113 /* r0b0..r7b0 */
114 if( (sh4r.sr & SR_MDRB) == SR_MDRB ) {
115 /* bank 1 is primary */
116 return &sh4r.r_bank[reg-43];
117 } else {
118 return &sh4r.r[reg-43];
119 }
120 } else if( reg < 59 ) {
121 /* r0b1..r7b1 */
122 if( (sh4r.sr & SR_MDRB) == SR_MDRB ) {
123 /* bank 1 is primary */
124 return &sh4r.r[reg-43];
125 } else {
126 return &sh4r.r_bank[reg-43];
127 }
128 } else {
129 return NULL; /* not supported at the moment */
130 }
131 }
134 const struct cpu_desc_struct sh4_cpu_desc =
135 { "SH4", sh4_disasm_instruction, sh4_get_register, sh4_has_page,
136 sh4_debug_read_phys, sh4_debug_write_phys, sh4_debug_read_vma, sh4_debug_write_vma,
137 sh4_execute_instruction,
138 sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2,
139 (char *)&sh4r, sizeof(sh4r), sh4_reg_map, 23, 59,
140 &sh4r.pc };
142 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_poweron_reset,
143 sh4_start, sh4_run_slice, sh4_stop,
144 sh4_save_state, sh4_load_state };
146 struct sh4_registers sh4r __attribute__((aligned(16)));
147 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
148 int sh4_breakpoint_count = 0;
150 gboolean sh4_starting = FALSE;
151 static gboolean sh4_use_translator = FALSE;
152 static jmp_buf sh4_exit_jmp_buf;
153 static gboolean sh4_running = FALSE;
154 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
156 /* At the moment this is a dummy event to mark the end of the
157 * timeslice
158 */
159 void sh4_dummy_event(int eventid)
160 {
161 }
163 void sh4_set_core( sh4core_t core )
164 {
165 // No-op if the translator was not built
166 #ifdef SH4_TRANSLATOR
167 if( core != SH4_INTERPRET ) {
168 sh4_translate_init();
169 sh4_use_translator = TRUE;
170 if( core == SH4_SHADOW ) {
171 sh4_shadow_init();
172 }
173 } else {
174 sh4_use_translator = FALSE;
175 }
176 #endif
177 }
179 gboolean sh4_translate_is_enabled()
180 {
181 return sh4_use_translator;
182 }
184 void sh4_init(void)
185 {
186 register_io_regions( mmio_list_sh4mmio );
187 register_event_callback( EVENT_ENDTIMESLICE, sh4_dummy_event );
188 MMU_init();
189 TMU_init();
190 xlat_cache_init();
191 sh4_poweron_reset();
192 #ifdef ENABLE_SH4STATS
193 sh4_stats_reset();
194 #endif
195 }
197 void sh4_start(void)
198 {
199 sh4_starting = TRUE;
200 }
202 void sh4_poweron_reset(void)
203 {
204 /* zero everything out, for the sake of having a consistent state. */
205 memset( &sh4r, 0, sizeof(sh4r) );
206 if( sh4_use_translator ) {
207 xlat_flush_cache();
208 }
210 /* Resume running if we were halted */
211 sh4r.sh4_state = SH4_STATE_RUNNING;
213 sh4r.pc = 0xA0000000;
214 sh4r.new_pc= 0xA0000002;
215 sh4r.vbr = 0x00000000;
216 sh4r.fpscr = 0x00040001;
217 sh4_write_sr(0x700000F0);
219 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
220 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
222 /* Peripheral modules */
223 CPG_reset();
224 INTC_reset();
225 PMM_reset();
226 TMU_reset();
227 SCIF_reset();
228 CCN_reset();
229 MMU_reset();
230 }
232 void sh4_stop(void)
233 {
234 if( sh4_use_translator ) {
235 /* If we were running with the translator, update new_pc and in_delay_slot */
236 sh4r.new_pc = sh4r.pc+2;
237 sh4r.in_delay_slot = FALSE;
238 }
240 }
242 /**
243 * Execute a timeslice using translated code only (ie translate/execute loop)
244 */
245 uint32_t sh4_run_slice( uint32_t nanosecs )
246 {
247 sh4r.slice_cycle = 0;
249 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
250 sh4_sleep_run_slice(nanosecs);
251 }
253 /* Setup for sudden vm exits */
254 switch( setjmp(sh4_exit_jmp_buf) ) {
255 case CORE_EXIT_BREAKPOINT:
256 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
257 /* fallthrough */
258 case CORE_EXIT_HALT:
259 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
260 TMU_run_slice( sh4r.slice_cycle );
261 SCIF_run_slice( sh4r.slice_cycle );
262 PMM_run_slice( sh4r.slice_cycle );
263 dreamcast_stop();
264 return sh4r.slice_cycle;
265 }
266 case CORE_EXIT_SYSRESET:
267 dreamcast_reset();
268 break;
269 case CORE_EXIT_SLEEP:
270 sh4_sleep_run_slice(nanosecs);
271 break;
272 case CORE_EXIT_FLUSH_ICACHE:
273 xlat_flush_cache();
274 break;
275 }
277 sh4_running = TRUE;
279 /* Execute the core's real slice */
280 #ifdef SH4_TRANSLATOR
281 if( sh4_use_translator ) {
282 sh4_translate_run_slice(nanosecs);
283 } else {
284 sh4_emulate_run_slice(nanosecs);
285 }
286 #else
287 sh4_emulate_run_slice(nanosecs);
288 #endif
290 /* And finish off the peripherals afterwards */
292 sh4_running = FALSE;
293 sh4_starting = FALSE;
294 sh4r.slice_cycle = nanosecs;
295 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
296 TMU_run_slice( nanosecs );
297 SCIF_run_slice( nanosecs );
298 PMM_run_slice( sh4r.slice_cycle );
299 }
300 return nanosecs;
301 }
303 void sh4_core_exit( int exit_code )
304 {
305 if( sh4_running ) {
306 #ifdef SH4_TRANSLATOR
307 if( sh4_use_translator ) {
308 if( exit_code == CORE_EXIT_EXCEPTION ) {
309 sh4_translate_exception_exit_recover();
310 } else {
311 sh4_translate_exit_recover();
312 }
313 }
314 #endif
315 if( exit_code != CORE_EXIT_EXCEPTION &&
316 exit_code != CORE_EXIT_BREAKPOINT ) {
317 sh4_finalize_instruction();
318 }
319 // longjmp back into sh4_run_slice
320 sh4_running = FALSE;
321 longjmp(sh4_exit_jmp_buf, exit_code);
322 }
323 }
325 void sh4_save_state( FILE *f )
326 {
327 if( sh4_use_translator ) {
328 /* If we were running with the translator, update new_pc and in_delay_slot */
329 sh4r.new_pc = sh4r.pc+2;
330 sh4r.in_delay_slot = FALSE;
331 }
333 fwrite( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
334 MMU_save_state( f );
335 CCN_save_state( f );
336 PMM_save_state( f );
337 INTC_save_state( f );
338 TMU_save_state( f );
339 SCIF_save_state( f );
340 }
342 int sh4_load_state( FILE * f )
343 {
344 if( sh4_use_translator ) {
345 xlat_flush_cache();
346 }
347 fread( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
348 sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
349 MMU_load_state( f );
350 CCN_load_state( f );
351 PMM_load_state( f );
352 INTC_load_state( f );
353 TMU_load_state( f );
354 return SCIF_load_state( f );
355 }
357 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
358 {
359 sh4_breakpoints[sh4_breakpoint_count].address = pc;
360 sh4_breakpoints[sh4_breakpoint_count].type = type;
361 if( sh4_use_translator ) {
362 xlat_invalidate_word( pc );
363 }
364 sh4_breakpoint_count++;
365 }
367 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
368 {
369 int i;
371 for( i=0; i<sh4_breakpoint_count; i++ ) {
372 if( sh4_breakpoints[i].address == pc &&
373 sh4_breakpoints[i].type == type ) {
374 while( ++i < sh4_breakpoint_count ) {
375 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
376 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
377 }
378 if( sh4_use_translator ) {
379 xlat_invalidate_word( pc );
380 }
381 sh4_breakpoint_count--;
382 return TRUE;
383 }
384 }
385 return FALSE;
386 }
388 int sh4_get_breakpoint( uint32_t pc )
389 {
390 int i;
391 for( i=0; i<sh4_breakpoint_count; i++ ) {
392 if( sh4_breakpoints[i].address == pc )
393 return sh4_breakpoints[i].type;
394 }
395 return 0;
396 }
398 void sh4_set_pc( int pc )
399 {
400 sh4r.pc = pc;
401 sh4r.new_pc = pc+2;
402 }
404 /**
405 * Dump all SH4 core information for crash-dump purposes
406 */
407 void sh4_crashdump()
408 {
409 cpu_print_registers( stderr, &sh4_cpu_desc );
410 #ifdef SH4_TRANSLATOR
411 if( sh4_use_translator ) {
412 sh4_translate_crashdump();
413 } /* Nothing really to print for emu core */
414 #endif
415 }
418 /******************************* Support methods ***************************/
420 static void sh4_switch_banks( )
421 {
422 uint32_t tmp[8];
424 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
425 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
426 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
427 }
429 void FASTCALL sh4_switch_fr_banks()
430 {
431 int i;
432 for( i=0; i<16; i++ ) {
433 float tmp = sh4r.fr[0][i];
434 sh4r.fr[0][i] = sh4r.fr[1][i];
435 sh4r.fr[1][i] = tmp;
436 }
437 }
439 void FASTCALL sh4_write_sr( uint32_t newval )
440 {
441 int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
442 int newbank = (newval&SR_MDRB) == SR_MDRB;
443 if( oldbank != newbank )
444 sh4_switch_banks();
445 sh4r.sr = newval & SR_MASK;
446 sh4r.t = (newval&SR_T) ? 1 : 0;
447 sh4r.s = (newval&SR_S) ? 1 : 0;
448 sh4r.m = (newval&SR_M) ? 1 : 0;
449 sh4r.q = (newval&SR_Q) ? 1 : 0;
450 sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
451 intc_mask_changed();
452 }
454 void FASTCALL sh4_write_fpscr( uint32_t newval )
455 {
456 if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
457 sh4_switch_fr_banks();
458 }
459 sh4r.fpscr = newval & FPSCR_MASK;
460 sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
461 }
463 uint32_t FASTCALL sh4_read_sr( void )
464 {
465 /* synchronize sh4r.sr with the various bitflags */
466 sh4r.sr &= SR_MQSTMASK;
467 if( sh4r.t ) sh4r.sr |= SR_T;
468 if( sh4r.s ) sh4r.sr |= SR_S;
469 if( sh4r.m ) sh4r.sr |= SR_M;
470 if( sh4r.q ) sh4r.sr |= SR_Q;
471 return sh4r.sr;
472 }
474 /**
475 * Raise a CPU reset exception with the specified exception code.
476 */
477 void FASTCALL sh4_raise_reset( int code )
478 {
479 MMIO_WRITE(MMU,EXPEVT,code);
480 sh4r.vbr = 0x00000000;
481 sh4r.pc = 0xA0000000;
482 sh4r.new_pc = sh4r.pc + 2;
483 sh4r.in_delay_slot = 0;
484 sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)&(~SR_FD) );
486 /* Peripheral manual reset (FIXME: incomplete) */
487 INTC_reset();
488 SCIF_reset();
489 MMU_reset();
490 }
492 void FASTCALL sh4_raise_tlb_multihit( sh4vma_t vpn )
493 {
494 MMIO_WRITE( MMU, TEA, vpn );
495 MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) );
496 sh4_raise_reset( EXC_TLB_MULTI_HIT );
497 }
499 /**
500 * Raise a general CPU exception for the specified exception code.
501 * (NOT for TRAPA or TLB exceptions)
502 */
503 void FASTCALL sh4_raise_exception( int code )
504 {
505 if( sh4r.sr & SR_BL ) {
506 sh4_raise_reset( EXC_MANUAL_RESET );
507 } else {
508 sh4r.spc = sh4r.pc;
509 sh4r.ssr = sh4_read_sr();
510 sh4r.sgr = sh4r.r[15];
511 MMIO_WRITE(MMU,EXPEVT, code);
512 sh4r.pc = sh4r.vbr + EXV_EXCEPTION;
513 sh4r.new_pc = sh4r.pc + 2;
514 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB );
515 sh4r.in_delay_slot = 0;
516 }
517 }
519 void FASTCALL sh4_raise_trap( int trap )
520 {
521 MMIO_WRITE( MMU, TRA, trap<<2 );
522 MMIO_WRITE( MMU, EXPEVT, EXC_TRAP );
523 sh4r.spc = sh4r.pc;
524 sh4r.ssr = sh4_read_sr();
525 sh4r.sgr = sh4r.r[15];
526 sh4r.pc = sh4r.vbr + EXV_EXCEPTION;
527 sh4r.new_pc = sh4r.pc + 2;
528 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB );
529 sh4r.in_delay_slot = 0;
530 }
532 void FASTCALL sh4_raise_tlb_exception( int code, sh4vma_t vpn )
533 {
534 MMIO_WRITE( MMU, TEA, vpn );
535 MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) );
536 MMIO_WRITE( MMU, EXPEVT, code );
537 sh4r.spc = sh4r.pc;
538 sh4r.ssr = sh4_read_sr();
539 sh4r.sgr = sh4r.r[15];
540 sh4r.pc = sh4r.vbr + EXV_TLBMISS;
541 sh4r.new_pc = sh4r.pc + 2;
542 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB );
543 sh4r.in_delay_slot = 0;
544 }
546 void FASTCALL sh4_accept_interrupt( void )
547 {
548 uint32_t code = intc_accept_interrupt();
549 MMIO_WRITE( MMU, INTEVT, code );
550 sh4r.ssr = sh4_read_sr();
551 sh4r.spc = sh4r.pc;
552 sh4r.sgr = sh4r.r[15];
553 sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
554 sh4r.pc = sh4r.vbr + 0x600;
555 sh4r.new_pc = sh4r.pc + 2;
556 sh4r.in_delay_slot = 0;
557 }
559 void FASTCALL signsat48( void )
560 {
561 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
562 sh4r.mac = 0xFFFF800000000000LL;
563 else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
564 sh4r.mac = 0x00007FFFFFFFFFFFLL;
565 }
567 void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
568 {
569 float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
570 *fr++ = cosf(angle);
571 *fr = sinf(angle);
572 }
574 /**
575 * Enter sleep mode (eg by executing a SLEEP instruction).
576 * Sets sh4_state appropriately and ensures any stopping peripheral modules
577 * are up to date.
578 */
579 void FASTCALL sh4_sleep(void)
580 {
581 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
582 sh4r.sh4_state = SH4_STATE_STANDBY;
583 /* Bring all running peripheral modules up to date, and then halt them. */
584 TMU_run_slice( sh4r.slice_cycle );
585 SCIF_run_slice( sh4r.slice_cycle );
586 PMM_run_slice( sh4r.slice_cycle );
587 } else {
588 if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
589 sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
590 /* Halt DMAC but other peripherals still running */
592 } else {
593 sh4r.sh4_state = SH4_STATE_SLEEP;
594 }
595 }
596 sh4_core_exit( CORE_EXIT_SLEEP );
597 }
599 /**
600 * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
601 * and restarts any peripheral devices that were stopped.
602 */
603 void sh4_wakeup(void)
604 {
605 switch( sh4r.sh4_state ) {
606 case SH4_STATE_STANDBY:
607 break;
608 case SH4_STATE_DEEP_SLEEP:
609 break;
610 case SH4_STATE_SLEEP:
611 break;
612 }
613 sh4r.sh4_state = SH4_STATE_RUNNING;
614 }
616 /**
617 * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
618 * Returns when either the SH4 wakes up (interrupt received) or the end of
619 * the slice is reached. Updates sh4.slice_cycle with the exit time and
620 * returns the same value.
621 */
622 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
623 {
624 int sleep_state = sh4r.sh4_state;
625 assert( sleep_state != SH4_STATE_RUNNING );
627 while( sh4r.event_pending < nanosecs ) {
628 sh4r.slice_cycle = sh4r.event_pending;
629 if( sh4r.event_types & PENDING_EVENT ) {
630 event_execute();
631 }
632 if( sh4r.event_types & PENDING_IRQ ) {
633 sh4_wakeup();
634 return sh4r.slice_cycle;
635 }
636 }
637 sh4r.slice_cycle = nanosecs;
638 return sh4r.slice_cycle;
639 }
642 /**
643 * Compute the matrix tranform of fv given the matrix xf.
644 * Both fv and xf are word-swapped as per the sh4r.fr banks
645 */
646 void FASTCALL sh4_ftrv( float *target )
647 {
648 float fv[4] = { target[1], target[0], target[3], target[2] };
649 target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
650 sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
651 target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
652 sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
653 target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
654 sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
655 target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
656 sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
657 }
659 gboolean sh4_has_page( sh4vma_t vma )
660 {
661 sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
662 return addr != MMU_VMA_ERROR && mem_has_page(addr);
663 }
665 /**
666 * Go through ext_address_space page by page
667 */
668 size_t sh4_debug_read_phys( unsigned char *buf, uint32_t addr, size_t length )
669 {
670 /* Quick and very dirty */
671 unsigned char *region = mem_get_region(addr);
672 if( region == NULL ) {
673 memset( buf, 0, length );
674 } else {
675 memcpy( buf, region, length );
676 }
677 return length;
678 }
680 size_t sh4_debug_write_phys( uint32_t addr, unsigned char *buf, size_t length )
681 {
682 unsigned char *region = mem_get_region(addr);
683 if( region != NULL ) {
684 memcpy( region, buf, length );
685 }
686 return length;
687 }
689 /**
690 * Read virtual memory - for now just go 1K at a time
691 */
692 size_t sh4_debug_read_vma( unsigned char *buf, uint32_t addr, size_t length )
693 {
694 if( IS_TLB_ENABLED() ) {
695 size_t read_len = 0;
696 while( length > 0 ) {
697 sh4addr_t phys = mmu_vma_to_phys_disasm(addr);
698 if( phys == MMU_VMA_ERROR )
699 break;
700 int next_len = 1024 - (phys&0x000003FF);
701 if( next_len >= length ) {
702 next_len = length;
703 }
704 sh4_debug_read_phys( buf, phys, length );
705 buf += next_len;
706 addr += next_len;
707 read_len += next_len;
708 length -= next_len;
709 }
710 return read_len;
711 } else {
712 return sh4_debug_read_phys( buf, addr, length );
713 }
714 }
716 size_t sh4_debug_write_vma( uint32_t addr, unsigned char *buf, size_t length )
717 {
718 if( IS_TLB_ENABLED() ) {
719 size_t read_len = 0;
720 while( length > 0 ) {
721 sh4addr_t phys = mmu_vma_to_phys_disasm(addr);
722 if( phys == MMU_VMA_ERROR )
723 break;
724 int next_len = 1024 - (phys&0x000003FF);
725 if( next_len >= length ) {
726 next_len = length;
727 }
728 sh4_debug_write_phys( phys, buf, length );
729 buf += next_len;
730 addr += next_len;
731 read_len += next_len;
732 length -= next_len;
733 }
734 return read_len;
735 } else {
736 return sh4_debug_write_phys( addr, buf, length );
737 }
738 }
.