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lxdream.org :: lxdream/src/asic.h
lxdream 0.9.1
released Jun 29
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filename src/asic.h
changeset 65:9f124c245fc6
prev56:3224dceaf2a3
next125:49bf45f8210a
author nkeynes
date Tue Jan 03 12:21:45 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Implement blanking (maybe, untested)
Quick hack to generate appropriate events on ta list completion
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     1 /**
     2  * $Id: asic.h,v 1.5 2006-01-03 12:21:45 nkeynes Exp $
     3  *
     4  * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
     5  * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions, 
     6  * although some functions (maple, ide) are implemented elsewhere.
     7  *
     8  * Copyright (c) 2005 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include "mmio.h"
    23 /**
    24  * ASIC interrupts are mappable to any (or all of) 3 actual CPU IRQ lines.
    25  * events selected for IRQA trigger IRQ 13, IRQB => 11 and IRQC => 9.
    26  */
    28 MMIO_REGION_BEGIN( 0x005F6000, ASIC, "System ASIC" )
    29     LONG_PORT( 0x800, PVRDMADEST, PORT_MRW, 0, "PVR DMA Dest Address" )
    30     LONG_PORT( 0x804, PVRDMACNT, PORT_MRW, 0, "PVR DMA Byte Count" )
    31     LONG_PORT( 0x808, PVRDMACTL, PORT_MRW, 0, "PVR DMA Control" )
    32     LONG_PORT( 0x810, ASICUNK1, PORT_MRW, 0, "ASIC <unknown1>" )
    33     LONG_PORT( 0x814, ASICUNK2, PORT_MRW, 0, "ASIC <unknown2>" )
    34     LONG_PORT( 0x818, ASICUNK3, PORT_MRW, 0, "ASIC <unknown3>" )
    35     LONG_PORT( 0x81C, ASICUNK4, PORT_MRW, 0, "ASIC <unknown4>" )
    36     LONG_PORT( 0x884, ASICUNK5, PORT_MRW, 0, "ASIC <unknown5>" )
    37     LONG_PORT( 0x888, ASICUNK6, PORT_MRW, 0, "ASIC <unknown6>" )
    38     LONG_PORT( 0x88C, G2STATUS, PORT_MR, 0, "G2 Bus status" )
    39     LONG_PORT( 0x89C, ASICUNK7, PORT_MRW, 0xB, "Unknown, always 0xB?" )
    40     LONG_PORT( 0x8A0, ASICUNK8, PORT_MRW, 0, "ASIC <unknown8>" )
    41     LONG_PORT( 0x8A4, ASICUNK9, PORT_MRW, 0, "ASIC <unknown9>" )
    42     LONG_PORT( 0x8AC, ASICUNKA, PORT_MRW, 0, "ASIC <unknownA>" )
    43     LONG_PORT( 0x900, PIRQ0, PORT_MRW, 0, "Pending interrupts 0" )
    44     LONG_PORT( 0x904, PIRQ1, PORT_MRW, 0, "Pending interrupts 1" )
    45     LONG_PORT( 0x908, PIRQ2, PORT_MRW, 0, "Pending interrupts 2" )
    46     LONG_PORT( 0x910, IRQA0, PORT_MRW, 0, "IRQ A event map 0" )
    47     LONG_PORT( 0x914, IRQA1, PORT_MRW, 0, "IRQ A event map 1" )
    48     LONG_PORT( 0x918, IRQA2, PORT_MRW, 0, "IRQ A event map 2" )
    49     LONG_PORT( 0x920, IRQB0, PORT_MRW, 0, "IRQ B event map 0" )
    50     LONG_PORT( 0x924, IRQB1, PORT_MRW, 0, "IRQ B event map 1" )
    51     LONG_PORT( 0x928, IRQB2, PORT_MRW, 0, "IRQ B event map 2" )
    52     LONG_PORT( 0x930, IRQC0, PORT_MRW, 0, "IRQ C event map 0" )
    53     LONG_PORT( 0x934, IRQC1, PORT_MRW, 0, "IRQ C event map 1" )
    54     LONG_PORT( 0x938, IRQC2, PORT_MRW, 0, "IRQ C event map 2" )
    55     LONG_PORT( 0x940, ASIC9UNK1, PORT_MRW, 0, "Unknown 1" )
    56     LONG_PORT( 0x944, ASIC9UNK2, PORT_MRW, 0, "Unknown 2" )
    57     LONG_PORT( 0x950, ASIC9UNK3, PORT_MRW, 0, "Unknown 3" )
    58     LONG_PORT( 0x954, ASIC9UNK4, PORT_MRW, 0, "Unknown 4" )
    59 /* ASIC events repeats at 0x980..0x9FF, then the whole region 800..9ff
    60  * repeats at 000..1ff, 200..3ff, 400..5ff, 600..7ff, a00..bff.
    61  * The whole region 800..8ff is long-readable, but since I so far have no idea
    62  * what any of it means (nor have I seen any of it accessed), they're not
    63  * listed above.
    64  */
    67     LONG_PORT( 0xC04, MAPLE_DMA, PORT_MRW, UNDEFINED, "Maple DMA Address" )
    68     LONG_PORT( 0xC10, MAPLE_RESET2, PORT_MRW, UNDEFINED, "Maple Reset 2" )
    69     LONG_PORT( 0xC14, MAPLE_ENABLE, PORT_MRW, UNDEFINED, "Maple Enable" )
    70     LONG_PORT( 0xC18, MAPLE_STATE, PORT_MRW, 0, "Maple State" )
    71     LONG_PORT( 0xC70, MAPLE_UNK1, PORT_MRW, 0, "Maple unknown 1" )
    72     LONG_PORT( 0xC74, MAPLE_UNK2, PORT_MRW, 0, "Maple unknown 2" )
    73     LONG_PORT( 0xC78, MAPLE_UNK3, PORT_MRW, 0, "Maple unknown 3" )
    74     LONG_PORT( 0xC7C, MAPLE_UNK4, PORT_MRW, 0, "Maple unknown 4" )
    75     LONG_PORT( 0xC80, MAPLE_SPEED, PORT_MRW, UNDEFINED, "Maple Speed" )
    76     LONG_PORT( 0xC84, MAPLE_UNK5, PORT_MRW, 0, "Maple unknown 5" )
    77     LONG_PORT( 0xC8C, MAPLE_RESET1, PORT_MRW, UNDEFINED, "Maple Reset 1" )
    78     LONG_PORT( 0xCE8, MAPLE_UNK6, PORT_MRW, 0, "Maple unknown 6" )
    79     LONG_PORT( 0xCF4, MAPLE_SRC, PORT_MRW, 0, "Maple current source" )
    80     LONG_PORT( 0xCF8, MAPLE_DEST1, PORT_MRW, 0, "Maple current destination" )
    81     LONG_PORT( 0xCFC, MAPLE_DEST2, PORT_MRW, 0, "Maple current destination 2?" )
    82 /* Note: Maple registers repeat at 0xD00..0xDFF,
    83  * 0xE00..0xEFF and 0xF00..0xFFF */
    84 MMIO_REGION_END
    86 MMIO_REGION_BEGIN( 0x005F7000, EXTDMA, "ASIC External DMA" )
    87     BYTE_PORT( 0x018, IDEALTSTATUS, PORT_RW, 0, "IDE Device Control / Alt-status" ) /* 10110 */
    88     BYTE_PORT( 0x01C, IDEUNK1, PORT_MRW, 0, "IDE Unknown" )
    89     WORD_PORT( 0x080, IDEDATA, PORT_RW, 0, "IDE Data" )
    90     BYTE_PORT( 0x084, IDEFEAT, PORT_RW, 0, "IDE Feature / Error" )
    91     BYTE_PORT( 0x088, IDECOUNT, PORT_RW, 0, "IDE Sector Count" )
    92     BYTE_PORT( 0x08C, IDELBA0, PORT_RW, 0, "IDE LBA lo" ) /* AKA sector */
    93     BYTE_PORT( 0x090, IDELBA1, PORT_RW, 0, "IDE LBA mid" ) /* AKA Cyl lo */
    94     BYTE_PORT( 0x094, IDELBA2, PORT_RW, 0, "IDE LBA hi" ) /* AKA Cyl hi */
    95     BYTE_PORT( 0x098, IDEDEV, PORT_RW, 0, "IDE Device" )
    96     BYTE_PORT( 0x09C, IDECMD, PORT_RW, 0, "IDE Command/Status" )
    97     LONG_PORT( 0x404, EXTDMASH4, PORT_MRW, 0, "Ext DMA SH4 address" )
    98     LONG_PORT( 0x408, EXTDMASIZ, PORT_MRW, 0, "Ext DMA Size" )
    99     LONG_PORT( 0x40C, EXTDMADIR, PORT_MRW, 0, "Ext DMA Direction" )
   100     LONG_PORT( 0x414, EXTDMACTL1, PORT_MRW, 0, "Ext DMA Control 1" )
   101     LONG_PORT( 0x418, EXTDMACTL2, PORT_MRW, 0, "Ext DMA Control 2" )
   102     WORD_PORT( 0x480, EXTDMAUNK0, PORT_MRW, 0, "Ext DMA <unknown0>" )
   103     LONG_PORT( 0x484, EXTDMAUNK1, PORT_MRW, 0, "Ext DMA <unknown1>" )
   104     LONG_PORT( 0x488, EXTDMAUNK2, PORT_MRW, 0, "Ext DMA <unknown2>" )
   105     LONG_PORT( 0x48C, EXTDMAUNK3, PORT_MRW, 0, "Ext DMA <unknown3>" )
   106     LONG_PORT( 0x490, EXTDMAUNK4, PORT_MRW, 0, "Ext DMA <unknown4>" )
   107     LONG_PORT( 0x494, EXTDMAUNK5, PORT_MRW, 0, "Ext DMA <unknown5>" )
   108     LONG_PORT( 0x4A0, EXTDMAUNK6, PORT_MRW, 0, "Ext DMA <unknown6>" )
   109     LONG_PORT( 0x4A4, EXTDMAUNK7, PORT_MRW, 0, "Ext DMA <unknown7>" )
   110     LONG_PORT( 0x4B4, EXTDMAUNK8, PORT_MRW, 0, "Ext DMA <unknown8>" )
   111     LONG_PORT( 0x4B8, EXTDMAUNK9, PORT_MRW, 0, "Ext DMA <unknown9>" )
   112     LONG_PORT( 0x4E4, IDEACTIVATE, PORT_MRW, 0, "IDE activate" )
   113     LONG_PORT( 0x800, SPUDMA0EXT, PORT_MRW, 0, "SPU DMA0 External address" )
   114     LONG_PORT( 0x804, SPUDMA0SH4, PORT_MRW, 0, "SPU DMA0 SH4-based address" )
   115     LONG_PORT( 0x808, SPUDMA0SIZ, PORT_MRW, 0, "SPU DMA0 Size" )
   116     LONG_PORT( 0x80C, SPUDMA0DIR, PORT_MRW, 0, "SPU DMA0 Direction" )
   117     LONG_PORT( 0x810, SPUDMA0MOD, PORT_MRW, 0, "SPU DMA0 Mode" )
   118     LONG_PORT( 0x814, SPUDMA0CTL1, PORT_MRW, 0, "SPU DMA0 Control 1" )
   119     LONG_PORT( 0x818, SPUDMA0CTL2, PORT_MRW, 0, "SPU DMA0 Control 2" )
   120     LONG_PORT( 0x81C, SPUDMA0UN1, PORT_MRW, 0, "SPU DMA0 <unknown1>" )
   121     LONG_PORT( 0x820, SPUDMA1EXT, PORT_MRW, 0, "SPU DMA1 External address" )
   122     LONG_PORT( 0x824, SPUDMA1SH4, PORT_MRW, 0, "SPU DMA1 SH4-based address" )
   123     LONG_PORT( 0x828, SPUDMA1SIZ, PORT_MRW, 0, "SPU DMA1 Size" )
   124     LONG_PORT( 0x82C, SPUDMA1DIR, PORT_MRW, 0, "SPU DMA1 Direction" )
   125     LONG_PORT( 0x830, SPUDMA1MOD, PORT_MRW, 0, "SPU DMA1 Mode" )
   126     LONG_PORT( 0x834, SPUDMA1CTL1, PORT_MRW, 0, "SPU DMA1 Control 1" )
   127     LONG_PORT( 0x838, SPUDMA1CTL2, PORT_MRW, 0, "SPU DMA1 Control 2" )
   128     LONG_PORT( 0x83C, SPUDMA1UN1, PORT_MRW, 0, "SPU DMA1 <unknown1>" )
   129     LONG_PORT( 0x840, SPUDMA2EXT, PORT_MRW, 0, "SPU DMA2 External address" )
   130     LONG_PORT( 0x844, SPUDMA2SH4, PORT_MRW, 0, "SPU DMA2 SH4-based address" )
   131     LONG_PORT( 0x848, SPUDMA2SIZ, PORT_MRW, 0, "SPU DMA2 Size" )
   132     LONG_PORT( 0x84C, SPUDMA2DIR, PORT_MRW, 0, "SPU DMA2 Direction" )
   133     LONG_PORT( 0x850, SPUDMA2MOD, PORT_MRW, 0, "SPU DMA2 Mode" )
   134     LONG_PORT( 0x854, SPUDMA2CTL1, PORT_MRW, 0, "SPU DMA2 Control 1" )
   135     LONG_PORT( 0x858, SPUDMA2CTL2, PORT_MRW, 0, "SPU DMA2 Control 2" )
   136     LONG_PORT( 0x85C, SPUDMA2UN1, PORT_MRW, 0, "SPU DMA2 <unknown1>" )
   137     LONG_PORT( 0x860, SPUDMA3EXT, PORT_MRW, 0, "SPU DMA3 External address" )
   138     LONG_PORT( 0x864, SPUDMA3SH4, PORT_MRW, 0, "SPU DMA3 SH4-based address" )
   139     LONG_PORT( 0x868, SPUDMA3SIZ, PORT_MRW, 0, "SPU DMA3 Size" )
   140     LONG_PORT( 0x86C, SPUDMA3DIR, PORT_MRW, 0, "SPU DMA3 Direction" )
   141     LONG_PORT( 0x870, SPUDMA3MOD, PORT_MRW, 0, "SPU DMA3 Mode" )
   142     LONG_PORT( 0x874, SPUDMA3CTL1, PORT_MRW, 0, "SPU DMA3 Control 1" )
   143     LONG_PORT( 0x878, SPUDMA3CTL2, PORT_MRW, 0, "SPU DMA3 Control 2" )
   144     LONG_PORT( 0x87C, SPUDMA3UN1, PORT_MRW, 0, "SPU DMA3 <unknown1>" )
   145     LONG_PORT( 0x890, SPUDMAWAIT, PORT_MRW, 0, "SPU DMA wait states (?)" )
   146     LONG_PORT( 0x894, SPUDMAUN1, PORT_MRW, 0, "SPU DMA <unknown1>" )
   147     LONG_PORT( 0x898, SPUDMAUN2, PORT_MRW, 0, "SPU DMA <unknown2>" )
   148     LONG_PORT( 0x89C, SPUDMAUN3, PORT_MRW, 0, "SPU DMA <unknown3>" )
   149     LONG_PORT( 0x8A0, SPUDMAUN4, PORT_MRW, 0, "SPU DMA <unknown4>" )
   150     LONG_PORT( 0x8A4, SPUDMAUN5, PORT_MRW, 0, "SPU DMA <unknown5>" )
   151     LONG_PORT( 0x8A8, SPUDMAUN6, PORT_MRW, 0, "SPU DMA <unknown6>" )
   152     LONG_PORT( 0x8AC, SPUDMAUN7, PORT_MRW, 0, "SPU DMA <unknown7>" )
   153     LONG_PORT( 0x8B0, SPUDMAUN8, PORT_MRW, 0, "SPU DMA <unknown8>" )
   154     LONG_PORT( 0x8B4, SPUDMAUN9, PORT_MRW, 0, "SPU DMA <unknown9>" )
   155     LONG_PORT( 0x8B8, SPUDMAUN10, PORT_MRW, 0, "SPU DMA <unknown10>" )
   156     LONG_PORT( 0x8BC, SPUDMAUN11, PORT_MRW, 0, "SPU DMA <unknown11>" )
   157     LONG_PORT( 0xC00, PVRDMA2EXT, PORT_MRW, 0, "PVR DMA External address" )
   158     LONG_PORT( 0xC04, PVRDMA2SH4, PORT_MRW, 0, "PVR DMA SH4 address" )
   159     LONG_PORT( 0xC08, PVRDMA2SIZ, PORT_MRW, 0, "PVR DMA Size" )
   160     LONG_PORT( 0xC0C, PVRDMA2DIR, PORT_MRW, 0, "PVR DMA Direction" )
   161     LONG_PORT( 0xC10, PVRDMA2MOD, PORT_MRW, 0, "PVR DMA Mode" )
   162     LONG_PORT( 0xC14, PVRDMA2CTL1, PORT_MRW, 0, "PVR DMA Control 1" )
   163     LONG_PORT( 0xC18, PVRDMA2CTL2, PORT_MRW, 0, "PVR DMA Control 2" )
   164     LONG_PORT( 0xC80, PVRDMA2UN1, PORT_MRW, 0, "PVR DMA <unknown1>" )
   166 MMIO_REGION_END
   168 #define EVENT_PVR_RENDER_DONE 2
   169 #define EVENT_SCANLINE1 3
   170 #define EVENT_SCANLINE2 4
   171 #define EVENT_RETRACE   5
   172 #define EVENT_PVR_UNK 6
   173 #define EVENT_PVR_OPAQUE_DONE 7
   174 #define EVENT_PVR_OPAQUEMOD_DONE 8
   175 #define EVENT_PVR_TRANS_DONE 9
   176 #define EVENT_PVR_TRANSMOD_DONE 10
   177 #define EVENT_MAPLE_DMA 12
   178 #define EVENT_MAPLE_ERR 13 /* ??? */
   179 #define EVENT_GDROM_DMA 14
   180 #define EVENT_SPU_DMA0  15
   181 #define EVENT_SPU_DMA1  16
   182 #define EVENT_SPU_DMA2  17
   183 #define EVENT_SPU_DMA3  18
   184 #define EVENT_PVR_DMA   19
   185 #define EVENT_PVR_PUNCHOUT_DONE 21
   187 #define EVENT_GDROM_CMD 32
   188 #define EVENT_AICA      33
   190 void asic_event( int event );
   191 void asic_init( void );
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