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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 65:9f124c245fc6
prev56:3224dceaf2a3
next85:71e239d20c5d
author nkeynes
date Tue Jan 03 12:21:45 2006 +0000 (15 years ago)
permissions -rw-r--r--
last change Implement blanking (maybe, untested)
Quick hack to generate appropriate events on ta list completion
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     1 /**
     2  * $Id: pvr2.c,v 1.12 2006-01-03 12:21:45 nkeynes Exp $
     3  *
     4  * PVR2 (Video) MMIO and supporting functions.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "video.h"
    22 #include "mem.h"
    23 #include "asic.h"
    24 #include "pvr2.h"
    25 #include "sh4/sh4core.h"
    26 #define MMIO_IMPL
    27 #include "pvr2.h"
    29 char *video_base;
    31 void pvr2_init( void );
    32 uint32_t pvr2_run_slice( uint32_t );
    33 void pvr2_next_frame( void );
    35 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, 
    36 					pvr2_run_slice, NULL,
    37 					NULL, NULL };
    39 void pvr2_init( void )
    40 {
    41     register_io_region( &mmio_region_PVR2 );
    42     register_io_region( &mmio_region_PVR2TA );
    43     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    44 }
    46 uint32_t pvr2_time_counter = 0;
    47 uint32_t pvr2_time_per_frame = 20000000;
    49 uint32_t pvr2_run_slice( uint32_t nanosecs ) 
    50 {
    51     pvr2_time_counter += nanosecs;
    52     while( pvr2_time_counter >= pvr2_time_per_frame ) {
    53 	pvr2_next_frame();
    54 	pvr2_time_counter -= pvr2_time_per_frame;
    55     }
    56     return nanosecs;
    57 }
    59 uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
    60 int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
    61 char *frame_start; /* current video start address (in real memory) */
    63 /*
    64  * Display the next frame, copying the current contents of video ram to
    65  * the window. If the video configuration has changed, first recompute the
    66  * new frame size/depth.
    67  */
    68 void pvr2_next_frame( void )
    69 {
    70     if( bChanged ) {
    71         int dispsize = MMIO_READ( PVR2, DISPSIZE );
    72         int dispmode = MMIO_READ( PVR2, DISPMODE );
    73         int vidcfg = MMIO_READ( PVR2, VIDCFG );
    74         vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
    75         vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
    76         vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
    77         vid_col = (dispmode & DISPMODE_COL);
    78         frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
    79         interlaced = (vidcfg & VIDCFG_I ? 1 : 0);
    80         bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & VIDCFG_VO ) ? 1 : 0;
    81         vid_size = (vid_ppl * vid_lpf) << (interlaced ? 3 : 2);
    82         vid_hres = vid_ppl;
    83         vid_vres = vid_lpf;
    84         if( interlaced ) vid_vres <<= 1;
    85         switch( vid_col ) {
    86             case MODE_RGB15:
    87             case MODE_RGB16: vid_hres <<= 1; break;
    88             case MODE_RGB24: vid_hres *= 3; break;
    89             case MODE_RGB32: vid_hres <<= 2; break;
    90         }
    91         vid_hres >>= 2;
    92         video_update_size( vid_hres, vid_vres, vid_col );
    93         bChanged = 0;
    94     }
    95     if( bEnabled ) {
    96 	if( MMIO_READ( PVR2, VIDCFG2 ) & 0x08 ) {
    97 	    /* Blanked */
    98 	    uint32_t colour = MMIO_READ( PVR2, BORDERCOL );
    99 	    video_fill( colour );
   100 	} else {
   101 	    /* Assume bit depths match for now... */
   102 	    memcpy( video_data, frame_start, vid_size );
   103 	}
   104     } else {
   105         memset( video_data, 0, vid_size );
   106     }
   107     video_update_frame();
   108     asic_event( EVENT_SCANLINE1 );
   109     asic_event( EVENT_SCANLINE2 );
   110     asic_event( EVENT_RETRACE );
   111 }
   113 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   114 {
   115     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   116         MMIO_WRITE( PVR2, reg, val );
   117         /* I don't want to hear about these */
   118         return;
   119     }
   121     INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
   122           MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
   124     switch(reg) {
   125     case DISPSIZE: bChanged = 1;
   126     case DISPMODE: bChanged = 1;
   127     case DISPADDR1: bChanged = 1;
   128     case DISPADDR2: bChanged = 1;
   129     case VIDCFG: bChanged = 1;
   130 	break;
   131     case RENDSTART:
   132 	if( val == 0xFFFFFFFF )
   133 	    pvr2_render_scene();
   134 	break;
   135     }
   136     MMIO_WRITE( PVR2, reg, val );
   137 }
   139 MMIO_REGION_READ_FN( PVR2, reg )
   140 {
   141     switch( reg ) {
   142         case BEAMPOS:
   143             return sh4r.icount&0x20 ? 0x2000 : 1;
   144         default:
   145             return MMIO_READ( PVR2, reg );
   146     }
   147 }
   149 void pvr2_set_base_address( uint32_t base ) 
   150 {
   151     mmio_region_PVR2_write( DISPADDR1, base );
   152 }
   155 void pvr2_render_scene( void )
   156 {
   157     /* Actual rendering goes here :) */
   158     asic_event( EVENT_PVR_RENDER_DONE );
   159     DEBUG( "Rendered frame %d", video_frame_count );
   160 }
   162 /** Tile Accelerator */
   164 struct tacmd {
   165     uint32_t command;
   166     uint32_t param1;
   167     uint32_t param2;
   168     uint32_t texture;
   169     float alpha;
   170     float red;
   171     float green;
   172     float blue;
   173 };
   175 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   176 {
   177     return 0xFFFFFFFF;
   178 }
   180 char pvr2ta_remainder[8];
   182 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   183 {
   184     DEBUG( "Direct write to TA %08X", val );
   185 }
   187 void pvr2ta_write( char *buf, uint32_t length )
   188 {
   189     int i;
   190     struct tacmd *cmd_list = (struct tacmd *)buf;
   191     int count = length >> 5;
   192     unsigned int lasttype = 0;
   193     for( i=0; i<count; i++ ){
   194 	unsigned int type = (cmd_list[i].command >> 24) & 0xFF;
   195 	DEBUG( "PVR2 cmd: %08X %08X %08X", cmd_list[i].command, cmd_list[i].param1, cmd_list[i].param2 );
   196 	if( type == 0 ) {
   197 	    /* End of list */
   198 	    switch( lasttype ) {
   199 	    case 0x80: /* Opaque polys */
   200 		asic_event( EVENT_PVR_OPAQUE_DONE );
   201 		break;
   202 	    case 0x81: /* Opaque poly modifier */
   203 		asic_event( EVENT_PVR_OPAQUEMOD_DONE );
   204 		break;
   205 	    case 0x82: /* Transparent polys */
   206 		asic_event( EVENT_PVR_TRANS_DONE );
   207 		break;
   208 	    case 0x83: /* Transparent poly modifier */
   209 		asic_event( EVENT_PVR_TRANSMOD_DONE );
   210 		break;
   211 	    case 0x84: /* Punchthrough */
   212 		asic_event( EVENT_PVR_PUNCHOUT_DONE );
   213 		break;
   214 	    }
   215 	} else {
   216 	    lasttype = type;
   217 	}
   218     }
   219 }
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