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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 619:0800a0137472
prev617:476a717a54f3
next638:d6dc39e935af
author nkeynes
date Fri Feb 08 00:06:56 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix LDS/STS to FPUL/FPSCR to check the FPU disabled bit. Fixes
the linux 2.4.0-test8 kernel boot
(this wasn't exactly very well documented in the original manual)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include <assert.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "sh4/sh4core.h"
    26 #include "sh4/sh4mmio.h"
    27 #include "sh4/intc.h"
    28 #include "sh4/xltcache.h"
    29 #include "sh4/sh4stat.h"
    30 #include "sh4/sh4trans.h"
    31 #include "mem.h"
    32 #include "clock.h"
    33 #include "syscall.h"
    35 void sh4_init( void );
    36 void sh4_xlat_init( void );
    37 void sh4_reset( void );
    38 void sh4_start( void );
    39 void sh4_stop( void );
    40 void sh4_save_state( FILE *f );
    41 int sh4_load_state( FILE *f );
    43 uint32_t sh4_run_slice( uint32_t );
    44 uint32_t sh4_xlat_run_slice( uint32_t );
    46 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    47 				       sh4_start, sh4_run_slice, sh4_stop,
    48 				       sh4_save_state, sh4_load_state };
    50 struct sh4_registers sh4r;
    51 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    52 int sh4_breakpoint_count = 0;
    53 sh4ptr_t sh4_main_ram;
    54 gboolean sh4_starting = FALSE;
    55 static gboolean sh4_use_translator = FALSE;
    56 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
    58 void sh4_set_use_xlat( gboolean use )
    59 {
    60 // No-op if the translator was not built
    61 #ifdef SH4_TRANSLATOR
    62     if( use ) {
    63 	xlat_cache_init();
    64 	sh4_x86_init();
    65 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    66     } else {
    67 	sh4_module.run_time_slice = sh4_run_slice;
    68     }
    69     sh4_use_translator = use;
    70 #endif
    71 }
    73 gboolean sh4_is_using_xlat()
    74 {
    75     return sh4_use_translator;
    76 }
    78 void sh4_init(void)
    79 {
    80     register_io_regions( mmio_list_sh4mmio );
    81     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    82     MMU_init();
    83     TMU_init();
    84     sh4_reset();
    85 }
    87 void sh4_start(void)
    88 {
    89     sh4_starting = TRUE;
    90 }
    92 void sh4_reset(void)
    93 {
    94     if(	sh4_use_translator ) {
    95 	xlat_flush_cache();
    96     }
    98     /* zero everything out, for the sake of having a consistent state. */
    99     memset( &sh4r, 0, sizeof(sh4r) );
   101     /* Resume running if we were halted */
   102     sh4r.sh4_state = SH4_STATE_RUNNING;
   104     sh4r.pc    = 0xA0000000;
   105     sh4r.new_pc= 0xA0000002;
   106     sh4r.vbr   = 0x00000000;
   107     sh4r.fpscr = 0x00040001;
   108     sh4r.sr    = 0x700000F0;
   109     sh4r.fr_bank = &sh4r.fr[0][0];
   111     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   112     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   114     /* Peripheral modules */
   115     CPG_reset();
   116     INTC_reset();
   117     MMU_reset();
   118     TMU_reset();
   119     SCIF_reset();
   120     sh4_stats_reset();
   121 }
   123 void sh4_stop(void)
   124 {
   125     if(	sh4_use_translator ) {
   126 	/* If we were running with the translator, update new_pc and in_delay_slot */
   127 	sh4r.new_pc = sh4r.pc+2;
   128 	sh4r.in_delay_slot = FALSE;
   129     }
   131 }
   133 void sh4_save_state( FILE *f )
   134 {
   135     if(	sh4_use_translator ) {
   136 	/* If we were running with the translator, update new_pc and in_delay_slot */
   137 	sh4r.new_pc = sh4r.pc+2;
   138 	sh4r.in_delay_slot = FALSE;
   139     }
   141     fwrite( &sh4r, sizeof(sh4r), 1, f );
   142     MMU_save_state( f );
   143     INTC_save_state( f );
   144     TMU_save_state( f );
   145     SCIF_save_state( f );
   146 }
   148 int sh4_load_state( FILE * f )
   149 {
   150     if(	sh4_use_translator ) {
   151 	xlat_flush_cache();
   152     }
   153     fread( &sh4r, sizeof(sh4r), 1, f );
   154     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   155     MMU_load_state( f );
   156     INTC_load_state( f );
   157     TMU_load_state( f );
   158     return SCIF_load_state( f );
   159 }
   162 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   163 {
   164     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   165     sh4_breakpoints[sh4_breakpoint_count].type = type;
   166     if( sh4_use_translator ) {
   167 	xlat_invalidate_word( pc );
   168     }
   169     sh4_breakpoint_count++;
   170 }
   172 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   173 {
   174     int i;
   176     for( i=0; i<sh4_breakpoint_count; i++ ) {
   177 	if( sh4_breakpoints[i].address == pc && 
   178 	    sh4_breakpoints[i].type == type ) {
   179 	    while( ++i < sh4_breakpoint_count ) {
   180 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   181 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   182 	    }
   183 	    if( sh4_use_translator ) {
   184 		xlat_invalidate_word( pc );
   185 	    }
   186 	    sh4_breakpoint_count--;
   187 	    return TRUE;
   188 	}
   189     }
   190     return FALSE;
   191 }
   193 int sh4_get_breakpoint( uint32_t pc )
   194 {
   195     int i;
   196     for( i=0; i<sh4_breakpoint_count; i++ ) {
   197 	if( sh4_breakpoints[i].address == pc )
   198 	    return sh4_breakpoints[i].type;
   199     }
   200     return 0;
   201 }
   203 void sh4_set_pc( int pc )
   204 {
   205     sh4r.pc = pc;
   206     sh4r.new_pc = pc+2;
   207 }
   210 /******************************* Support methods ***************************/
   212 static void sh4_switch_banks( )
   213 {
   214     uint32_t tmp[8];
   216     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   217     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   218     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   219 }
   221 void sh4_write_sr( uint32_t newval )
   222 {
   223     int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
   224     int newbank = (newval&SR_MDRB) == SR_MDRB;
   225     if( oldbank != newbank )
   226         sh4_switch_banks();
   227     sh4r.sr = newval;
   228     sh4r.t = (newval&SR_T) ? 1 : 0;
   229     sh4r.s = (newval&SR_S) ? 1 : 0;
   230     sh4r.m = (newval&SR_M) ? 1 : 0;
   231     sh4r.q = (newval&SR_Q) ? 1 : 0;
   232     intc_mask_changed();
   233 }
   235 uint32_t sh4_read_sr( void )
   236 {
   237     /* synchronize sh4r.sr with the various bitflags */
   238     sh4r.sr &= SR_MQSTMASK;
   239     if( sh4r.t ) sh4r.sr |= SR_T;
   240     if( sh4r.s ) sh4r.sr |= SR_S;
   241     if( sh4r.m ) sh4r.sr |= SR_M;
   242     if( sh4r.q ) sh4r.sr |= SR_Q;
   243     return sh4r.sr;
   244 }
   248 #define RAISE( x, v ) do{			\
   249     if( sh4r.vbr == 0 ) { \
   250         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   251         dreamcast_stop(); return FALSE;	\
   252     } else { \
   253         sh4r.spc = sh4r.pc;	\
   254         sh4r.ssr = sh4_read_sr(); \
   255         sh4r.sgr = sh4r.r[15]; \
   256         MMIO_WRITE(MMU,EXPEVT,x); \
   257         sh4r.pc = sh4r.vbr + v; \
   258         sh4r.new_pc = sh4r.pc + 2; \
   259         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   260 	if( sh4r.in_delay_slot ) { \
   261 	    sh4r.in_delay_slot = 0; \
   262 	    sh4r.spc -= 2; \
   263 	} \
   264     } \
   265     return TRUE; } while(0)
   267 /**
   268  * Raise a general CPU exception for the specified exception code.
   269  * (NOT for TRAPA or TLB exceptions)
   270  */
   271 gboolean sh4_raise_exception( int code )
   272 {
   273     RAISE( code, EXV_EXCEPTION );
   274 }
   276 /**
   277  * Raise a CPU reset exception with the specified exception code.
   278  */
   279 gboolean sh4_raise_reset( int code )
   280 {
   281     // FIXME: reset modules as per "manual reset"
   282     sh4_reset();
   283     MMIO_WRITE(MMU,EXPEVT,code);
   284     sh4r.vbr = 0;
   285     sh4r.pc = 0xA0000000;
   286     sh4r.new_pc = sh4r.pc + 2;
   287     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   288 		  &(~SR_FD) );
   289 }
   291 gboolean sh4_raise_trap( int trap )
   292 {
   293     MMIO_WRITE( MMU, TRA, trap<<2 );
   294     RAISE( EXC_TRAP, EXV_EXCEPTION );
   295 }
   297 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   298     if( sh4r.in_delay_slot ) {
   299 	return sh4_raise_exception(slot_code);
   300     } else {
   301 	return sh4_raise_exception(normal_code);
   302     }
   303 }
   305 gboolean sh4_raise_tlb_exception( int code )
   306 {
   307     RAISE( code, EXV_TLBMISS );
   308 }
   310 void sh4_accept_interrupt( void )
   311 {
   312     uint32_t code = intc_accept_interrupt();
   313     sh4r.ssr = sh4_read_sr();
   314     sh4r.spc = sh4r.pc;
   315     sh4r.sgr = sh4r.r[15];
   316     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   317     MMIO_WRITE( MMU, INTEVT, code );
   318     sh4r.pc = sh4r.vbr + 0x600;
   319     sh4r.new_pc = sh4r.pc + 2;
   320     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   321 }
   323 void signsat48( void )
   324 {
   325     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   326 	sh4r.mac = 0xFFFF800000000000LL;
   327     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   328 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   329 }
   331 void sh4_fsca( uint32_t anglei, float *fr )
   332 {
   333     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   334     *fr++ = cosf(angle);
   335     *fr = sinf(angle);
   336 }
   338 /**
   339  * Enter sleep mode (eg by executing a SLEEP instruction).
   340  * Sets sh4_state appropriately and ensures any stopping peripheral modules
   341  * are up to date.
   342  */
   343 void sh4_sleep(void)
   344 {
   345     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   346 	sh4r.sh4_state = SH4_STATE_STANDBY;
   347 	/* Bring all running peripheral modules up to date, and then halt them. */
   348 	TMU_run_slice( sh4r.slice_cycle );
   349 	SCIF_run_slice( sh4r.slice_cycle );
   350     } else {
   351 	if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
   352 	    sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
   353 	    /* Halt DMAC but other peripherals still running */
   355 	} else {
   356 	    sh4r.sh4_state = SH4_STATE_SLEEP;
   357 	}
   358     }
   359     if( sh4_xlat_is_running() ) {
   360 	sh4_translate_exit( XLAT_EXIT_SLEEP );
   361     }
   362 }
   364 /**
   365  * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
   366  * and restarts any peripheral devices that were stopped.
   367  */
   368 void sh4_wakeup(void)
   369 {
   370     switch( sh4r.sh4_state ) {
   371     case SH4_STATE_STANDBY:
   372 	break;
   373     case SH4_STATE_DEEP_SLEEP:
   374 	break;
   375     case SH4_STATE_SLEEP:
   376 	break;
   377     }
   378     sh4r.sh4_state = SH4_STATE_RUNNING;
   379 }
   381 /**
   382  * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
   383  * Returns when either the SH4 wakes up (interrupt received) or the end of
   384  * the slice is reached. Updates sh4.slice_cycle with the exit time and
   385  * returns the same value.
   386  */
   387 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
   388 {
   389     int sleep_state = sh4r.sh4_state;
   390     assert( sleep_state != SH4_STATE_RUNNING );
   391     while( sh4r.event_pending < nanosecs ) {
   392 	sh4r.slice_cycle = sh4r.event_pending;
   393 	if( sh4r.event_types & PENDING_EVENT ) {
   394 	    event_execute();
   395 	}
   396 	if( sh4r.event_types & PENDING_IRQ ) {
   397 	    sh4_wakeup();
   398 	    nanosecs = sh4r.event_pending;
   399 	    break;
   400 	}
   401     }
   402     sh4r.slice_cycle = nanosecs;
   403     return sh4r.slice_cycle;
   404 }
   407 /**
   408  * Compute the matrix tranform of fv given the matrix xf.
   409  * Both fv and xf are word-swapped as per the sh4r.fr banks
   410  */
   411 void sh4_ftrv( float *target, float *xf )
   412 {
   413     float fv[4] = { target[1], target[0], target[3], target[2] };
   414     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   415 	xf[9]*fv[2] + xf[13]*fv[3];
   416     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   417 	xf[8]*fv[2] + xf[12]*fv[3];
   418     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   419 	xf[11]*fv[2] + xf[15]*fv[3];
   420     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   421 	xf[10]*fv[2] + xf[14]*fv[3];
   422 }
   424 gboolean sh4_has_page( sh4vma_t vma )
   425 {
   426     sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
   427     return addr != MMU_VMA_ERROR && mem_has_page(addr);
   428 }
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