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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 626:a010e30a30e9
prev617:476a717a54f3
next641:afb9a42c61c6
author nkeynes
date Fri Feb 08 00:06:56 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix LDS/STS to FPUL/FPSCR to check the FPU disabled bit. Fixes
the linux 2.4.0-test8 kernel boot
(this wasn't exactly very well documented in the original manual)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <assert.h>
    22 #include <math.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "eventq.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/intc.h"
    33 #define SH4_CALLTRACE 1
    35 #define MAX_INT 0x7FFFFFFF
    36 #define MIN_INT 0x80000000
    37 #define MAX_INTF 2147483647.0
    38 #define MIN_INTF -2147483648.0
    40 /********************** SH4 Module Definition ****************************/
    42 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    43 {
    44     int i;
    45     sh4r.slice_cycle = 0;
    47     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
    48 	sh4_sleep_run_slice(nanosecs);
    49     }
    51     if( sh4_breakpoint_count == 0 ) {
    52 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    53 	    if( SH4_EVENT_PENDING() ) {
    54 		if( sh4r.event_types & PENDING_EVENT ) {
    55 		    event_execute();
    56 		}
    57 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    58 		if( sh4r.event_types & PENDING_IRQ ) {
    59 		    sh4_accept_interrupt();
    60 		}
    61 	    }
    62 	    if( !sh4_execute_instruction() ) {
    63 		break;
    64 	    }
    65 	}
    66     } else {
    67 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    68 	    if( SH4_EVENT_PENDING() ) {
    69 		if( sh4r.event_types & PENDING_EVENT ) {
    70 		    event_execute();
    71 		}
    72 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    73 		if( sh4r.event_types & PENDING_IRQ ) {
    74 		    sh4_accept_interrupt();
    75 		}
    76 	    }
    78 	    if( !sh4_execute_instruction() )
    79 		break;
    80 #ifdef ENABLE_DEBUG_MODE
    81 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    82 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    83 		    break;
    84 		}
    85 	    }
    86 	    if( i != sh4_breakpoint_count ) {
    87 		dreamcast_stop();
    88 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
    89 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
    90 		break;
    91 	    }
    92 #endif	
    93 	}
    94     }
    96     /* If we aborted early, but the cpu is still technically running,
    97      * we're doing a hard abort - cut the timeslice back to what we
    98      * actually executed
    99      */
   100     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   101 	nanosecs = sh4r.slice_cycle;
   102     }
   103     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   104 	TMU_run_slice( nanosecs );
   105 	SCIF_run_slice( nanosecs );
   106     }
   107     return nanosecs;
   108 }
   110 /********************** SH4 emulation core  ****************************/
   112 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   113 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   115 #if(SH4_CALLTRACE == 1)
   116 #define MAX_CALLSTACK 32
   117 static struct call_stack {
   118     sh4addr_t call_addr;
   119     sh4addr_t target_addr;
   120     sh4addr_t stack_pointer;
   121 } call_stack[MAX_CALLSTACK];
   123 static int call_stack_depth = 0;
   124 int sh4_call_trace_on = 0;
   126 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   127 {
   128     if( call_stack_depth < MAX_CALLSTACK ) {
   129 	call_stack[call_stack_depth].call_addr = source;
   130 	call_stack[call_stack_depth].target_addr = dest;
   131 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   132     }
   133     call_stack_depth++;
   134 }
   136 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   137 {
   138     if( call_stack_depth > 0 ) {
   139 	call_stack_depth--;
   140     }
   141 }
   143 void fprint_stack_trace( FILE *f )
   144 {
   145     int i = call_stack_depth -1;
   146     if( i >= MAX_CALLSTACK )
   147 	i = MAX_CALLSTACK - 1;
   148     for( ; i >= 0; i-- ) {
   149 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   150 		 (call_stack_depth - i), call_stack[i].call_addr,
   151 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   152     }
   153 }
   155 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   156 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   157 #else
   158 #define TRACE_CALL( dest, rts ) 
   159 #define TRACE_RETURN( source, dest )
   160 #endif
   162 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
   163 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
   164 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
   165 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
   166 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
   167 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
   169 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   171 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   172 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   174 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   175 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   176 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   177 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   178 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   180 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   181 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   182 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   184 static void sh4_write_float( uint32_t addr, int reg )
   185 {
   186     if( IS_FPU_DOUBLESIZE() ) {
   187 	if( reg & 1 ) {
   188 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   189 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   190 	} else {
   191 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   192 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   193 	}
   194     } else {
   195 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   196     }
   197 }
   199 static void sh4_read_float( uint32_t addr, int reg )
   200 {
   201     if( IS_FPU_DOUBLESIZE() ) {
   202 	if( reg & 1 ) {
   203 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   204 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   205 	} else {
   206 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   207 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   208 	}
   209     } else {
   210 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   211     }
   212 }
   214 gboolean sh4_execute_instruction( void )
   215 {
   216     uint32_t pc;
   217     unsigned short ir;
   218     uint32_t tmp;
   219     float ftmp;
   220     double dtmp;
   221     int64_t memtmp; // temporary holder for memory reads
   223 #define R0 sh4r.r[0]
   224     pc = sh4r.pc;
   225     if( pc > 0xFFFFFF00 ) {
   226 	/* SYSCALL Magic */
   227 	syscall_invoke( pc );
   228 	sh4r.in_delay_slot = 0;
   229 	pc = sh4r.pc = sh4r.pr;
   230 	sh4r.new_pc = sh4r.pc + 2;
   231     }
   232     CHECKRALIGN16(pc);
   234     /* Read instruction */
   235     if( !IS_IN_ICACHE(pc) ) {
   236 	if( !mmu_update_icache(pc) ) {
   237 	    // Fault - look for the fault handler
   238 	    if( !mmu_update_icache(sh4r.pc) ) {
   239 		// double fault - halt
   240 		ERROR( "Double fault - halting" );
   241 		dreamcast_stop();
   242 		return FALSE;
   243 	    }
   244 	}
   245 	pc = sh4r.pc;
   246     }
   247     assert( IS_IN_ICACHE(pc) );
   248     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   249         switch( (ir&0xF000) >> 12 ) {
   250             case 0x0:
   251                 switch( ir&0xF ) {
   252                     case 0x2:
   253                         switch( (ir&0x80) >> 7 ) {
   254                             case 0x0:
   255                                 switch( (ir&0x70) >> 4 ) {
   256                                     case 0x0:
   257                                         { /* STC SR, Rn */
   258                                         uint32_t Rn = ((ir>>8)&0xF); 
   259                                         CHECKPRIV();
   260                                         sh4r.r[Rn] = sh4_read_sr();
   261                                         }
   262                                         break;
   263                                     case 0x1:
   264                                         { /* STC GBR, Rn */
   265                                         uint32_t Rn = ((ir>>8)&0xF); 
   266                                         CHECKPRIV();
   267                                         sh4r.r[Rn] = sh4r.gbr;
   268                                         }
   269                                         break;
   270                                     case 0x2:
   271                                         { /* STC VBR, Rn */
   272                                         uint32_t Rn = ((ir>>8)&0xF); 
   273                                         CHECKPRIV();
   274                                         sh4r.r[Rn] = sh4r.vbr;
   275                                         }
   276                                         break;
   277                                     case 0x3:
   278                                         { /* STC SSR, Rn */
   279                                         uint32_t Rn = ((ir>>8)&0xF); 
   280                                         CHECKPRIV();
   281                                         sh4r.r[Rn] = sh4r.ssr;
   282                                         }
   283                                         break;
   284                                     case 0x4:
   285                                         { /* STC SPC, Rn */
   286                                         uint32_t Rn = ((ir>>8)&0xF); 
   287                                         CHECKPRIV();
   288                                         sh4r.r[Rn] = sh4r.spc;
   289                                         }
   290                                         break;
   291                                     default:
   292                                         UNDEF();
   293                                         break;
   294                                 }
   295                                 break;
   296                             case 0x1:
   297                                 { /* STC Rm_BANK, Rn */
   298                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   299                                 CHECKPRIV();
   300                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   301                                 }
   302                                 break;
   303                         }
   304                         break;
   305                     case 0x3:
   306                         switch( (ir&0xF0) >> 4 ) {
   307                             case 0x0:
   308                                 { /* BSRF Rn */
   309                                 uint32_t Rn = ((ir>>8)&0xF); 
   310                                 CHECKSLOTILLEGAL();
   311                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   312                                 sh4r.in_delay_slot = 1;
   313                                 sh4r.pr = sh4r.pc + 4;
   314                                 sh4r.pc = sh4r.new_pc;
   315                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   316                                 TRACE_CALL( pc, sh4r.new_pc );
   317                                 return TRUE;
   318                                 }
   319                                 break;
   320                             case 0x2:
   321                                 { /* BRAF Rn */
   322                                 uint32_t Rn = ((ir>>8)&0xF); 
   323                                 CHECKSLOTILLEGAL();
   324                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   325                                 sh4r.in_delay_slot = 1;
   326                                 sh4r.pc = sh4r.new_pc;
   327                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   328                                 return TRUE;
   329                                 }
   330                                 break;
   331                             case 0x8:
   332                                 { /* PREF @Rn */
   333                                 uint32_t Rn = ((ir>>8)&0xF); 
   334                                 tmp = sh4r.r[Rn];
   335                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {
   336                            	 sh4_flush_store_queue(tmp);
   337                                 }
   338                                 }
   339                                 break;
   340                             case 0x9:
   341                                 { /* OCBI @Rn */
   342                                 uint32_t Rn = ((ir>>8)&0xF); 
   343                                 }
   344                                 break;
   345                             case 0xA:
   346                                 { /* OCBP @Rn */
   347                                 uint32_t Rn = ((ir>>8)&0xF); 
   348                                 }
   349                                 break;
   350                             case 0xB:
   351                                 { /* OCBWB @Rn */
   352                                 uint32_t Rn = ((ir>>8)&0xF); 
   353                                 }
   354                                 break;
   355                             case 0xC:
   356                                 { /* MOVCA.L R0, @Rn */
   357                                 uint32_t Rn = ((ir>>8)&0xF); 
   358                                 tmp = sh4r.r[Rn];
   359                                 CHECKWALIGN32(tmp);
   360                                 MEM_WRITE_LONG( tmp, R0 );
   361                                 }
   362                                 break;
   363                             default:
   364                                 UNDEF();
   365                                 break;
   366                         }
   367                         break;
   368                     case 0x4:
   369                         { /* MOV.B Rm, @(R0, Rn) */
   370                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   371                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   372                         }
   373                         break;
   374                     case 0x5:
   375                         { /* MOV.W Rm, @(R0, Rn) */
   376                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   377                         CHECKWALIGN16( R0 + sh4r.r[Rn] );
   378                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   379                         }
   380                         break;
   381                     case 0x6:
   382                         { /* MOV.L Rm, @(R0, Rn) */
   383                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   384                         CHECKWALIGN32( R0 + sh4r.r[Rn] );
   385                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   386                         }
   387                         break;
   388                     case 0x7:
   389                         { /* MUL.L Rm, Rn */
   390                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   391                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   392                                                (sh4r.r[Rm] * sh4r.r[Rn]);
   393                         }
   394                         break;
   395                     case 0x8:
   396                         switch( (ir&0xFF0) >> 4 ) {
   397                             case 0x0:
   398                                 { /* CLRT */
   399                                 sh4r.t = 0;
   400                                 }
   401                                 break;
   402                             case 0x1:
   403                                 { /* SETT */
   404                                 sh4r.t = 1;
   405                                 }
   406                                 break;
   407                             case 0x2:
   408                                 { /* CLRMAC */
   409                                 sh4r.mac = 0;
   410                                 }
   411                                 break;
   412                             case 0x3:
   413                                 { /* LDTLB */
   414                                 MMU_ldtlb();
   415                                 }
   416                                 break;
   417                             case 0x4:
   418                                 { /* CLRS */
   419                                 sh4r.s = 0;
   420                                 }
   421                                 break;
   422                             case 0x5:
   423                                 { /* SETS */
   424                                 sh4r.s = 1;
   425                                 }
   426                                 break;
   427                             default:
   428                                 UNDEF();
   429                                 break;
   430                         }
   431                         break;
   432                     case 0x9:
   433                         switch( (ir&0xF0) >> 4 ) {
   434                             case 0x0:
   435                                 { /* NOP */
   436                                 /* NOP */
   437                                 }
   438                                 break;
   439                             case 0x1:
   440                                 { /* DIV0U */
   441                                 sh4r.m = sh4r.q = sh4r.t = 0;
   442                                 }
   443                                 break;
   444                             case 0x2:
   445                                 { /* MOVT Rn */
   446                                 uint32_t Rn = ((ir>>8)&0xF); 
   447                                 sh4r.r[Rn] = sh4r.t;
   448                                 }
   449                                 break;
   450                             default:
   451                                 UNDEF();
   452                                 break;
   453                         }
   454                         break;
   455                     case 0xA:
   456                         switch( (ir&0xF0) >> 4 ) {
   457                             case 0x0:
   458                                 { /* STS MACH, Rn */
   459                                 uint32_t Rn = ((ir>>8)&0xF); 
   460                                 sh4r.r[Rn] = (sh4r.mac>>32);
   461                                 }
   462                                 break;
   463                             case 0x1:
   464                                 { /* STS MACL, Rn */
   465                                 uint32_t Rn = ((ir>>8)&0xF); 
   466                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;
   467                                 }
   468                                 break;
   469                             case 0x2:
   470                                 { /* STS PR, Rn */
   471                                 uint32_t Rn = ((ir>>8)&0xF); 
   472                                 sh4r.r[Rn] = sh4r.pr;
   473                                 }
   474                                 break;
   475                             case 0x3:
   476                                 { /* STC SGR, Rn */
   477                                 uint32_t Rn = ((ir>>8)&0xF); 
   478                                 CHECKPRIV();
   479                                 sh4r.r[Rn] = sh4r.sgr;
   480                                 }
   481                                 break;
   482                             case 0x5:
   483                                 { /* STS FPUL, Rn */
   484                                 uint32_t Rn = ((ir>>8)&0xF); 
   485                                 CHECKFPUEN();
   486                                 sh4r.r[Rn] = sh4r.fpul;
   487                                 }
   488                                 break;
   489                             case 0x6:
   490                                 { /* STS FPSCR, Rn */
   491                                 uint32_t Rn = ((ir>>8)&0xF); 
   492                                 CHECKFPUEN();
   493                                 sh4r.r[Rn] = sh4r.fpscr;
   494                                 }
   495                                 break;
   496                             case 0xF:
   497                                 { /* STC DBR, Rn */
   498                                 uint32_t Rn = ((ir>>8)&0xF); 
   499                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
   500                                 }
   501                                 break;
   502                             default:
   503                                 UNDEF();
   504                                 break;
   505                         }
   506                         break;
   507                     case 0xB:
   508                         switch( (ir&0xFF0) >> 4 ) {
   509                             case 0x0:
   510                                 { /* RTS */
   511                                 CHECKSLOTILLEGAL();
   512                                 CHECKDEST( sh4r.pr );
   513                                 sh4r.in_delay_slot = 1;
   514                                 sh4r.pc = sh4r.new_pc;
   515                                 sh4r.new_pc = sh4r.pr;
   516                                 TRACE_RETURN( pc, sh4r.new_pc );
   517                                 return TRUE;
   518                                 }
   519                                 break;
   520                             case 0x1:
   521                                 { /* SLEEP */
   522                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   523                             	sh4r.sh4_state = SH4_STATE_STANDBY;
   524                                 } else {
   525                             	sh4r.sh4_state = SH4_STATE_SLEEP;
   526                                 }
   527                                 return FALSE; /* Halt CPU */
   528                                 }
   529                                 break;
   530                             case 0x2:
   531                                 { /* RTE */
   532                                 CHECKPRIV();
   533                                 CHECKDEST( sh4r.spc );
   534                                 CHECKSLOTILLEGAL();
   535                                 sh4r.in_delay_slot = 1;
   536                                 sh4r.pc = sh4r.new_pc;
   537                                 sh4r.new_pc = sh4r.spc;
   538                                 sh4_write_sr( sh4r.ssr );
   539                                 return TRUE;
   540                                 }
   541                                 break;
   542                             default:
   543                                 UNDEF();
   544                                 break;
   545                         }
   546                         break;
   547                     case 0xC:
   548                         { /* MOV.B @(R0, Rm), Rn */
   549                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   550                         MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   551                         }
   552                         break;
   553                     case 0xD:
   554                         { /* MOV.W @(R0, Rm), Rn */
   555                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   556                         CHECKRALIGN16( R0 + sh4r.r[Rm] );
   557                            MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   558                         }
   559                         break;
   560                     case 0xE:
   561                         { /* MOV.L @(R0, Rm), Rn */
   562                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   563                         CHECKRALIGN32( R0 + sh4r.r[Rm] );
   564                            MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   565                         }
   566                         break;
   567                     case 0xF:
   568                         { /* MAC.L @Rm+, @Rn+ */
   569                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   570                         int64_t tmpl;
   571                         if( Rm == Rn ) {
   572                     	CHECKRALIGN32( sh4r.r[Rn] );
   573                     	MEM_READ_LONG(sh4r.r[Rn], tmp);
   574                     	tmpl = SIGNEXT32(tmp);
   575                     	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
   576                     	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   577                     	sh4r.r[Rn] += 8;
   578                         } else {
   579                     	CHECKRALIGN32( sh4r.r[Rm] );
   580                     	CHECKRALIGN32( sh4r.r[Rn] );
   581                     	MEM_READ_LONG(sh4r.r[Rn], tmp);
   582                     	tmpl = SIGNEXT32(tmp);
   583                     	MEM_READ_LONG(sh4r.r[Rm], tmp);
   584                     	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   585                     	sh4r.r[Rn] += 4;
   586                     	sh4r.r[Rm] += 4;
   587                         }
   588                         if( sh4r.s ) {
   589                             /* 48-bit Saturation. Yuch */
   590                             if( tmpl < (int64_t)0xFFFF800000000000LL )
   591                                 tmpl = 0xFFFF800000000000LL;
   592                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   593                                 tmpl = 0x00007FFFFFFFFFFFLL;
   594                         }
   595                         sh4r.mac = tmpl;
   596                         }
   597                         break;
   598                     default:
   599                         UNDEF();
   600                         break;
   601                 }
   602                 break;
   603             case 0x1:
   604                 { /* MOV.L Rm, @(disp, Rn) */
   605                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   606                 tmp = sh4r.r[Rn] + disp;
   607                 CHECKWALIGN32( tmp );
   608                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   609                 }
   610                 break;
   611             case 0x2:
   612                 switch( ir&0xF ) {
   613                     case 0x0:
   614                         { /* MOV.B Rm, @Rn */
   615                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   616                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   617                         }
   618                         break;
   619                     case 0x1:
   620                         { /* MOV.W Rm, @Rn */
   621                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   622                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   623                         }
   624                         break;
   625                     case 0x2:
   626                         { /* MOV.L Rm, @Rn */
   627                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   628                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   629                         }
   630                         break;
   631                     case 0x4:
   632                         { /* MOV.B Rm, @-Rn */
   633                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   634                         MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--;
   635                         }
   636                         break;
   637                     case 0x5:
   638                         { /* MOV.W Rm, @-Rn */
   639                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   640                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2;
   641                         }
   642                         break;
   643                     case 0x6:
   644                         { /* MOV.L Rm, @-Rn */
   645                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   646                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4;
   647                         }
   648                         break;
   649                     case 0x7:
   650                         { /* DIV0S Rm, Rn */
   651                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   652                         sh4r.q = sh4r.r[Rn]>>31;
   653                         sh4r.m = sh4r.r[Rm]>>31;
   654                         sh4r.t = sh4r.q ^ sh4r.m;
   655                         }
   656                         break;
   657                     case 0x8:
   658                         { /* TST Rm, Rn */
   659                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   660                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
   661                         }
   662                         break;
   663                     case 0x9:
   664                         { /* AND Rm, Rn */
   665                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   666                         sh4r.r[Rn] &= sh4r.r[Rm];
   667                         }
   668                         break;
   669                     case 0xA:
   670                         { /* XOR Rm, Rn */
   671                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   672                         sh4r.r[Rn] ^= sh4r.r[Rm];
   673                         }
   674                         break;
   675                     case 0xB:
   676                         { /* OR Rm, Rn */
   677                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   678                         sh4r.r[Rn] |= sh4r.r[Rm];
   679                         }
   680                         break;
   681                     case 0xC:
   682                         { /* CMP/STR Rm, Rn */
   683                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   684                         /* set T = 1 if any byte in RM & RN is the same */
   685                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   686                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   687                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   688                         }
   689                         break;
   690                     case 0xD:
   691                         { /* XTRCT Rm, Rn */
   692                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   693                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
   694                         }
   695                         break;
   696                     case 0xE:
   697                         { /* MULU.W Rm, Rn */
   698                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   699                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   700                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   701                         }
   702                         break;
   703                     case 0xF:
   704                         { /* MULS.W Rm, Rn */
   705                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   706                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   707                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   708                         }
   709                         break;
   710                     default:
   711                         UNDEF();
   712                         break;
   713                 }
   714                 break;
   715             case 0x3:
   716                 switch( ir&0xF ) {
   717                     case 0x0:
   718                         { /* CMP/EQ Rm, Rn */
   719                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   720                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
   721                         }
   722                         break;
   723                     case 0x2:
   724                         { /* CMP/HS Rm, Rn */
   725                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   726                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
   727                         }
   728                         break;
   729                     case 0x3:
   730                         { /* CMP/GE Rm, Rn */
   731                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   732                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   733                         }
   734                         break;
   735                     case 0x4:
   736                         { /* DIV1 Rm, Rn */
   737                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   738                         /* This is derived from the sh4 manual with some simplifications */
   739                         uint32_t tmp0, tmp1, tmp2, dir;
   741                         dir = sh4r.q ^ sh4r.m;
   742                         sh4r.q = (sh4r.r[Rn] >> 31);
   743                         tmp2 = sh4r.r[Rm];
   744                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   745                         tmp0 = sh4r.r[Rn];
   746                         if( dir ) {
   747                              sh4r.r[Rn] += tmp2;
   748                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   749                         } else {
   750                              sh4r.r[Rn] -= tmp2;
   751                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   752                         }
   753                         sh4r.q ^= sh4r.m ^ tmp1;
   754                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   755                         }
   756                         break;
   757                     case 0x5:
   758                         { /* DMULU.L Rm, Rn */
   759                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   760                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
   761                         }
   762                         break;
   763                     case 0x6:
   764                         { /* CMP/HI Rm, Rn */
   765                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   766                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
   767                         }
   768                         break;
   769                     case 0x7:
   770                         { /* CMP/GT Rm, Rn */
   771                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   772                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   773                         }
   774                         break;
   775                     case 0x8:
   776                         { /* SUB Rm, Rn */
   777                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   778                         sh4r.r[Rn] -= sh4r.r[Rm];
   779                         }
   780                         break;
   781                     case 0xA:
   782                         { /* SUBC Rm, Rn */
   783                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   784                         tmp = sh4r.r[Rn];
   785                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   786                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   787                         }
   788                         break;
   789                     case 0xB:
   790                         UNIMP(ir); /* SUBV Rm, Rn */
   791                         break;
   792                     case 0xC:
   793                         { /* ADD Rm, Rn */
   794                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   795                         sh4r.r[Rn] += sh4r.r[Rm];
   796                         }
   797                         break;
   798                     case 0xD:
   799                         { /* DMULS.L Rm, Rn */
   800                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   801                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
   802                         }
   803                         break;
   804                     case 0xE:
   805                         { /* ADDC Rm, Rn */
   806                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   807                         tmp = sh4r.r[Rn];
   808                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   809                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   810                         }
   811                         break;
   812                     case 0xF:
   813                         { /* ADDV Rm, Rn */
   814                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   815                         tmp = sh4r.r[Rn] + sh4r.r[Rm];
   816                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   817                         sh4r.r[Rn] = tmp;
   818                         }
   819                         break;
   820                     default:
   821                         UNDEF();
   822                         break;
   823                 }
   824                 break;
   825             case 0x4:
   826                 switch( ir&0xF ) {
   827                     case 0x0:
   828                         switch( (ir&0xF0) >> 4 ) {
   829                             case 0x0:
   830                                 { /* SHLL Rn */
   831                                 uint32_t Rn = ((ir>>8)&0xF); 
   832                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
   833                                 }
   834                                 break;
   835                             case 0x1:
   836                                 { /* DT Rn */
   837                                 uint32_t Rn = ((ir>>8)&0xF); 
   838                                 sh4r.r[Rn] --;
   839                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   840                                 }
   841                                 break;
   842                             case 0x2:
   843                                 { /* SHAL Rn */
   844                                 uint32_t Rn = ((ir>>8)&0xF); 
   845                                 sh4r.t = sh4r.r[Rn] >> 31;
   846                                 sh4r.r[Rn] <<= 1;
   847                                 }
   848                                 break;
   849                             default:
   850                                 UNDEF();
   851                                 break;
   852                         }
   853                         break;
   854                     case 0x1:
   855                         switch( (ir&0xF0) >> 4 ) {
   856                             case 0x0:
   857                                 { /* SHLR Rn */
   858                                 uint32_t Rn = ((ir>>8)&0xF); 
   859                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
   860                                 }
   861                                 break;
   862                             case 0x1:
   863                                 { /* CMP/PZ Rn */
   864                                 uint32_t Rn = ((ir>>8)&0xF); 
   865                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
   866                                 }
   867                                 break;
   868                             case 0x2:
   869                                 { /* SHAR Rn */
   870                                 uint32_t Rn = ((ir>>8)&0xF); 
   871                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
   872                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   873                                 }
   874                                 break;
   875                             default:
   876                                 UNDEF();
   877                                 break;
   878                         }
   879                         break;
   880                     case 0x2:
   881                         switch( (ir&0xF0) >> 4 ) {
   882                             case 0x0:
   883                                 { /* STS.L MACH, @-Rn */
   884                                 uint32_t Rn = ((ir>>8)&0xF); 
   885                                 CHECKWALIGN32( sh4r.r[Rn] );
   886                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
   887                                 sh4r.r[Rn] -= 4;
   888                                 }
   889                                 break;
   890                             case 0x1:
   891                                 { /* STS.L MACL, @-Rn */
   892                                 uint32_t Rn = ((ir>>8)&0xF); 
   893                                 CHECKWALIGN32( sh4r.r[Rn] );
   894                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
   895                                 sh4r.r[Rn] -= 4;
   896                                 }
   897                                 break;
   898                             case 0x2:
   899                                 { /* STS.L PR, @-Rn */
   900                                 uint32_t Rn = ((ir>>8)&0xF); 
   901                                 CHECKWALIGN32( sh4r.r[Rn] );
   902                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
   903                                 sh4r.r[Rn] -= 4;
   904                                 }
   905                                 break;
   906                             case 0x3:
   907                                 { /* STC.L SGR, @-Rn */
   908                                 uint32_t Rn = ((ir>>8)&0xF); 
   909                                 CHECKPRIV();
   910                                 CHECKWALIGN32( sh4r.r[Rn] );
   911                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
   912                                 sh4r.r[Rn] -= 4;
   913                                 }
   914                                 break;
   915                             case 0x5:
   916                                 { /* STS.L FPUL, @-Rn */
   917                                 uint32_t Rn = ((ir>>8)&0xF); 
   918                                 CHECKFPUEN();
   919                                 CHECKWALIGN32( sh4r.r[Rn] );
   920                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
   921                                 sh4r.r[Rn] -= 4;
   922                                 }
   923                                 break;
   924                             case 0x6:
   925                                 { /* STS.L FPSCR, @-Rn */
   926                                 uint32_t Rn = ((ir>>8)&0xF); 
   927                                 CHECKFPUEN();
   928                                 CHECKWALIGN32( sh4r.r[Rn] );
   929                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
   930                                 sh4r.r[Rn] -= 4;
   931                                 }
   932                                 break;
   933                             case 0xF:
   934                                 { /* STC.L DBR, @-Rn */
   935                                 uint32_t Rn = ((ir>>8)&0xF); 
   936                                 CHECKPRIV();
   937                                 CHECKWALIGN32( sh4r.r[Rn] );
   938                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
   939                                 sh4r.r[Rn] -= 4;
   940                                 }
   941                                 break;
   942                             default:
   943                                 UNDEF();
   944                                 break;
   945                         }
   946                         break;
   947                     case 0x3:
   948                         switch( (ir&0x80) >> 7 ) {
   949                             case 0x0:
   950                                 switch( (ir&0x70) >> 4 ) {
   951                                     case 0x0:
   952                                         { /* STC.L SR, @-Rn */
   953                                         uint32_t Rn = ((ir>>8)&0xF); 
   954                                         CHECKPRIV();
   955                                         CHECKWALIGN32( sh4r.r[Rn] );
   956                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
   957                                         sh4r.r[Rn] -= 4;
   958                                         }
   959                                         break;
   960                                     case 0x1:
   961                                         { /* STC.L GBR, @-Rn */
   962                                         uint32_t Rn = ((ir>>8)&0xF); 
   963                                         CHECKWALIGN32( sh4r.r[Rn] );
   964                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
   965                                         sh4r.r[Rn] -= 4;
   966                                         }
   967                                         break;
   968                                     case 0x2:
   969                                         { /* STC.L VBR, @-Rn */
   970                                         uint32_t Rn = ((ir>>8)&0xF); 
   971                                         CHECKPRIV();
   972                                         CHECKWALIGN32( sh4r.r[Rn] );
   973                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
   974                                         sh4r.r[Rn] -= 4;
   975                                         }
   976                                         break;
   977                                     case 0x3:
   978                                         { /* STC.L SSR, @-Rn */
   979                                         uint32_t Rn = ((ir>>8)&0xF); 
   980                                         CHECKPRIV();
   981                                         CHECKWALIGN32( sh4r.r[Rn] );
   982                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
   983                                         sh4r.r[Rn] -= 4;
   984                                         }
   985                                         break;
   986                                     case 0x4:
   987                                         { /* STC.L SPC, @-Rn */
   988                                         uint32_t Rn = ((ir>>8)&0xF); 
   989                                         CHECKPRIV();
   990                                         CHECKWALIGN32( sh4r.r[Rn] );
   991                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
   992                                         sh4r.r[Rn] -= 4;
   993                                         }
   994                                         break;
   995                                     default:
   996                                         UNDEF();
   997                                         break;
   998                                 }
   999                                 break;
  1000                             case 0x1:
  1001                                 { /* STC.L Rm_BANK, @-Rn */
  1002                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1003                                 CHECKPRIV();
  1004                                 CHECKWALIGN32( sh4r.r[Rn] );
  1005                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
  1006                                 sh4r.r[Rn] -= 4;
  1008                                 break;
  1010                         break;
  1011                     case 0x4:
  1012                         switch( (ir&0xF0) >> 4 ) {
  1013                             case 0x0:
  1014                                 { /* ROTL Rn */
  1015                                 uint32_t Rn = ((ir>>8)&0xF); 
  1016                                 sh4r.t = sh4r.r[Rn] >> 31;
  1017                                 sh4r.r[Rn] <<= 1;
  1018                                 sh4r.r[Rn] |= sh4r.t;
  1020                                 break;
  1021                             case 0x2:
  1022                                 { /* ROTCL Rn */
  1023                                 uint32_t Rn = ((ir>>8)&0xF); 
  1024                                 tmp = sh4r.r[Rn] >> 31;
  1025                                 sh4r.r[Rn] <<= 1;
  1026                                 sh4r.r[Rn] |= sh4r.t;
  1027                                 sh4r.t = tmp;
  1029                                 break;
  1030                             default:
  1031                                 UNDEF();
  1032                                 break;
  1034                         break;
  1035                     case 0x5:
  1036                         switch( (ir&0xF0) >> 4 ) {
  1037                             case 0x0:
  1038                                 { /* ROTR Rn */
  1039                                 uint32_t Rn = ((ir>>8)&0xF); 
  1040                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1041                                 sh4r.r[Rn] >>= 1;
  1042                                 sh4r.r[Rn] |= (sh4r.t << 31);
  1044                                 break;
  1045                             case 0x1:
  1046                                 { /* CMP/PL Rn */
  1047                                 uint32_t Rn = ((ir>>8)&0xF); 
  1048                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
  1050                                 break;
  1051                             case 0x2:
  1052                                 { /* ROTCR Rn */
  1053                                 uint32_t Rn = ((ir>>8)&0xF); 
  1054                                 tmp = sh4r.r[Rn] & 0x00000001;
  1055                                 sh4r.r[Rn] >>= 1;
  1056                                 sh4r.r[Rn] |= (sh4r.t << 31 );
  1057                                 sh4r.t = tmp;
  1059                                 break;
  1060                             default:
  1061                                 UNDEF();
  1062                                 break;
  1064                         break;
  1065                     case 0x6:
  1066                         switch( (ir&0xF0) >> 4 ) {
  1067                             case 0x0:
  1068                                 { /* LDS.L @Rm+, MACH */
  1069                                 uint32_t Rm = ((ir>>8)&0xF); 
  1070                                 CHECKRALIGN32( sh4r.r[Rm] );
  1071                                 MEM_READ_LONG(sh4r.r[Rm], tmp);
  1072                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1073                             	(((uint64_t)tmp)<<32);
  1074                                 sh4r.r[Rm] += 4;
  1076                                 break;
  1077                             case 0x1:
  1078                                 { /* LDS.L @Rm+, MACL */
  1079                                 uint32_t Rm = ((ir>>8)&0xF); 
  1080                                 CHECKRALIGN32( sh4r.r[Rm] );
  1081                                 MEM_READ_LONG(sh4r.r[Rm], tmp);
  1082                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1083                                            (uint64_t)((uint32_t)tmp);
  1084                                 sh4r.r[Rm] += 4;
  1086                                 break;
  1087                             case 0x2:
  1088                                 { /* LDS.L @Rm+, PR */
  1089                                 uint32_t Rm = ((ir>>8)&0xF); 
  1090                                 CHECKRALIGN32( sh4r.r[Rm] );
  1091                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
  1092                                 sh4r.r[Rm] += 4;
  1094                                 break;
  1095                             case 0x3:
  1096                                 { /* LDC.L @Rm+, SGR */
  1097                                 uint32_t Rm = ((ir>>8)&0xF); 
  1098                                 CHECKPRIV();
  1099                                 CHECKRALIGN32( sh4r.r[Rm] );
  1100                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
  1101                                 sh4r.r[Rm] +=4;
  1103                                 break;
  1104                             case 0x5:
  1105                                 { /* LDS.L @Rm+, FPUL */
  1106                                 uint32_t Rm = ((ir>>8)&0xF); 
  1107                                 CHECKFPUEN();
  1108                                 CHECKRALIGN32( sh4r.r[Rm] );
  1109                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
  1110                                 sh4r.r[Rm] +=4;
  1112                                 break;
  1113                             case 0x6:
  1114                                 { /* LDS.L @Rm+, FPSCR */
  1115                                 uint32_t Rm = ((ir>>8)&0xF); 
  1116                                 CHECKFPUEN();
  1117                                 CHECKRALIGN32( sh4r.r[Rm] );
  1118                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
  1119                                 sh4r.r[Rm] +=4;
  1120                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1122                                 break;
  1123                             case 0xF:
  1124                                 { /* LDC.L @Rm+, DBR */
  1125                                 uint32_t Rm = ((ir>>8)&0xF); 
  1126                                 CHECKPRIV();
  1127                                 CHECKRALIGN32( sh4r.r[Rm] );
  1128                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
  1129                                 sh4r.r[Rm] +=4;
  1131                                 break;
  1132                             default:
  1133                                 UNDEF();
  1134                                 break;
  1136                         break;
  1137                     case 0x7:
  1138                         switch( (ir&0x80) >> 7 ) {
  1139                             case 0x0:
  1140                                 switch( (ir&0x70) >> 4 ) {
  1141                                     case 0x0:
  1142                                         { /* LDC.L @Rm+, SR */
  1143                                         uint32_t Rm = ((ir>>8)&0xF); 
  1144                                         CHECKSLOTILLEGAL();
  1145                                         CHECKPRIV();
  1146                                         CHECKWALIGN32( sh4r.r[Rm] );
  1147                                         MEM_READ_LONG(sh4r.r[Rm], tmp);
  1148                                         sh4_write_sr( tmp );
  1149                                         sh4r.r[Rm] +=4;
  1151                                         break;
  1152                                     case 0x1:
  1153                                         { /* LDC.L @Rm+, GBR */
  1154                                         uint32_t Rm = ((ir>>8)&0xF); 
  1155                                         CHECKRALIGN32( sh4r.r[Rm] );
  1156                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
  1157                                         sh4r.r[Rm] +=4;
  1159                                         break;
  1160                                     case 0x2:
  1161                                         { /* LDC.L @Rm+, VBR */
  1162                                         uint32_t Rm = ((ir>>8)&0xF); 
  1163                                         CHECKPRIV();
  1164                                         CHECKRALIGN32( sh4r.r[Rm] );
  1165                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
  1166                                         sh4r.r[Rm] +=4;
  1168                                         break;
  1169                                     case 0x3:
  1170                                         { /* LDC.L @Rm+, SSR */
  1171                                         uint32_t Rm = ((ir>>8)&0xF); 
  1172                                         CHECKPRIV();
  1173                                         CHECKRALIGN32( sh4r.r[Rm] );
  1174                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
  1175                                         sh4r.r[Rm] +=4;
  1177                                         break;
  1178                                     case 0x4:
  1179                                         { /* LDC.L @Rm+, SPC */
  1180                                         uint32_t Rm = ((ir>>8)&0xF); 
  1181                                         CHECKPRIV();
  1182                                         CHECKRALIGN32( sh4r.r[Rm] );
  1183                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
  1184                                         sh4r.r[Rm] +=4;
  1186                                         break;
  1187                                     default:
  1188                                         UNDEF();
  1189                                         break;
  1191                                 break;
  1192                             case 0x1:
  1193                                 { /* LDC.L @Rm+, Rn_BANK */
  1194                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1195                                 CHECKPRIV();
  1196                                 CHECKRALIGN32( sh4r.r[Rm] );
  1197                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
  1198                                 sh4r.r[Rm] += 4;
  1200                                 break;
  1202                         break;
  1203                     case 0x8:
  1204                         switch( (ir&0xF0) >> 4 ) {
  1205                             case 0x0:
  1206                                 { /* SHLL2 Rn */
  1207                                 uint32_t Rn = ((ir>>8)&0xF); 
  1208                                 sh4r.r[Rn] <<= 2;
  1210                                 break;
  1211                             case 0x1:
  1212                                 { /* SHLL8 Rn */
  1213                                 uint32_t Rn = ((ir>>8)&0xF); 
  1214                                 sh4r.r[Rn] <<= 8;
  1216                                 break;
  1217                             case 0x2:
  1218                                 { /* SHLL16 Rn */
  1219                                 uint32_t Rn = ((ir>>8)&0xF); 
  1220                                 sh4r.r[Rn] <<= 16;
  1222                                 break;
  1223                             default:
  1224                                 UNDEF();
  1225                                 break;
  1227                         break;
  1228                     case 0x9:
  1229                         switch( (ir&0xF0) >> 4 ) {
  1230                             case 0x0:
  1231                                 { /* SHLR2 Rn */
  1232                                 uint32_t Rn = ((ir>>8)&0xF); 
  1233                                 sh4r.r[Rn] >>= 2;
  1235                                 break;
  1236                             case 0x1:
  1237                                 { /* SHLR8 Rn */
  1238                                 uint32_t Rn = ((ir>>8)&0xF); 
  1239                                 sh4r.r[Rn] >>= 8;
  1241                                 break;
  1242                             case 0x2:
  1243                                 { /* SHLR16 Rn */
  1244                                 uint32_t Rn = ((ir>>8)&0xF); 
  1245                                 sh4r.r[Rn] >>= 16;
  1247                                 break;
  1248                             default:
  1249                                 UNDEF();
  1250                                 break;
  1252                         break;
  1253                     case 0xA:
  1254                         switch( (ir&0xF0) >> 4 ) {
  1255                             case 0x0:
  1256                                 { /* LDS Rm, MACH */
  1257                                 uint32_t Rm = ((ir>>8)&0xF); 
  1258                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1259                                            (((uint64_t)sh4r.r[Rm])<<32);
  1261                                 break;
  1262                             case 0x1:
  1263                                 { /* LDS Rm, MACL */
  1264                                 uint32_t Rm = ((ir>>8)&0xF); 
  1265                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1266                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));
  1268                                 break;
  1269                             case 0x2:
  1270                                 { /* LDS Rm, PR */
  1271                                 uint32_t Rm = ((ir>>8)&0xF); 
  1272                                 sh4r.pr = sh4r.r[Rm];
  1274                                 break;
  1275                             case 0x3:
  1276                                 { /* LDC Rm, SGR */
  1277                                 uint32_t Rm = ((ir>>8)&0xF); 
  1278                                 CHECKPRIV();
  1279                                 sh4r.sgr = sh4r.r[Rm];
  1281                                 break;
  1282                             case 0x5:
  1283                                 { /* LDS Rm, FPUL */
  1284                                 uint32_t Rm = ((ir>>8)&0xF); 
  1285                                 CHECKFPUEN();
  1286                                 sh4r.fpul = sh4r.r[Rm];
  1288                                 break;
  1289                             case 0x6:
  1290                                 { /* LDS Rm, FPSCR */
  1291                                 uint32_t Rm = ((ir>>8)&0xF); 
  1292                                 CHECKFPUEN();
  1293                                 sh4r.fpscr = sh4r.r[Rm]; 
  1294                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1296                                 break;
  1297                             case 0xF:
  1298                                 { /* LDC Rm, DBR */
  1299                                 uint32_t Rm = ((ir>>8)&0xF); 
  1300                                 CHECKPRIV();
  1301                                 sh4r.dbr = sh4r.r[Rm];
  1303                                 break;
  1304                             default:
  1305                                 UNDEF();
  1306                                 break;
  1308                         break;
  1309                     case 0xB:
  1310                         switch( (ir&0xF0) >> 4 ) {
  1311                             case 0x0:
  1312                                 { /* JSR @Rn */
  1313                                 uint32_t Rn = ((ir>>8)&0xF); 
  1314                                 CHECKDEST( sh4r.r[Rn] );
  1315                                 CHECKSLOTILLEGAL();
  1316                                 sh4r.in_delay_slot = 1;
  1317                                 sh4r.pc = sh4r.new_pc;
  1318                                 sh4r.new_pc = sh4r.r[Rn];
  1319                                 sh4r.pr = pc + 4;
  1320                                 TRACE_CALL( pc, sh4r.new_pc );
  1321                                 return TRUE;
  1323                                 break;
  1324                             case 0x1:
  1325                                 { /* TAS.B @Rn */
  1326                                 uint32_t Rn = ((ir>>8)&0xF); 
  1327                                 MEM_READ_BYTE( sh4r.r[Rn], tmp );
  1328                                 sh4r.t = ( tmp == 0 ? 1 : 0 );
  1329                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
  1331                                 break;
  1332                             case 0x2:
  1333                                 { /* JMP @Rn */
  1334                                 uint32_t Rn = ((ir>>8)&0xF); 
  1335                                 CHECKDEST( sh4r.r[Rn] );
  1336                                 CHECKSLOTILLEGAL();
  1337                                 sh4r.in_delay_slot = 1;
  1338                                 sh4r.pc = sh4r.new_pc;
  1339                                 sh4r.new_pc = sh4r.r[Rn];
  1340                                 return TRUE;
  1342                                 break;
  1343                             default:
  1344                                 UNDEF();
  1345                                 break;
  1347                         break;
  1348                     case 0xC:
  1349                         { /* SHAD Rm, Rn */
  1350                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1351                         tmp = sh4r.r[Rm];
  1352                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1353                         else if( (tmp & 0x1F) == 0 )  
  1354                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
  1355                         else 
  1356                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
  1358                         break;
  1359                     case 0xD:
  1360                         { /* SHLD Rm, Rn */
  1361                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1362                         tmp = sh4r.r[Rm];
  1363                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1364                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
  1365                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
  1367                         break;
  1368                     case 0xE:
  1369                         switch( (ir&0x80) >> 7 ) {
  1370                             case 0x0:
  1371                                 switch( (ir&0x70) >> 4 ) {
  1372                                     case 0x0:
  1373                                         { /* LDC Rm, SR */
  1374                                         uint32_t Rm = ((ir>>8)&0xF); 
  1375                                         CHECKSLOTILLEGAL();
  1376                                         CHECKPRIV();
  1377                                         sh4_write_sr( sh4r.r[Rm] );
  1379                                         break;
  1380                                     case 0x1:
  1381                                         { /* LDC Rm, GBR */
  1382                                         uint32_t Rm = ((ir>>8)&0xF); 
  1383                                         sh4r.gbr = sh4r.r[Rm];
  1385                                         break;
  1386                                     case 0x2:
  1387                                         { /* LDC Rm, VBR */
  1388                                         uint32_t Rm = ((ir>>8)&0xF); 
  1389                                         CHECKPRIV();
  1390                                         sh4r.vbr = sh4r.r[Rm];
  1392                                         break;
  1393                                     case 0x3:
  1394                                         { /* LDC Rm, SSR */
  1395                                         uint32_t Rm = ((ir>>8)&0xF); 
  1396                                         CHECKPRIV();
  1397                                         sh4r.ssr = sh4r.r[Rm];
  1399                                         break;
  1400                                     case 0x4:
  1401                                         { /* LDC Rm, SPC */
  1402                                         uint32_t Rm = ((ir>>8)&0xF); 
  1403                                         CHECKPRIV();
  1404                                         sh4r.spc = sh4r.r[Rm];
  1406                                         break;
  1407                                     default:
  1408                                         UNDEF();
  1409                                         break;
  1411                                 break;
  1412                             case 0x1:
  1413                                 { /* LDC Rm, Rn_BANK */
  1414                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1415                                 CHECKPRIV();
  1416                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1418                                 break;
  1420                         break;
  1421                     case 0xF:
  1422                         { /* MAC.W @Rm+, @Rn+ */
  1423                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1424                         int32_t stmp;
  1425                         if( Rm == Rn ) {
  1426                     	CHECKRALIGN16(sh4r.r[Rn]);
  1427                     	MEM_READ_WORD( sh4r.r[Rn], tmp );
  1428                     	stmp = SIGNEXT16(tmp);
  1429                     	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
  1430                     	stmp *= SIGNEXT16(tmp);
  1431                     	sh4r.r[Rn] += 4;
  1432                         } else {
  1433                     	CHECKRALIGN16( sh4r.r[Rn] );
  1434                     	CHECKRALIGN16( sh4r.r[Rm] );
  1435                     	MEM_READ_WORD(sh4r.r[Rn], tmp);
  1436                     	stmp = SIGNEXT16(tmp);
  1437                     	MEM_READ_WORD(sh4r.r[Rm], tmp);
  1438                     	stmp = stmp * SIGNEXT16(tmp);
  1439                     	sh4r.r[Rn] += 2;
  1440                     	sh4r.r[Rm] += 2;
  1442                         if( sh4r.s ) {
  1443                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
  1444                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
  1445                     	    sh4r.mac = 0x000000017FFFFFFFLL;
  1446                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
  1447                     	    sh4r.mac = 0x0000000180000000LL;
  1448                     	} else {
  1449                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1450                     		((uint32_t)(sh4r.mac + stmp));
  1452                         } else {
  1453                     	sh4r.mac += SIGNEXT32(stmp);
  1456                         break;
  1458                 break;
  1459             case 0x5:
  1460                 { /* MOV.L @(disp, Rm), Rn */
  1461                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  1462                 tmp = sh4r.r[Rm] + disp;
  1463                 CHECKRALIGN32( tmp );
  1464                 MEM_READ_LONG( tmp, sh4r.r[Rn] );
  1466                 break;
  1467             case 0x6:
  1468                 switch( ir&0xF ) {
  1469                     case 0x0:
  1470                         { /* MOV.B @Rm, Rn */
  1471                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1472                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] );
  1474                         break;
  1475                     case 0x1:
  1476                         { /* MOV.W @Rm, Rn */
  1477                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1478                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] );
  1480                         break;
  1481                     case 0x2:
  1482                         { /* MOV.L @Rm, Rn */
  1483                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1484                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] );
  1486                         break;
  1487                     case 0x3:
  1488                         { /* MOV Rm, Rn */
  1489                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1490                         sh4r.r[Rn] = sh4r.r[Rm];
  1492                         break;
  1493                     case 0x4:
  1494                         { /* MOV.B @Rm+, Rn */
  1495                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1496                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++;
  1498                         break;
  1499                     case 0x5:
  1500                         { /* MOV.W @Rm+, Rn */
  1501                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1502                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2;
  1504                         break;
  1505                     case 0x6:
  1506                         { /* MOV.L @Rm+, Rn */
  1507                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1508                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4;
  1510                         break;
  1511                     case 0x7:
  1512                         { /* NOT Rm, Rn */
  1513                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1514                         sh4r.r[Rn] = ~sh4r.r[Rm];
  1516                         break;
  1517                     case 0x8:
  1518                         { /* SWAP.B Rm, Rn */
  1519                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1520                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
  1522                         break;
  1523                     case 0x9:
  1524                         { /* SWAP.W Rm, Rn */
  1525                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1526                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
  1528                         break;
  1529                     case 0xA:
  1530                         { /* NEGC Rm, Rn */
  1531                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1532                         tmp = 0 - sh4r.r[Rm];
  1533                         sh4r.r[Rn] = tmp - sh4r.t;
  1534                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
  1536                         break;
  1537                     case 0xB:
  1538                         { /* NEG Rm, Rn */
  1539                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1540                         sh4r.r[Rn] = 0 - sh4r.r[Rm];
  1542                         break;
  1543                     case 0xC:
  1544                         { /* EXTU.B Rm, Rn */
  1545                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1546                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
  1548                         break;
  1549                     case 0xD:
  1550                         { /* EXTU.W Rm, Rn */
  1551                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1552                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
  1554                         break;
  1555                     case 0xE:
  1556                         { /* EXTS.B Rm, Rn */
  1557                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1558                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
  1560                         break;
  1561                     case 0xF:
  1562                         { /* EXTS.W Rm, Rn */
  1563                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1564                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
  1566                         break;
  1568                 break;
  1569             case 0x7:
  1570                 { /* ADD #imm, Rn */
  1571                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1572                 sh4r.r[Rn] += imm;
  1574                 break;
  1575             case 0x8:
  1576                 switch( (ir&0xF00) >> 8 ) {
  1577                     case 0x0:
  1578                         { /* MOV.B R0, @(disp, Rn) */
  1579                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1580                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
  1582                         break;
  1583                     case 0x1:
  1584                         { /* MOV.W R0, @(disp, Rn) */
  1585                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1586                         tmp = sh4r.r[Rn] + disp;
  1587                         CHECKWALIGN16( tmp );
  1588                         MEM_WRITE_WORD( tmp, R0 );
  1590                         break;
  1591                     case 0x4:
  1592                         { /* MOV.B @(disp, Rm), R0 */
  1593                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1594                         MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 );
  1596                         break;
  1597                     case 0x5:
  1598                         { /* MOV.W @(disp, Rm), R0 */
  1599                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1600                         tmp = sh4r.r[Rm] + disp;
  1601                         CHECKRALIGN16( tmp );
  1602                         MEM_READ_WORD( tmp, R0 );
  1604                         break;
  1605                     case 0x8:
  1606                         { /* CMP/EQ #imm, R0 */
  1607                         int32_t imm = SIGNEXT8(ir&0xFF); 
  1608                         sh4r.t = ( R0 == imm ? 1 : 0 );
  1610                         break;
  1611                     case 0x9:
  1612                         { /* BT disp */
  1613                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1614                         CHECKSLOTILLEGAL();
  1615                         if( sh4r.t ) {
  1616                             CHECKDEST( sh4r.pc + disp + 4 )
  1617                             sh4r.pc += disp + 4;
  1618                             sh4r.new_pc = sh4r.pc + 2;
  1619                             return TRUE;
  1622                         break;
  1623                     case 0xB:
  1624                         { /* BF disp */
  1625                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1626                         CHECKSLOTILLEGAL();
  1627                         if( !sh4r.t ) {
  1628                             CHECKDEST( sh4r.pc + disp + 4 )
  1629                             sh4r.pc += disp + 4;
  1630                             sh4r.new_pc = sh4r.pc + 2;
  1631                             return TRUE;
  1634                         break;
  1635                     case 0xD:
  1636                         { /* BT/S disp */
  1637                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1638                         CHECKSLOTILLEGAL();
  1639                         if( sh4r.t ) {
  1640                             CHECKDEST( sh4r.pc + disp + 4 )
  1641                             sh4r.in_delay_slot = 1;
  1642                             sh4r.pc = sh4r.new_pc;
  1643                             sh4r.new_pc = pc + disp + 4;
  1644                             sh4r.in_delay_slot = 1;
  1645                             return TRUE;
  1648                         break;
  1649                     case 0xF:
  1650                         { /* BF/S disp */
  1651                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1652                         CHECKSLOTILLEGAL();
  1653                         if( !sh4r.t ) {
  1654                             CHECKDEST( sh4r.pc + disp + 4 )
  1655                             sh4r.in_delay_slot = 1;
  1656                             sh4r.pc = sh4r.new_pc;
  1657                             sh4r.new_pc = pc + disp + 4;
  1658                             return TRUE;
  1661                         break;
  1662                     default:
  1663                         UNDEF();
  1664                         break;
  1666                 break;
  1667             case 0x9:
  1668                 { /* MOV.W @(disp, PC), Rn */
  1669                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  1670                 CHECKSLOTILLEGAL();
  1671                 tmp = pc + 4 + disp;
  1672                 MEM_READ_WORD( tmp, sh4r.r[Rn] );
  1674                 break;
  1675             case 0xA:
  1676                 { /* BRA disp */
  1677                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1678                 CHECKSLOTILLEGAL();
  1679                 CHECKDEST( sh4r.pc + disp + 4 );
  1680                 sh4r.in_delay_slot = 1;
  1681                 sh4r.pc = sh4r.new_pc;
  1682                 sh4r.new_pc = pc + 4 + disp;
  1683                 return TRUE;
  1685                 break;
  1686             case 0xB:
  1687                 { /* BSR disp */
  1688                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1689                 CHECKDEST( sh4r.pc + disp + 4 );
  1690                 CHECKSLOTILLEGAL();
  1691                 sh4r.in_delay_slot = 1;
  1692                 sh4r.pr = pc + 4;
  1693                 sh4r.pc = sh4r.new_pc;
  1694                 sh4r.new_pc = pc + 4 + disp;
  1695                 TRACE_CALL( pc, sh4r.new_pc );
  1696                 return TRUE;
  1698                 break;
  1699             case 0xC:
  1700                 switch( (ir&0xF00) >> 8 ) {
  1701                     case 0x0:
  1702                         { /* MOV.B R0, @(disp, GBR) */
  1703                         uint32_t disp = (ir&0xFF); 
  1704                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
  1706                         break;
  1707                     case 0x1:
  1708                         { /* MOV.W R0, @(disp, GBR) */
  1709                         uint32_t disp = (ir&0xFF)<<1; 
  1710                         tmp = sh4r.gbr + disp;
  1711                         CHECKWALIGN16( tmp );
  1712                         MEM_WRITE_WORD( tmp, R0 );
  1714                         break;
  1715                     case 0x2:
  1716                         { /* MOV.L R0, @(disp, GBR) */
  1717                         uint32_t disp = (ir&0xFF)<<2; 
  1718                         tmp = sh4r.gbr + disp;
  1719                         CHECKWALIGN32( tmp );
  1720                         MEM_WRITE_LONG( tmp, R0 );
  1722                         break;
  1723                     case 0x3:
  1724                         { /* TRAPA #imm */
  1725                         uint32_t imm = (ir&0xFF); 
  1726                         CHECKSLOTILLEGAL();
  1727                         sh4r.pc += 2;
  1728                         sh4_raise_trap( imm );
  1729                         return TRUE;
  1731                         break;
  1732                     case 0x4:
  1733                         { /* MOV.B @(disp, GBR), R0 */
  1734                         uint32_t disp = (ir&0xFF); 
  1735                         MEM_READ_BYTE( sh4r.gbr + disp, R0 );
  1737                         break;
  1738                     case 0x5:
  1739                         { /* MOV.W @(disp, GBR), R0 */
  1740                         uint32_t disp = (ir&0xFF)<<1; 
  1741                         tmp = sh4r.gbr + disp;
  1742                         CHECKRALIGN16( tmp );
  1743                         MEM_READ_WORD( tmp, R0 );
  1745                         break;
  1746                     case 0x6:
  1747                         { /* MOV.L @(disp, GBR), R0 */
  1748                         uint32_t disp = (ir&0xFF)<<2; 
  1749                         tmp = sh4r.gbr + disp;
  1750                         CHECKRALIGN32( tmp );
  1751                         MEM_READ_LONG( tmp, R0 );
  1753                         break;
  1754                     case 0x7:
  1755                         { /* MOVA @(disp, PC), R0 */
  1756                         uint32_t disp = (ir&0xFF)<<2; 
  1757                         CHECKSLOTILLEGAL();
  1758                         R0 = (pc&0xFFFFFFFC) + disp + 4;
  1760                         break;
  1761                     case 0x8:
  1762                         { /* TST #imm, R0 */
  1763                         uint32_t imm = (ir&0xFF); 
  1764                         sh4r.t = (R0 & imm ? 0 : 1);
  1766                         break;
  1767                     case 0x9:
  1768                         { /* AND #imm, R0 */
  1769                         uint32_t imm = (ir&0xFF); 
  1770                         R0 &= imm;
  1772                         break;
  1773                     case 0xA:
  1774                         { /* XOR #imm, R0 */
  1775                         uint32_t imm = (ir&0xFF); 
  1776                         R0 ^= imm;
  1778                         break;
  1779                     case 0xB:
  1780                         { /* OR #imm, R0 */
  1781                         uint32_t imm = (ir&0xFF); 
  1782                         R0 |= imm;
  1784                         break;
  1785                     case 0xC:
  1786                         { /* TST.B #imm, @(R0, GBR) */
  1787                         uint32_t imm = (ir&0xFF); 
  1788                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 );
  1790                         break;
  1791                     case 0xD:
  1792                         { /* AND.B #imm, @(R0, GBR) */
  1793                         uint32_t imm = (ir&0xFF); 
  1794                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp );
  1796                         break;
  1797                     case 0xE:
  1798                         { /* XOR.B #imm, @(R0, GBR) */
  1799                         uint32_t imm = (ir&0xFF); 
  1800                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp );
  1802                         break;
  1803                     case 0xF:
  1804                         { /* OR.B #imm, @(R0, GBR) */
  1805                         uint32_t imm = (ir&0xFF); 
  1806                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp );
  1808                         break;
  1810                 break;
  1811             case 0xD:
  1812                 { /* MOV.L @(disp, PC), Rn */
  1813                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  1814                 CHECKSLOTILLEGAL();
  1815                 tmp = (pc&0xFFFFFFFC) + disp + 4;
  1816                 MEM_READ_LONG( tmp, sh4r.r[Rn] );
  1818                 break;
  1819             case 0xE:
  1820                 { /* MOV #imm, Rn */
  1821                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1822                 sh4r.r[Rn] = imm;
  1824                 break;
  1825             case 0xF:
  1826                 switch( ir&0xF ) {
  1827                     case 0x0:
  1828                         { /* FADD FRm, FRn */
  1829                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1830                         CHECKFPUEN();
  1831                         if( IS_FPU_DOUBLEPREC() ) {
  1832                     	DR(FRn) += DR(FRm);
  1833                         } else {
  1834                     	FR(FRn) += FR(FRm);
  1837                         break;
  1838                     case 0x1:
  1839                         { /* FSUB FRm, FRn */
  1840                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1841                         CHECKFPUEN();
  1842                         if( IS_FPU_DOUBLEPREC() ) {
  1843                     	DR(FRn) -= DR(FRm);
  1844                         } else {
  1845                     	FR(FRn) -= FR(FRm);
  1848                         break;
  1849                     case 0x2:
  1850                         { /* FMUL FRm, FRn */
  1851                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1852                         CHECKFPUEN();
  1853                         if( IS_FPU_DOUBLEPREC() ) {
  1854                     	DR(FRn) *= DR(FRm);
  1855                         } else {
  1856                     	FR(FRn) *= FR(FRm);
  1859                         break;
  1860                     case 0x3:
  1861                         { /* FDIV FRm, FRn */
  1862                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1863                         CHECKFPUEN();
  1864                         if( IS_FPU_DOUBLEPREC() ) {
  1865                     	DR(FRn) /= DR(FRm);
  1866                         } else {
  1867                     	FR(FRn) /= FR(FRm);
  1870                         break;
  1871                     case 0x4:
  1872                         { /* FCMP/EQ FRm, FRn */
  1873                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1874                         CHECKFPUEN();
  1875                         if( IS_FPU_DOUBLEPREC() ) {
  1876                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1877                         } else {
  1878                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1881                         break;
  1882                     case 0x5:
  1883                         { /* FCMP/GT FRm, FRn */
  1884                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1885                         CHECKFPUEN();
  1886                         if( IS_FPU_DOUBLEPREC() ) {
  1887                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1888                         } else {
  1889                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1892                         break;
  1893                     case 0x6:
  1894                         { /* FMOV @(R0, Rm), FRn */
  1895                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1896                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
  1898                         break;
  1899                     case 0x7:
  1900                         { /* FMOV FRm, @(R0, Rn) */
  1901                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1902                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
  1904                         break;
  1905                     case 0x8:
  1906                         { /* FMOV @Rm, FRn */
  1907                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1908                         MEM_FP_READ( sh4r.r[Rm], FRn );
  1910                         break;
  1911                     case 0x9:
  1912                         { /* FMOV @Rm+, FRn */
  1913                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1914                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
  1916                         break;
  1917                     case 0xA:
  1918                         { /* FMOV FRm, @Rn */
  1919                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1920                         MEM_FP_WRITE( sh4r.r[Rn], FRm );
  1922                         break;
  1923                     case 0xB:
  1924                         { /* FMOV FRm, @-Rn */
  1925                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1926                         MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH;
  1928                         break;
  1929                     case 0xC:
  1930                         { /* FMOV FRm, FRn */
  1931                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1932                         if( IS_FPU_DOUBLESIZE() )
  1933                     	DR(FRn) = DR(FRm);
  1934                         else
  1935                     	FR(FRn) = FR(FRm);
  1937                         break;
  1938                     case 0xD:
  1939                         switch( (ir&0xF0) >> 4 ) {
  1940                             case 0x0:
  1941                                 { /* FSTS FPUL, FRn */
  1942                                 uint32_t FRn = ((ir>>8)&0xF); 
  1943                                 CHECKFPUEN(); FR(FRn) = FPULf;
  1945                                 break;
  1946                             case 0x1:
  1947                                 { /* FLDS FRm, FPUL */
  1948                                 uint32_t FRm = ((ir>>8)&0xF); 
  1949                                 CHECKFPUEN(); FPULf = FR(FRm);
  1951                                 break;
  1952                             case 0x2:
  1953                                 { /* FLOAT FPUL, FRn */
  1954                                 uint32_t FRn = ((ir>>8)&0xF); 
  1955                                 CHECKFPUEN();
  1956                                 if( IS_FPU_DOUBLEPREC() ) {
  1957                             	if( FRn&1 ) { // No, really...
  1958                             	    dtmp = (double)FPULi;
  1959                             	    FR(FRn) = *(((float *)&dtmp)+1);
  1960                             	} else {
  1961                             	    DRF(FRn>>1) = (double)FPULi;
  1963                                 } else {
  1964                             	FR(FRn) = (float)FPULi;
  1967                                 break;
  1968                             case 0x3:
  1969                                 { /* FTRC FRm, FPUL */
  1970                                 uint32_t FRm = ((ir>>8)&0xF); 
  1971                                 CHECKFPUEN();
  1972                                 if( IS_FPU_DOUBLEPREC() ) {
  1973                             	if( FRm&1 ) {
  1974                             	    dtmp = 0;
  1975                             	    *(((float *)&dtmp)+1) = FR(FRm);
  1976                             	} else {
  1977                             	    dtmp = DRF(FRm>>1);
  1979                                     if( dtmp >= MAX_INTF )
  1980                                         FPULi = MAX_INT;
  1981                                     else if( dtmp <= MIN_INTF )
  1982                                         FPULi = MIN_INT;
  1983                                     else 
  1984                                         FPULi = (int32_t)dtmp;
  1985                                 } else {
  1986                             	ftmp = FR(FRm);
  1987                             	if( ftmp >= MAX_INTF )
  1988                             	    FPULi = MAX_INT;
  1989                             	else if( ftmp <= MIN_INTF )
  1990                             	    FPULi = MIN_INT;
  1991                             	else
  1992                             	    FPULi = (int32_t)ftmp;
  1995                                 break;
  1996                             case 0x4:
  1997                                 { /* FNEG FRn */
  1998                                 uint32_t FRn = ((ir>>8)&0xF); 
  1999                                 CHECKFPUEN();
  2000                                 if( IS_FPU_DOUBLEPREC() ) {
  2001                             	DR(FRn) = -DR(FRn);
  2002                                 } else {
  2003                                     FR(FRn) = -FR(FRn);
  2006                                 break;
  2007                             case 0x5:
  2008                                 { /* FABS FRn */
  2009                                 uint32_t FRn = ((ir>>8)&0xF); 
  2010                                 CHECKFPUEN();
  2011                                 if( IS_FPU_DOUBLEPREC() ) {
  2012                             	DR(FRn) = fabs(DR(FRn));
  2013                                 } else {
  2014                                     FR(FRn) = fabsf(FR(FRn));
  2017                                 break;
  2018                             case 0x6:
  2019                                 { /* FSQRT FRn */
  2020                                 uint32_t FRn = ((ir>>8)&0xF); 
  2021                                 CHECKFPUEN();
  2022                                 if( IS_FPU_DOUBLEPREC() ) {
  2023                             	DR(FRn) = sqrt(DR(FRn));
  2024                                 } else {
  2025                                     FR(FRn) = sqrtf(FR(FRn));
  2028                                 break;
  2029                             case 0x7:
  2030                                 { /* FSRRA FRn */
  2031                                 uint32_t FRn = ((ir>>8)&0xF); 
  2032                                 CHECKFPUEN();
  2033                                 if( !IS_FPU_DOUBLEPREC() ) {
  2034                             	FR(FRn) = 1.0/sqrtf(FR(FRn));
  2037                                 break;
  2038                             case 0x8:
  2039                                 { /* FLDI0 FRn */
  2040                                 uint32_t FRn = ((ir>>8)&0xF); 
  2041                                 CHECKFPUEN();
  2042                                 if( IS_FPU_DOUBLEPREC() ) {
  2043                             	DR(FRn) = 0.0;
  2044                                 } else {
  2045                                     FR(FRn) = 0.0;
  2048                                 break;
  2049                             case 0x9:
  2050                                 { /* FLDI1 FRn */
  2051                                 uint32_t FRn = ((ir>>8)&0xF); 
  2052                                 CHECKFPUEN();
  2053                                 if( IS_FPU_DOUBLEPREC() ) {
  2054                             	DR(FRn) = 1.0;
  2055                                 } else {
  2056                                     FR(FRn) = 1.0;
  2059                                 break;
  2060                             case 0xA:
  2061                                 { /* FCNVSD FPUL, FRn */
  2062                                 uint32_t FRn = ((ir>>8)&0xF); 
  2063                                 CHECKFPUEN();
  2064                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2065                             	DR(FRn) = (double)FPULf;
  2068                                 break;
  2069                             case 0xB:
  2070                                 { /* FCNVDS FRm, FPUL */
  2071                                 uint32_t FRm = ((ir>>8)&0xF); 
  2072                                 CHECKFPUEN();
  2073                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2074                             	FPULf = (float)DR(FRm);
  2077                                 break;
  2078                             case 0xE:
  2079                                 { /* FIPR FVm, FVn */
  2080                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  2081                                 CHECKFPUEN();
  2082                                 if( !IS_FPU_DOUBLEPREC() ) {
  2083                                     int tmp2 = FVn<<2;
  2084                                     tmp = FVm<<2;
  2085                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  2086                                         FR(tmp+1)*FR(tmp2+1) +
  2087                                         FR(tmp+2)*FR(tmp2+2) +
  2088                                         FR(tmp+3)*FR(tmp2+3);
  2091                                 break;
  2092                             case 0xF:
  2093                                 switch( (ir&0x100) >> 8 ) {
  2094                                     case 0x0:
  2095                                         { /* FSCA FPUL, FRn */
  2096                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  2097                                         CHECKFPUEN();
  2098                                         if( !IS_FPU_DOUBLEPREC() ) {
  2099                                     	sh4_fsca( FPULi, &(DRF(FRn>>1)) );
  2100                                     	/*
  2101                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  2102                                             FR(FRn) = sinf(angle);
  2103                                             FR((FRn)+1) = cosf(angle);
  2104                                     	*/
  2107                                         break;
  2108                                     case 0x1:
  2109                                         switch( (ir&0x200) >> 9 ) {
  2110                                             case 0x0:
  2111                                                 { /* FTRV XMTRX, FVn */
  2112                                                 uint32_t FVn = ((ir>>10)&0x3); 
  2113                                                 CHECKFPUEN();
  2114                                                 if( !IS_FPU_DOUBLEPREC() ) {
  2115                                             	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
  2116                                             	/*
  2117                                                     tmp = FVn<<2;
  2118                                             	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
  2119                                                     float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  2120                                                     FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
  2121                                             	    xf[9]*fv[2] + xf[13]*fv[3];
  2122                                                     FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
  2123                                             	    xf[8]*fv[2] + xf[12]*fv[3];
  2124                                                     FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
  2125                                             	    xf[11]*fv[2] + xf[15]*fv[3];
  2126                                                     FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
  2127                                             	    xf[10]*fv[2] + xf[14]*fv[3];
  2128                                             	*/
  2131                                                 break;
  2132                                             case 0x1:
  2133                                                 switch( (ir&0xC00) >> 10 ) {
  2134                                                     case 0x0:
  2135                                                         { /* FSCHG */
  2136                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
  2138                                                         break;
  2139                                                     case 0x2:
  2140                                                         { /* FRCHG */
  2141                                                         CHECKFPUEN(); 
  2142                                                         sh4r.fpscr ^= FPSCR_FR; 
  2143                                                         sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  2145                                                         break;
  2146                                                     case 0x3:
  2147                                                         { /* UNDEF */
  2148                                                         UNDEF(ir);
  2150                                                         break;
  2151                                                     default:
  2152                                                         UNDEF();
  2153                                                         break;
  2155                                                 break;
  2157                                         break;
  2159                                 break;
  2160                             default:
  2161                                 UNDEF();
  2162                                 break;
  2164                         break;
  2165                     case 0xE:
  2166                         { /* FMAC FR0, FRm, FRn */
  2167                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2168                         CHECKFPUEN();
  2169                         if( IS_FPU_DOUBLEPREC() ) {
  2170                             DR(FRn) += DR(FRm)*DR(0);
  2171                         } else {
  2172                     	FR(FRn) += FR(FRm)*FR(0);
  2175                         break;
  2176                     default:
  2177                         UNDEF();
  2178                         break;
  2180                 break;
  2183     sh4r.pc = sh4r.new_pc;
  2184     sh4r.new_pc += 2;
  2185     sh4r.in_delay_slot = 0;
  2186     return TRUE;
.