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lxdream.org :: lxdream/src/aica/armcore.h
lxdream 0.9.1
released Jun 29
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filename src/aica/armcore.h
changeset 736:a02d1475ccfd
prev586:2a3ba82cf243
next814:f1a21df54e19
author nkeynes
date Mon Jul 14 07:44:42 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Re-indent everything consistently
Fix include guards for consistency as well
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     1 /**
     2  * $Id$
     3  * 
     4  * Interface definitions for the ARM CPU emulation core proper.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    19 #ifndef lxdream_armcore_H
    20 #define lxdream_armcore_H 1
    22 #include "lxdream.h"
    23 #include "mem.h"
    24 #include <stdint.h>
    25 #include <stdio.h>
    27 #ifdef __cplusplus
    28 extern "C" {
    29 #endif
    31 #define ARM_BASE_RATE 2 /* MHZ */
    32 extern uint32_t arm_cpu_freq;
    33 extern uint32_t arm_cpu_period;
    35 #define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) )
    37 struct arm_registers {
    38     uint32_t r[16]; /* Current register bank */
    40     uint32_t cpsr;
    41     uint32_t spsr;
    43     /* Various banked versions of the registers. Note that these are used
    44      * to save the registers for the named bank when leaving the mode, they're
    45      * not actually used actively.
    46      **/
    47     uint32_t user_r[7]; /* User/System bank 8..14 */
    48     uint32_t svc_r[3]; /* SVC bank 13..14, SPSR */
    49     uint32_t abt_r[3]; /* ABT bank 13..14, SPSR */
    50     uint32_t und_r[3]; /* UND bank 13..14, SPSR */
    51     uint32_t irq_r[3]; /* IRQ bank 13..14, SPSR */
    52     uint32_t fiq_r[8]; /* FIQ bank 8..14, SPSR */
    54     uint32_t c,n,z,v,t;
    56     /* "fake" registers */
    57     uint32_t int_pending; /* Mask of CPSR_I and CPSR_F */
    58     uint32_t shift_c;  /* used for temporary storage of shifter results */
    59     uint32_t icount; /* Instruction counter */
    60     gboolean running; /* Indicates that the ARM is operational, as opposed to
    61 		       * halted */
    62 };
    64 #define CPSR_N 0x80000000 /* Negative flag */
    65 #define CPSR_Z 0x40000000 /* Zero flag */
    66 #define CPSR_C 0x20000000 /* Carry flag */
    67 #define CPSR_V 0x10000000 /* Overflow flag */
    68 #define CPSR_I 0x00000080 /* Interrupt disable bit */ 
    69 #define CPSR_F 0x00000040 /* Fast interrupt disable bit */
    70 #define CPSR_T 0x00000020 /* Thumb mode */
    71 #define CPSR_MODE 0x0000001F /* Current execution mode */
    72 #define CPSR_COMPACT_MASK 0x0FFFFFDF /* Mask excluding all separated flags */
    74 #define MODE_USER 0x10 /* User mode */
    75 #define MODE_FIQ   0x11 /* Fast IRQ mode */
    76 #define MODE_IRQ  0x12 /* IRQ mode */
    77 #define MODE_SVC  0x13 /* Supervisor mode */
    78 #define MODE_ABT 0x17 /* Abort mode */
    79 #define MODE_UND 0x1B /* Undefined mode */
    80 #define MODE_SYS 0x1F /* System mode */
    82 #define IS_PRIVILEGED_MODE() ((armr.cpsr & CPSR_MODE) != MODE_USER)
    83 #define IS_EXCEPTION_MODE() (IS_PRIVILEGED_MODE() && (armr.cpsr & CPSR_MODE) != MODE_SYS)
    84 #define IS_FIQ_MODE() ((armr.cpsr & CPSR_MODE) == MODE_FIQ)
    86 extern struct arm_registers armr;
    88 #define CARRY_FLAG (armr.cpsr&CPSR_C)
    90 /* ARM core functions */
    91 void arm_reset( void );
    92 uint32_t arm_run_slice( uint32_t nanosecs );
    93 void arm_save_state( FILE *f );
    94 int arm_load_state( FILE *f );
    95 gboolean arm_execute_instruction( void );
    96 void arm_set_breakpoint( uint32_t pc, breakpoint_type_t type );
    97 gboolean arm_clear_breakpoint( uint32_t pc, breakpoint_type_t type );
    98 int arm_get_breakpoint( uint32_t pc );
   100 /* ARM Memory */
   101 uint32_t arm_read_long( uint32_t addr );
   102 uint32_t arm_read_word( uint32_t addr );
   103 uint32_t arm_read_byte( uint32_t addr );
   104 uint32_t arm_read_long_user( uint32_t addr );
   105 uint32_t arm_read_byte_user( uint32_t addr );
   106 void arm_write_long( uint32_t addr, uint32_t val );
   107 void arm_write_word( uint32_t addr, uint32_t val );
   108 void arm_write_byte( uint32_t addr, uint32_t val );
   109 void arm_write_long_user( uint32_t addr, uint32_t val );
   110 void arm_write_byte_user( uint32_t addr, uint32_t val );
   111 int32_t arm_read_phys_word( uint32_t addr );
   112 int arm_has_page( uint32_t addr );
   113 void arm_mem_init(void);
   115 #ifdef __cplusplus
   116 }
   117 #endif
   119 #endif /* !lxdream_armcore_H */
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